Multi-Process Systems: Memory (2) Memory & paging structures: free frames. Memory & paging structures. Physical memory

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1 Multi-Process Systems: Memory (2) What we will learn A detailed description of various ways of organizing memory Discuss various memory-management techniques, including paging and segmentation To provide a description hardware support Address space augmentation: Swapping Address space augmentation: Virtual Memory Background Demand Paging Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating Kernel Memory Other Considerations Operating-System Examples 2 Memory & paging structures Page 0 Page 1 Page 2 Page 3 Page 4 Logical memory (P0) Page 0 Page 1 Logical memory (P1) Page (P0) 8 0 Page (P1) Page frame number Free pages Physical memory Page 1 (P1) Page 4 (P0) Page 1 (P0) Page 2 (P0) Page 0 (P0) Page 0 (P1) Page 3 (P0) Memory & paging structures: free frames Before allocation After allocation 4

2 Implementing page s in software typedef struct { unsigned int frame:22; unsigned int bit : 1; /* 1 => frame is valid */ unsigned int dirty: 1; /* 1 => frame has been updated; needs writing */ unsigned int ref : 1; /* 1 => the page has been referenced */ int cnt; /* how many references */ int first_time; /* swap-in time for page */ int last_time; /* last time referenced */ } page_entry; typedef struct { page_entry entries[maxpages]; } page_; typedef struct { int page; } frame_entry; typedef struct { frame_entry entries[maxframes]; } frame_; page_ *PTBR; frame_ *FTBR; 5 Implementing page s in hardware Page resides in main (physical) memory CPU uses special registers for paging Page base register (PTBR) points to the page Page length register (PTLR) contains length of page : restricts maximum legal logical address Translating an address requires two memory accesses First access reads page entry (PTE) Second access reads the data / instruction from memory Reduce number of memory accesses Can t avoid second access (we need the value from memory) Eliminate first access by keeping a hardware cache (called a translation lookaside buffer or TLB) of recently used page entries Operating Systems and 6 Distributed Systems Implementing page s in hardware Translation Lookaside Buffer (TLB) Search the TLB for the desired logical page number Search entries in parallel Use standard cache techniques If desired logical page number is found, get frame number from TLB If desired logical page number isn t found Get frame number from page in memory Replace an entry in the TLB with the logical & physical page numbers from this reference Logical page # 8 unused Physical frame # Example TLB 7 Operating Systems and 8 Distributed Systems

3 TLB: Associative Memory Paging Hardware With TLB Page # Frame # Associative memory parallel search Handling TLB misses If PTE isn t found in TLB, OS needs to do the lookup in the page Lookup can be done in hardware or software Hardware TLB replacement CPU hardware does page lookup Can be faster than software Less flexible than software, and more complex hardware Software TLB replacement OS gets TLB exception Exception handler does page lookup & places the result into the TLB Program continues after return from exception Larger TLB (lower miss rate) can make this feasible 11 How long do memory accesses take? Assume the following times: TLB lookup time = T TLB (often zero overlapped in CPU) Memory access time = TMEM Hit ratio (h) is percentage of time that a logical page number is found in the TLB Larger TLB usually means higher h TLB structure can affect h as well Effective access time (an average) is calculated as: EAT = (T MEM + T TLB)h + (T MEM + T MEM + T TLB)(1-h) EAT = T TLB + (2-h) T MEM Interpretation Reference always requires TLB lookup, 1 memory access TLB misses also require an additional memory reference Operating Systems and 12Distributed Systems

4 Memory Protection Memory protection implemented by associating protection bit with each frame Valid-invalid bit attached to each entry in the page : valid indicates that the associated page is in the process logical address space, and is thus a legal page invalid indicates that the page is not in the process logical address space Memory Protection Protection D R V Page frame number Valid bit Shared Pages Shared Pages Example Shared code One copy of read-only (re-entrant) code shared among processes (ie, text editors, compilers, window systems) Shared code must appear in same location in the logical address space of all processes Private code and data Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in the logical address space

5 Structure of the Page Table Hierarchical Paging Hashed Page Tables Inverted Page Tables Hierarchical Page Tables Break up the logical address space into multiple page s A simple technique is a two-level page Two-level page s Two-level paging: example Problem: page s can be too large 2 32 bytes in 4KB pages need 1 million PTEs Solution: use multi-level page s Page size in first page is large (megabytes) PTE marked invalid in first page needs no 2nd level page 1st level page has pointers to 2nd level page s 2nd level page has actual physical page numbers in it 1st level page 2nd level page s main memory System characteristics 8 KB pages 32-bit logical address divided into 13 bit page offset, 19 bit page number Page number divided into: 10 bit page number (p1) 9 bit page offset (p2) Logical address looks like this: p 1 is an index into the 1st level page p 2 is an index into the 2nd level page pointed to by p 1 page number page offset p 1 = 10 bits p 2 = 9 bits offset = 13 bits Operating Systems and 19Distributed Systems Operating Systems and 20Distributed Systems

6 2-level address translation example Page base page number page offset p 1 = 10 bits p 2 = 9 bits offset = 13 bits 0 1 p 1 1st level page 0 1 p 2 2nd level page physical address frame number main memory More on two-level page s Trade-off between 1st and 2nd level page sizes Total number of bits indexing 1st and 2nd level is constant for a given page size and logical address length Trade-off between number of bits indexing 1st and number indexing 2nd level s More bits in 1st level: fine granularity at 2nd level Fewer bits in 1st level: maybe less wasted space? All addresses in are physical addresses Protection bits kept in 2nd level 22 Hashed Page Tables Hashed Page Table Common in address spaces > 32 bits The virtual page number is hashed into a page This page contains a chain of elements hashing to the same location Virtual page numbers are compared in this chain searching for a match If a match is found, the corresponding physical frame is extracted

7 Inverted page Reduce page size further: keep one entry for each frame in memory Alternative: merge s for pages in memory and on disk PTE contains Virtual address pointing to this frame Information about the process that owns this page Search page by Hashing the virtual page number and process ID Starting at the entry corresponding to the hash result Search until either the entry is found or a limit is reached Page frame number is index of PTE Improve performance by using more advanced hashing algorithms 25 Inverted page architecture page number process ID p = 19 bits offset = 13 bits pid p search 0 1 k pid 0 pid 1 pid k p 0 p 1 p k inverted page page offset physical address k Page frame number 0 1 main memory Augmenting address space The big picture Swappig Virtual Memory Page request Page replacement Frame allocation User s View of a Program Process address space Memory organization (allocation) Non contiguous allocation Contiguous allocation Fixed dimension Variable dimension Variable partitioning Fixed partitioning Paging Segmentation Dynamic allocation Table based partitioning Paging & Segmentation HW support Limit & relocation registers Dedicated registers Page TLB Segment

8 Segmentation Why use segmentation? Memory-management scheme that supports user view of memory A program is a collection of segments A segment is a logical unit such as:!! main program,!! procedure,!! function,!! method,!! object,!! local variables, global variables,!! common block,!! stack,!! symbol, arrays Allocated Virtual address space Call stack Constants Source text Symbol In use Different units in a single virtual address space Each unit can grow How can they be kept apart? Example: symbol is out of space Solution: segmentation Give each unit its own address space Operating Systems and 30Distributed Systems Using segments Each region of the process has its own segment Each segment can start at 0 Addresses within the segment relative to the segment start Virtual addresses are <segment #, offset within segment> 20K 16K 12K 8K 4K Symbol 0K Segment 0 16K 12K 8K 4K Source text 0K Segment 1 8K 4K Constants 0K Segment 2 12K 8K 4K Call stack 0K Segment 3 Segmentation model Unit of memory movement is: Variably sized Defined by the programmer Two component addresses, <Seg#, offset> Address translation is more complex than paging B t : segments x offsets! Physical Address " {#} B t (i, j) = k Operating Systems and 31Distributed Systems

9 Segmentation model: Segment Address Translation B t : segments x offsets! physical address " {#} B t (i, j) = k S: segments! segment addresses B t (S(segName), j) = k N: offset names! offset addresses B t (S(segName), N(offsetName)) = k Address Translation in Segmentation Missing segment <segmentname, offsetname> S N segment # offset? B t Limit Base P Limit Relocation + To Memory Address Register Paging vs segmentation What? Paging Segmentation Need the programmer know about it? How many linear address spaces? More addresses than physical memory? Separate protection for different objects? Variable-sized objects handled with ease? No Operating Systems and 35Distributed Systems Yes 1 Many Yes No No Yes Yes Yes Is sharing easy? No Yes Why use it? More address space without buying more memory Break programs into logical pieces that are handled separately Hardware implementation Segmentation requires special hardware Segment descriptor support Segment base registers (segment, code, stack) Translation hardware Some of translation can be static No dynamic offset name binding Limited protection

10 Segmentation Hardware Segmentation Architecture (Cont) Protection With each entry in segment associate: validation bit = 0 $ illegal segment read/write/execute privileges Protection bits associated with segments; code sharing occurs at segment level Since segments vary in length, memory allocation is a dynamic storage-allocation problem A segmentation example is shown in the following diagram Example of Segmentation Implementing segmentation Segment 3 (10 KB) Segment 2 (4 KB) Segment 1 (12 KB) Segment 3 (10 KB) Segment 2 (4 KB) Segment 4 (7 KB) 5 KB free Segment 5 (6 KB) 4 KB free Segment 2 (4 KB) Segment 4 (7 KB) 5 KB free Segment 6 (8 KB) Segment 9 KB free6 (8 KB) Segment 5 (6 KB) Segment 2 (4 KB) Segment 4 (7 KB) Segment 0 (6 KB) Segment 0 (6 KB) Segment 0 (6 KB) Segment 0 (6 KB) => Need to do memory compaction! Operating Systems and 40Distributed Systems

11 Segmentation: summary Segmentation Architecture Logical address consists of a pair: <segment-number, offset>, Segment maps two-dimensional physical addresses; each entry has: base contains the starting physical address where the segments reside in memory limit specifies the length of the segment Segment- base register (STBR) points to the segment s location in memory Segment- length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR Relocation dynamic by segment Sharing shared segments same segment number Allocation first fit/best fit external fragmentation Protection With each entry in segment associate: validation bit = 0 illegal segment read/write/execute privileges Protection bits associated with segments; code sharing occurs at segment level Since segments vary in length, memory allocation is a dynamic storage-allocation problem Better: segmentation and paging Operating Systems and 42Distributed Systems Example: The Intel Pentium Supports both segmentation and segmentation with paging CPU generates logical address Given to segmentation unit Which produces linear addresses Linear address given to paging unit Which generates physical address in main memory Paging units form equivalent of MMU Memory management in the Pentium Memory composed of segments Segment pointed to by segment descriptor Segment selector used to identify descriptor Segment descriptor describes segment Base virtual address Size Protection Code / data Operating Systems and 44Distributed Systems

12 Logical to Physical Address Translation in Pentium Pentium Paging Architecture Pentium has 6 segment registers CS, SS, DS, ES, FS, GS Also has 6 microprogram registers to hold the associated segment descriptor to avoid memory refs on each translation A segment register holds a segment "selector" A selector is 16 bits and uses 13 to hold the segment index (s), 1 bit for the gdt/ldt switch (g), and 2 bits for the privilege level (p) The gdt/ldt switch is used to select between the GDT (one for the entire system and shared between all processes) and the LDT (private to the process) Given the, use (s) to index into the Intel Pentium Segmentation Unit Pentium Paging Architecture Segment selector used to identify descriptor Segment pointed to by segment descriptor Segment descriptor describes segment

13 Process address space Augmenting address space Memory organization (allocation) HW support The big picture Non contiguous allocation Contiguous allocation Swappig Virtual Memory Limit & relocation registers Page request Page replacement Fixed dimension Variable dimension Variable partitioning Fixed partitioning Dedicated registers Paging Segmentation Dynamic allocation Table based partitioning Page Frame allocation TLB Paging & Segmentation Segment Augmentation strategies: Swapping Supported by dynamic memory allocation Suppose there is high demand for execu memory Equi policy might be to time-multiplex processes into the memory (also spacemux) Means that process can have its address space unloaded when it still needs memory Usually only happens when it is blocked Swapping Swapping: leaving room to grow B B B B A A A A D D D OS OS OS OS OS OS OS Memory allocation changes as Processes come into memory Processes leave memory Swapped to disk Complete execution Gray regions are unused memory C C C C C Need to allow for programs to grow Allocate more memory for data Larger stack Handled by allocating more space than is necessary at the start Inefficient: wastes memory that s not currently in use What if the process requests too much memory? Process B Process A Stack Data Code Stack Data Code OS Room for B to grow Room for A to grow Operating Systems and 51Distributed Systems Operating Systems and 52Distributed Systems

14 Limitations of swapping Problems with swapping Process must fit into physical memory (impossible to run larger processes) Memory becomes fragmented External fragmentation: lots of small free areas Compaction needed to reassemble larger free areas Processes are either in memory or on disk: half and half doesn t do any good Overlays solved the first problem Bring in pieces of the process over time (typically data) Still doesn t solve the problem of fragmentation or partially resident processes 53 Process address space Augmenting address space Memory organization (allocation) HW support The big picture Contiguous allocation Swappig Virtual Memory Non contiguous allocation Limit & relocation registers Page request Page replacement Fixed dimension Variable dimension Variable partitioning Fixed partitioning Dedicated registers Paging Segmentation Dynamic allocation Table based partitioning Page Frame allocation TLB Paging & Segmentation Segment Virtual Memory Virtual memory separation of user logical memory from physical memory Only part of the program needs to be in memory for execution Logical address space can therefore be much larger than physical address space Allows address spaces to be shared by several processes Allows for more efficient process creation Virtual Memory Every process has code and data locality Code tends to execute in a few fragments at one time Tend to reference same set of data structures Dynamically load/unload currently-used address space fragments as the process executes Uses dynamic address relocation/binding Generalization of base-limit registers Physical address corresponding to a compiletime address is not bound until run time

15 Size of Blocks of Memory Virtual Memory That is Larger Than Physical Memory Virtual memory system transfers blocks of the address space to/from primary memory Fixed size blocks: System-defined pages are moved back and forth between primary and secondary memory Variable size blocks: Programmer-defined segments corresponding to logical fragments are the unit of movement Paging is the commercially dominant form of virtual memory today $ Shared Library Using Virtual Memory Demand Paging Bring a page into memory only when it is needed Less I/O needed Less memory needed Faster response More users Page is needed $ reference to it invalid reference $ abort not-in-memory $ bring to memory Lazy swapper never swaps a page into memory unless page will be needed Swapper that deals with pages is a pager

16 Transfer of a Paged Memory to Contiguous Disk Space Valid-Invalid Bit With each page entry a valid invalid bit is associated (v $ in-memory, i $ not-in-memory) Initially valid invalid bit is set to i on all entries Frame # page valid-invalid bit v v v v i i i During address translation, if valid invalid bit in page entry is I $ page fault Page Table When Some Pages Are Not in Main Memory Page Fault If there is a reference to a page, first reference to that page will trap to operating system: page fault 1 Operating system looks at another to decide:! Invalid reference $ abort! Just not in memory 2 Get empty frame 3 Swap page into frame 4 Reset s 5 Set validation bit = v 6 Restart the instruction that caused the page fault

17 How is a page fault handled? Hardware causes a page fault General registers saved (as on every exception) OS determines which virtual page needed Actual fault address in a special register Address of faulting instruction in register Page fault was in fetching instruction, or Page fault was in fetching operands for instruction OS must figure out which 65 OS checks validity of address Process killed if address was illegal OS finds a place to put new page frame If frame selected for replacement is dirty, write it out to disk OS requests the new page from disk Page s updated Faulting instruction backed up so it can be restarted Faulting process scheduled Registers restored Program continues Steps in Handling a Page Fault Backing up an instruction Problem: page fault happens in the middle of instruction execution Some changes may have already happened Others may be waiting for VM to be fixed Solution: undo all of the changes made by the instruction Restart instruction from the beginning This is easier on some architectures than others Example: LW R1, 12(R2) Page fault in fetching instruction: nothing to undo Page fault in getting value at 12(R2): restart instruction Example: ADD (Rd)+,(Rs1)+,(Rs2)+ Page fault in writing to (Rd): may have to undo an awful lot Performance of Demand Paging Page Fault Rate: probability 0 % p % 10 if p = 0 no page faults if p = 1, every reference is a fault Effective Access Time (EAT)!! EAT = (1 p) x memory access!!! + p x (page fault overhead!!! + swap page out!!! + swap page in!!! + restart overhead ) Operating Systems and 67Distributed Systems

18 Demand Paging: Example Process Creation Memory access time = 200 nanoseconds Average page-fault service time = 8 milliseconds Compute EAT and slowdown factor assuming that one access out of 1,000 causes a page fault EAT = (1 p) x p (8 milliseconds)! = (1 p) x p x 8,000,000 = p x 7,999,800 If one access out of 1,000 causes a page fault, then EAT = 82 microseconds This is a slowdown by a factor of 40!! " Virtual memory allows other benefits during process creation:! - Copy-on-Write! - Memory-Mapped Files (later) Copy-on-Write Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory If either process modifies a shared page, only then is the page copied COW allows more efficient process creation as only modified pages are copied Free pages are allocated from a pool of zeroed-out pages