ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012

Size: px
Start display at page:

Download "ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012"

Transcription

1 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name (please print) total

2 Problem 1 (5 parts, 25points) Code Fragments and Short Answers Part A (7 points) Write a MIPS code fragment that adds the value 0x4FA2C3 to register $1 and puts the result in $2. Modify only registers $1 and $2. (You may use hexadecimal immediate values.) For maximum credit, include comments. Label Instruction Comment Part B (10 points) Write a C code fragment that loops through an array of integers A until it hits one that is zero. It should compute and store in the variable p the running product of the nonzero integers that occur in the array before the zero. Assume that A contains at least one zero and it contains at least one nonzero integer before the first zero. For maximum credit, choose the most appropriate loop construct and declare and initialize variables as needed. int A[] = {..., 0,...; int p; Part C (2 points) In the following command, what does -Wall tell gcc to do? gcc HW1-2.c g Wall o HW1-2 Part D (2 points) Suppose your current working directory is ece2035 and it has a subdirectory called HW1. Write a Linux command to change to the subdirectory HW1. Part E (4 points) Suppose you give the Linux command: mv P1-1-shell.c P1-1.c What is argc? What is argv[0]? Argc = Argv[0] = 2

3 Problem 2 (1 part, 25 points) Flow Control Draw a control flow diagram for the following C code fragment based on the HW1-2.c set intersection baseline. int i, j, k=0, x; for (i = 0; i < 10; i++) { x = SetA[i]; for (j = 0; j < 10; j++) { if (x == SetB[j]) { printf("%d\n", x); k++; break; printf("size: %d\n", k); 3

4 Problem 3 (2 parts, 24 points) Baseline Reverse Engineering Consider the following code fragment based on a simplification of the HW2 maximum mode baseline. This code loops through the Nums array of values. It maintains the following variables in these registers: $1 I (index into Nums array) $7 ModeFreq (max frequency encountered so far) $2 Mode (most frequently occuring element so far) $8 Predicate register $3 Nums[I] (current element) $9 Array bound $6 Freq (current element's frequency) Part A (12 points) For the instructions that have no comments (i.e., those in lines 3-9), provide a description of each instruction in terms of the variables given in the table above. Label Instruction Comment OuterLoop: lw $3, Array($1) # load current value (i.e., Nums[I]) slt $8, $7, $6 # 3 bne $8, $0, Update # bne $7, $6, NextElt # slt $8, $2, $3 # beq $8, $0, NextElt # Update: addi $2, $3, 0 # 8 addi $7, $6, 0 # 9 NextElt: addi $1, $1, 4 # increment array pointer index 10 bne $1, $9, OuterLoop # exit loop if hit array bound 11 Part B (12 points) The code in lines 3-7 can be used to implement a compound predicate that determines whether Mode and ModeFreq are updated in the following loop (also based on the HW2 baseline). Fill in the blank line with the compound predicate that lines 3-7 implement. for (I = 0; I < 100; I++) { Freq = 0; for (J = I; J < 100; J++) if (Nums[I] == Nums[J]) Freq++; if ( ) { Mode = Nums[I]; ModeFreq = Freq; 4

5 Problem 4 (2 parts, 26 points) Subroutines and Stack Part A (12 points) Complete this MIPS subroutine that takes three inputs: an integer in $3, a running sum in $5, and a count in $7. If the integer in $3 is odd, it adds it to the running sum in $5 and increments the count in $7. You may use additional registers. Label Instruction Comment CountOdd: # is integer in $3 even? Return: # then return to caller # else add $3 to running sum $5 # increment count in $7 # return to caller Part B (14 points) The following MIPS subroutine computes the average of all the odd numbers in an integer array starting at location labeled Array. Registers are used as follows: $1 Array index $5 Running sum of odd numbers; output average $2 Size of the array in bytes $7 Running count of odd numbers $3 Current Array element $8 Predicate register Complete the routine by adding MIPS code to preserve registers before the jal by pushing them on the stack and to restore them after the subroutine call. Assume CountOdd can modify any registers, not just the ones your version modified in Part A. OddAvg: addi $1, $0, 0 # init Array index addi $2, $0, 400 # init Array size addi $5, $0, 0 # init Array index addi $7, $0, 0 # init Array index Loop: lw $3, Array($1) # load in current element jal CountOdd # in: $3, $5, $7; out: $5, $7 addi $1, $1, 4 # inc Array index bne $1, $2, Loop # if end not reached, loop div $5, $7 # odd running sum / odd count mflo $5 # put odd number avg in $5 jr $31 # return to caller 5

6 MIPS Instruction Set (core) instruction example meaning arithmetic add add $1,$2,$3 $1 = $2 + $3 subtract sub $1,$2,$3 $1 = $2 - $3 add immediate addi $1,$2,100 $1 = $ add unsigned addu $1,$2,$3 $1 = $2 + $3 subtract unsigned subu $1,$2,$3 $1 = $2 - $3 add immediate unsigned addiu $1,$2,100 $1 = $ set if less than slt $1, $2, $3 if ($2 < $3), $1 = 1 else $1 = 0 set if less than immediate slti $1, $2, 100 if ($2 < 100), $1 = 1 else $1 = 0 set if less than unsigned sltu $1, $2, $3 if ($2 < $3), $1 = 1 else $1 = 0 set if < immediate unsigned sltui $1, $2, 100 if ($2 < 100), $1 = 1 else $1 = 0 multiply mult $2,$3 Hi, Lo = $2 * $3, 64-bit signed product multiply unsigned multu $2,$3 Hi, Lo = $2 * $3, 64-bit unsigned product divide div $2,$3 Lo = $2 / $3, Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 / $3, Hi = $2 mod $3, unsigned transfer move from Hi mfhi $1 $1 = Hi move from Lo mflo $1 $1 = Lo load upper immediate lui $1,100 $1 = 100 x 2 16 logic and and $1,$2,$3 $1 = $2 & $3 or or $1,$2,$3 $1 = $2 $3 and immediate andi $1,$2,100 $1 = $2 & 100 or immediate ori $1,$2,100 $1 = $2 100 nor nor $1,$2,$3 $1 = not($2 $3) xor xor $1, $2, $3 $1 = $2 $3 xor immediate xori $1, $2, 255 $1 = $2 255 shift shift left logical sll $1,$2,5 $1 = $2 << 5 (logical) shift left logical variable sllv $1,$2,$3 $1 = $2 << $3 (logical), variable shift amt shift right logical srl $1,$2,5 $1 = $2 >> 5 (logical) shift right logical variable srlv $1,$2,$3 $1 = $2 >> $3 (logical), variable shift amt shift right arithmetic sra $1,$2,5 $1 = $2 >> 5 (arithmetic) shift right arithmetic variable srav $1,$2,$3 $1 = $2 >> $3 (arithmetic), variable shift amt memory load word lw $1, 1000($2) $1 = memory [$2+1000] store word sw $1, 1000($2) memory [$2+1000] = $1 load byte lb $1, 1002($2) $1 = memory[$2+1002] in least sig. byte load byte unsigned lbu $1, 1002($2) $1 = memory[$2+1002] in least sig. byte store byte sb $1, 1002($2) memory[$2+1002] = $1 (byte modified only) branch branch if equal beq $1,$2,100 if ($1 = $2), PC = PC (100*4) branch if not equal bne $1,$2,100 if ($1 $2), PC = PC (100*4) jump jump j PC = 10000*4 jump register jr $31 PC = $31 jump and link jal $31 = PC + 4; PC = 10000*4 6

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly) Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Q1: /30 Q2: /25 Q3: /45. Total: /100

Q1: /30 Q2: /25 Q3: /45. Total: /100 ECE 2035(A) Programming for Hardware/Software Systems Fall 2013 Exam One September 19 th 2013 This is a closed book, closed note texam. Calculators are not permitted. Please work the exam in pencil and

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed. Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed. Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 8 December 2014 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Three 10 April 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 9 December 2015

ECE 2035 A Programming Hw/Sw Systems Fall problems, 8 pages Final Exam 9 December 2015 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 9 December 2013

ECE 2035 Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 9 December 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016

ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

MIPS Instruction Reference

MIPS Instruction Reference Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

More information

MIPS Reference Guide

MIPS Reference Guide MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

More information

F. Appendix 6 MIPS Instruction Reference

F. Appendix 6 MIPS Instruction Reference F. Appendix 6 MIPS Instruction Reference Note: ALL immediate values should be sign extended. Exception: For logical operations immediate values should be zero extended. After extensions, you treat them

More information

ECE 2035 Programming HW/SW Systems Spring problems, 7 pages Exam One Solutions 4 February 2013

ECE 2035 Programming HW/SW Systems Spring problems, 7 pages Exam One Solutions 4 February 2013 Problem 1 (3 parts, 30 points) Code Fragments Part A (5 points) Write a MIPS code fragment that branches to label Target when register $1 is less than or equal to register $2. You may use only two instructions.

More information

Week 10: Assembly Programming

Week 10: Assembly Programming Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +

More information

Assembly Programming

Assembly Programming Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

More information

Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck!

Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck! CSC B58 Winter 2017 Final Examination Duration 2 hours and 50 minutes Aids allowed: none Last Name: Student Number: UTORid: First Name: Question 0. [1 mark] Read and follow all instructions on this page,

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.

More information

Computer Architecture. The Language of the Machine

Computer Architecture. The Language of the Machine Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers

More information

The MIPS Instruction Set Architecture

The MIPS Instruction Set Architecture The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying

More information

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction

More information

MIPS Instruction Set

MIPS Instruction Set MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central

More information

SPIM Instruction Set

SPIM Instruction Set SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

More information

TSK3000A - Generic Instructions

TSK3000A - Generic Instructions TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions

More information

Computer Architecture. MIPS Instruction Set Architecture

Computer Architecture. MIPS Instruction Set Architecture Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design

More information

ECE Exam I February 19 th, :00 pm 4:25pm

ECE Exam I February 19 th, :00 pm 4:25pm ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

More information

Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then

More information

CS 61c: Great Ideas in Computer Architecture

CS 61c: Great Ideas in Computer Architecture MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: $s0-$s7,$t0-$t9, $0

More information

ECE 15B Computer Organization Spring 2010

ECE 15B Computer Organization Spring 2010 ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 7: Procedures I Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by and

More information

ECE 30 Introduction to Computer Engineering

ECE 30 Introduction to Computer Engineering ECE 30 Introduction to Computer Engineering Study Problems, Set #3 Spring 2015 Use the MIPS assembly instructions listed below to solve the following problems. arithmetic add add sub subtract addi add

More information

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design. Computer Organization - Previously covered ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

More information

MIPS Instruction Format

MIPS Instruction Format MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

More information

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2) Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into

More information

MIPS Assembly Language. Today s Lecture

MIPS Assembly Language. Today s Lecture MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program

More information

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

More information

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

M2 Instruction Set Architecture

M2 Instruction Set Architecture M2 Instruction Set Architecture Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine

More information

Arithmetic for Computers

Arithmetic for Computers MIPS Arithmetic Instructions Cptr280 Dr Curtis Nelson Arithmetic for Computers Operations on integers Addition and subtraction; Multiplication and division; Dealing with overflow; Signed vs. unsigned numbers.

More information

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix

More information

MIPS%Assembly% E155%

MIPS%Assembly% E155% MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary

More information

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

More information

Programming the processor

Programming the processor CSC258 Week 9 Logistics This week: Lab 7 is the last Logisim DE2 lab. Next week: Lab 8 will be assembly. For assembly labs you can work individually or in pairs. No matter how you do it, the important

More information

Lec 10: Assembler. Announcements

Lec 10: Assembler. Announcements Lec 10: Assembler Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University Announcements HW 2 is out Due Wed after Fall Break Robot-wide paths PA 1 is due next Wed Don t use incrementor 4 times

More information

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION. A bit of history CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

More information

CS61c MIDTERM EXAM: 3/17/99

CS61c MIDTERM EXAM: 3/17/99 CS61c MIDTERM EXAM: 3/17/99 D. A. Patterson Last name Student ID number First name Login: cs61c- Please circle the last two letters of your login name. a b c d e f g h i j k l m n o p q r s t u v w x y

More information

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local

More information

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations CS6C L9 MIPS Logical & Shift Ops, and Instruction Representation I () inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I 25-9-28

More information

CSc 256 Midterm (green) Fall 2018

CSc 256 Midterm (green) Fall 2018 CSc 256 Midterm (green) Fall 2018 NAME: Problem 1 (5 points): Suppose we are tracing a C/C++ program using a debugger such as gdb. The code showing all function calls looks like this: main() { bat(5);

More information

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers

More information

Examples of branch instructions

Examples of branch instructions Examples of branch instructions Beq rs,rt,target #go to target if rs = rt Beqz rs, target #go to target if rs = 0 Bne rs,rt,target #go to target if rs!= rt Bltz rs, target #go to target if rs < 0 etc.

More information

CSc 256 Midterm 2 Fall 2011

CSc 256 Midterm 2 Fall 2011 CSc 256 Midterm 2 Fall 2011 NAME: 1a) You are given a MIPS branch instruction: x: beq $12, $0, y The address of the label "y" is 0x400468. The memory location at "x" contains: address contents 0x40049c

More information

CSc 256 Midterm 2 Spring 2012

CSc 256 Midterm 2 Spring 2012 CSc 256 Midterm 2 Spring 2012 NAME: 1a) You are given this MIPS assembly language instruction (i.e., pseudo- instruction): ble $12, 0x20004880, there Translate this MIPS instruction to an efficient sequence

More information

CSc 256 Final Fall 2016

CSc 256 Final Fall 2016 CSc 256 Final Fall 2016 NAME: Problem 1 (25 points) Translate the C/C++ function func() into MIPS assembly language. The prototype is: void func(int arg0, int *arg1); arg0-arg1 are in $a0- $a1 respectively.

More information

Computer Architecture Experiment

Computer Architecture Experiment Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

Number Systems and Their Representations

Number Systems and Their Representations Number Representations Cptr280 Dr Curtis Nelson Number Systems and Their Representations In this presentation you will learn about: Representation of numbers in computers; Signed vs. unsigned numbers;

More information

Flow of Control -- Conditional branch instructions

Flow of Control -- Conditional branch instructions Flow of Control -- Conditional branch instructions You can compare directly Equality or inequality of two registers One register with 0 (>,

More information

MACHINE LANGUAGE. To work with the machine, we need a translator.

MACHINE LANGUAGE. To work with the machine, we need a translator. LECTURE 2 Assembly MACHINE LANGUAGE As humans, communicating with a machine is a tedious task. We can t, for example, just say add this number and that number and store the result here. Computers have

More information

Midterm. Sticker winners: if you got >= 50 / 67

Midterm. Sticker winners: if you got >= 50 / 67 CSC258 Week 8 Midterm Class average: 4.2 / 67 (6%) Highest mark: 64.5 / 67 Tests will be return in office hours. Make sure your midterm mark is correct on MarkUs Solution posted on the course website.

More information

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-2 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

More information

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011 CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

MIPS Assembly Language

MIPS Assembly Language MIPS Assembly Language Chapter 15 S. Dandamudi Outline MIPS architecture Registers Addressing modes MIPS instruction set Instruction format Data transfer instructions Arithmetic instructions Logical/shift/rotate/compare

More information

Concocting an Instruction Set

Concocting an Instruction Set Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von

More information

CMPE324 Computer Architecture Lecture 2

CMPE324 Computer Architecture Lecture 2 CMPE324 Computer Architecture Lecture 2.1 What is Computer Architecture? Software Hardware Application (Netscape) Operating System Compiler (Unix; Assembler Windows 9x) Processor Memory Datapath & Control

More information

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture ECE468 Computer Organization & Architecture MIPS Instruction Set Architecture ECE468 Lec4.1 MIPS R2000 / R3000 Registers 32-bit machine --> Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0 = 0) 32

More information

A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches

More information

INSTRUCTION SET COMPARISONS

INSTRUCTION SET COMPARISONS INSTRUCTION SET COMPARISONS MIPS SPARC MOTOROLA REGISTERS: INTEGER 32 FIXED WINDOWS 32 FIXED FP SEPARATE SEPARATE SHARED BRANCHES: CONDITION CODES NO YES NO COMPARE & BR. YES NO YES A=B COMP. & BR. YES

More information

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter

More information

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Procedure Calls A procedure of a subroutine is like an agent which needs certain information to perform a

More information

Midterm. CS64 Spring Midterm Exam

Midterm. CS64 Spring Midterm Exam Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every

More information

Review: MIPS Organization

Review: MIPS Organization 1 MIPS Arithmetic Review: MIPS Organization Processor Memory src1 addr 5 src2 addr 5 dst addr 5 write data Register File registers ($zero - $ra) bits src1 data src2 data read/write addr 1 1100 2 30 words

More information

Chapter 2A Instructions: Language of the Computer

Chapter 2A Instructions: Language of the Computer Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction

More information

Part II Instruction-Set Architecture. Jan Computer Architecture, Instruction-Set Architecture Slide 1

Part II Instruction-Set Architecture. Jan Computer Architecture, Instruction-Set Architecture Slide 1 Part II Instruction-Set Architecture Jan. 211 Computer Architecture, Instruction-Set Architecture Slide 1 MiniMIPS Instruction Formats op rs rt 31 25 2 15 1 5 R 6 bits 5 bits 5 bits 5 bits I J Opcode Source

More information

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont ) Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise

More information

UCB CS61C : Machine Structures

UCB CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Guest Lecturer Alan Christopher Lecture 08 MIPS Instruction Representation I 2014-02-07 BOINC MORE THAN JUST SETI@HOME BOINC (developed here

More information

We will study the MIPS assembly language as an exemplar of the concept.

We will study the MIPS assembly language as an exemplar of the concept. MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and

More information

ICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE. Midterm Exam. First Semester (141) Time: 1:00-3:30 PM. Student Name : _KEY

ICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE. Midterm Exam. First Semester (141) Time: 1:00-3:30 PM. Student Name : _KEY Page 1 of 14 Nov. 22, 2014 ICS DEPARTMENT ICS 233 COMPUTER ARCHITECTURE & ASSEMBLY LANGUAGE Midterm Exam First Semester (141) Time: 1:00-3:30 PM Student Name : _KEY Student ID. : Question Max Points Score

More information

CS3350B Computer Architecture MIPS Instruction Representation

CS3350B Computer Architecture MIPS Instruction Representation CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada

More information

Project Part A: Single Cycle Processor

Project Part A: Single Cycle Processor Curtis Mayberry Andrew Kies Mark Monat Iowa State University CprE 381 Professor Joseph Zambreno Project Part A: Single Cycle Processor Introduction The second part in the three part MIPS Processor design

More information

EE 109 Unit 13 MIPS Instruction Set. Instruction Set Architecture (ISA) Components of an ISA INSTRUCTION SET OVERVIEW

EE 109 Unit 13 MIPS Instruction Set. Instruction Set Architecture (ISA) Components of an ISA INSTRUCTION SET OVERVIEW 1 2 EE 109 Unit 13 MIPS Instruction Set Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 4 Instruction Set Architecture (ISA) Defines the of the processor and memory system Instruction set

More information

Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015

Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015 Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative

More information

Compiling Techniques

Compiling Techniques Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically

More information

Concocting an Instruction Set

Concocting an Instruction Set Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.6 L04 Instruction Set 1 A General-Purpose Computer The von

More information

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved.

MIPS Coding Snippets. Prof. James L. Frankel Harvard University. Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved. MIPS Coding Snippets Prof. James L. Frankel Harvard University Version of 9:32 PM 14-Feb-2016 Copyright 2016 James L. Frankel. All rights reserved. Loading a 32-bit constant into a register # Example loading

More information

University of California at Santa Barbara. ECE 154A Introduction to Computer Architecture. Quiz #1. October 30 th, Name (Last, First)

University of California at Santa Barbara. ECE 154A Introduction to Computer Architecture. Quiz #1. October 30 th, Name (Last, First) University of California at Santa Barbara ECE 154A Introduction to Computer Architecture Quiz #1 October 30 th, 2012 Name (Last, First) All grades will be posted on the website as a single spreadsheet

More information

Exam in Computer Engineering

Exam in Computer Engineering Exam in Computer Engineering Kurskod D0013E/SMD137/SMD082/SMD066 Tentamensdatum 2010-10-29 Skrivtid 14.00-18.00 Maximalt resultat 50 poäng Godkänt resultat 25 poäng Jourhavande lärare Andrey Kruglyak Tel

More information

CS61C Machine Structures. Lecture 12 - MIPS Procedures II & Logical Ops. 2/13/2006 John Wawrzynek. www-inst.eecs.berkeley.

CS61C Machine Structures. Lecture 12 - MIPS Procedures II & Logical Ops. 2/13/2006 John Wawrzynek. www-inst.eecs.berkeley. CS61C Machine Structures Lecture 12 - MIPS Procedures II & Logical Ops 2/13/2006 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L12 MIPS Procedures II / Logical (1)

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures $2M 3D camera Lecture 8 MIPS Instruction Representation I Instructor: Miki Lustig 2014-09-17 August 25: The final ISA showdown: Is ARM, x86, or

More information

EE 109 Unit 8 MIPS Instruction Set

EE 109 Unit 8 MIPS Instruction Set 1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system

More information

Assembly Language. Prof. Dr. Antônio Augusto Fröhlich. Sep 2006

Assembly Language. Prof. Dr. Antônio Augusto Fröhlich.   Sep 2006 Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 33 Assembly Language Prof. Dr. Antônio Augusto Fröhlich guto@lisha.ufsc.br http://www.lisha.ufsc.br/~guto Sep 2006 Sep 2006 Prof. Antônio

More information

CS61C - Machine Structures. Lecture 6 - Instruction Representation. September 15, 2000 David Patterson.

CS61C - Machine Structures. Lecture 6 - Instruction Representation. September 15, 2000 David Patterson. CS61C - Machine Structures Lecture 6 - Instruction Representation September 15, 2000 David Patterson http://www-inst.eecs.berkeley.edu/~cs61c/ 1 Review Instructions: add, addi, sub, lw, sw beq, bne, j

More information

RISC-V Assembly and Binary Notation

RISC-V Assembly and Binary Notation RISC-V Assembly and Binary Notation L02-1 Course Mechanics Reminders Course website: http://6004.mit.edu All lectures, videos, tutorials, and exam material can be found under Information/Resources tab.

More information

MIPS Integer ALU Requirements

MIPS Integer ALU Requirements MIPS Integer ALU Requirements Add, AddU, Sub, SubU, AddI, AddIU: 2 s complement adder/sub with overflow detection. And, Or, Andi, Ori, Xor, Xori, Nor: Logical AND, logical OR, XOR, nor. SLTI, SLTIU (set

More information

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed

More information