UNIVERSITY OF ULSTER UNIVERSITY EXAMINATIONS : 2001/2002. Semester 2. Year 2 MICROCONTROLLER SYSTEMS. Module Code: EEE305J2. Time allowed: 3 Hours

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1 UNIVERSITY OF ULSTER UNIVERSITY EXAMINATIONS : 2001/2002 Semester 2 Year 2 MICROCONTROLLER SYSTEMS Module Code: EEE305J2 Time allowed: 3 Hours Answer as many questions as you can. Not more than TWO questions from Section B will contribute to the final mark. Use separate answer books for each section. A PIC16 FXXX instruction set appears at the end of this paper A CCS C compiler reference card appears at the end of this paper Module Co-Ordinator: Dr S J Katzen 1/9

2 SECTION A Q.A1 A certain TV panel game has eight contestants who will answer questions posed by the compère. Each contestant has a single push switch he/she closes if ready to respond. A single common cathode 7-segment display is to be used to indicate which contestant responded first. A single buzzer sounds for nominally one second to alert the compère that there has been some response. After the buzzer has sounded, there is to be a nominal 20-second delay to lock out any further contestant switch activity. The intelligence of this logic system is to be implemented using a PIC16F87X-based system which is to read the eight switches and drive the 7-segment display and single buzzer. Pertinent hardware details are: A closed switch gives a logic 0. The single common-cathode 7-segment display requires a nominal current of 20 ma for each segment. The buzzer requires 5 volts to activate. The PIC is clocked using a 4 MHz crystal and uses a 5V power supply. You are asked to design both input and output interface circuitry and software for the system to implement the following scheme. Questions (1), (2) and (3) should be illustrated and any software port configuration shown at this point. (1) The input interface for the eight contestant switches, including any necessary resistors. [6 marks] (2) The output interface to the single common-cathode 7-segment display. Determine the value of the seven current limiting resistors. [8 marks] (3) A single output line to drive the buzzer. [2 marks] (4) An algorithm and assembly-level code as listed below, assuming that file registers between 20h and 2Fh are free. (a) A main endless loop to: (i) Initialise the system; 2/9

3 (ii) (iii) (iv) (v) loop to scan and count the eight contestant switches looking for a closure; breaking out of the loop on a closed switch and calling up subroutine (b) below to convert the contestant number of 7-segment code and activate the display; sound the buzzer for nominally one second using subroutine (c); wait for a further 19 seconds using subroutine (c), clear the display and repeat forever. [26 marks] (b) (c) A subroutine converting a 4-bit binary code 0000 through 1000, in the working register to active-high 7-segment code. [8 marks] A subroutine that gives a nominal n-100 ms (0.1s) delay, where n is an Integer passed to the subroutine in the working register. [10 marks] For bonus marks: (5) What additional software and hardware resources would be needed to extend your system to cope with up to twelve contestants. [4 marks] (6) Write a main ( ) function in C to implement the code of 4 (a) above. You can assume that functions svnseg(n) and delay_ms(n) are already available to implement 4 (b) and 4 (c). [18 marks] 3/9

4 SECTION B Q.B2 (a) An analogue-to-digital (A/D) converter is to be used to capture digitised speech signals which have been band limited to a range of 300 Hz to 3000 Hz. Choose a suitable type of A/D converter and with the aid of a block diagram and circuit waveforms, explain the operation of the converter. [12 marks] (b) (c) Comment on the speed of conversion of the A/D converter chosen in Q.2a and comment on its noise immunity and resolution when compared with one other type of A/D converter with which you are familiar. [3 marks] Digitising the video signal obtained from a television camera requires a special type of A/D converter, due to the relatively high frequency of the signal. Briefly describe a digital-to-analogue conversion technique which could be used in this situation. [5 marks] Q.B3 (a) The terms single-ended and balanced-differential are sometimes used to describe the standards for serial interfaces between microcomputer systems. Using simple diagrams, describe two industry standards for these types of interfaces and compare and contrast their performance. [10 marks] (b) (c) Explain when and why it becomes necessary to consider the transmission-line characteristics of an interconnecting line for a serial interface. What are the problems encountered? [8 marks] How can the effects of some of the problems mentioned in Q.3b be reduced by suitable choice of connecting cables? [2 marks] 4/9

5 Q.B4 (a) With reference to Fig. Q.B4, explain the operation of Timer 0 detailing the function of each register and configuration bit. [10 marks] (b) Write a subroutine to use Timer 0 to create a fixed delay of 208 ms. You may assume that the crystal frequency is 4 MHz. Your answer should show how you would configure Timer 0 using a pre-scaler ratio of frequency divide ratio of 4. [10 marks] F /4 osc File 1 TMR0 Synch 1 0 Prescaler F /4 osc RA4 1 T0CKI Timer PS0 0 PS1 1 PS2 2 Overflow 2 INTCON T0IF File 0B h T0SE 4 T0CS 5 PSA 3 OPTION_REG File 81 h Fig. Q.B4 5/9

6 14-bit 16CXX Dest CCR op-code Instruction Mnemonic WFZD C Operation summary LLLL LLLL ADD Literal to W addlw LL w <- w + #LL dfff ffff ADD W and F addwf f,d d <- w + f LLLL LLLL AND Literal to W andlw LL w <- w #LL dfff ffff ANDWtoF andwf f,d d <- w f 01 00nn nfff ffff Bit Clear File bit n bcf f,n 01 01nn nfff ffff Bit Set File bit n bsf f,n 01 10nn nfff ffff Bit Test File bit n & Skip if Clear btfsc f,n 01 11nn nfff ffff Bit Test File bit n & Skip if Set btfss f,n fn <- 0 fn <- 1 pc++ IF fn == 0 pc++ IF fn == aaa aaaa aaaa CALL (jump to) subroutine call aaa TOS <- pc, pc <- aaa fff ffff CLeaR File clrf f f < CLeaR Working register clrw d < CLeaR Watch Dog Timer clrwdt wdt < dfff ffff COMplement File comf f,d d <- f dfff ffff DECrement File decf f,d d <- f dfff ffff DECrement File & Skip on Zero decfsz f,d d <- f--, pc++ IF f == aaa aaaa aaaa GOTO (jump to) aaa goto aaa pc <- aaa dfff ffff INCrement File incf f,d d <- f dfff ffff INCrement File & Skip on Zero incfsz f,d d <- f++, pc++ IF f == LLLL LLLL Inclusive OR Literal to W iorlw LL w <- w + #LL dfff ffff Inclusive OR W to F iorwf f,d d <- w + f dfff ffff MOVe in File (load) movf f,d d <- f LLLL LLLL MOVe Literal into W movlw LL w <- #LL fff ffff MOVe W out to File (store) movwf f f <- w No OPeration nop Do nothing LLLL LLLL RETurn from subroutine with L in W retlw w <- #LL, pc <- TOS RETURN from subroutine return pc <- TOS RETurn From IntErrupt retfie GIE <- 1, pc <- TOS dfff ffff Rotate Left File rlf f,d b7 C 7 file dfff ffff Rotate Right File rrf f,d b0 7 file 0 C Sleep mode on sleep wdt <- 0, Clock off LLLL LLLL SUB W from Literal sublw LL w <- #LL - w dfff ffff SUBtract W from F subwf f,d d <- f - w dfff ffff SWAP File nybbles swapf f,d d <- f[7:4] <--> f[3:0] LLLL LLLL exclusive OR Literal to W xorlw LL w <- w #LL dfff ffff exclusive OR W to F xorwf f,d d <- w f : Flag operates in the normal manner : Not affected a : Address d : Destination; 0=w,1=f f : File register f n : File bit n L : Literal data pc : Program Counter w : Working register wdt : Watch Dog Timer/prescaler TOS : Top Of Stack pc++ : Jump over next instruction == : Equivalent to ++ : Add one -- : Subtract one GIE : Global Interrupt Enable mask # : Constant S.J. Katzen L A T E X2ε Version November 13, 2001 pic_ins14.tex 6/9

7 PIC16F83/84 Special-Purpose Register file summary File Name Power-on All other address Reset Resets Bank 0 00h INDF Uses contents of this to address Data memory (not a physical register) 01h TMR0 8-bit real-time clock/counter XXXX XXXX UUUU UUUU 02h PCL 1 Lower-order 8 bits of the Program Counter h STATUS 1 IRP RP1 RP0 TO PD Z DC C XXX 000??UUU 04h FSR Indirect Data memory address pointer 0 XXXX XXXX UUUU UUUU 05h PORTA RA4 RA3 RA2 RA1 RA0 X XXXX U UUUU 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 XXXX XXXX UUUU UUUU 08h EEDATA Data EEPROM Data register XXXX XXXX UUUU UUUU 09h EEADR Data EEPROM Address register XXXX XXXX UUUU UUUU 0Ah PCLATH Write buffer for top 5 PC bits Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF X U Bank 1 80h INDF Uses contents of this to address Data memory (not a physical register) 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS h PCL 1 Lower-order 8 bits of the Program Counter h STATUS 1 IRP RP1 RP0 TO PD Z DC C XXX 000??UUU 84h FSR Indirect Data memory address pointer 0 XXXX XXXX UUUU UUUU 85h TRISA Port A Direction Register h TRISB Port B Data Direction Register h EECON1 Data EEPROM Data register XXXX XXXX UUUU UUUU 89h EECON2 EEPROM Control register (not a physical register) 8Ah PCLATH Write buffer for top 5 PC bits Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF X U X Not known U Unchanged? Value depends on whether a Watchdog Reset and if in Sleep mode before Reset. Unimplemented; reads as 0. Note 1: Next instruction address if PIC in Sleep mode. S.J. Katzen L A T E X2ε Version November 13, 2001 pic_ins14.tex 7/9

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