Midterm. Sticker winners: if you got >= 50 / 67

Transcription

1 CSC258 Week 8

2 Midterm Class average: 4.2 / 67 (6%) Highest mark: 64.5 / 67 Tests will be return in office hours. Make sure your midterm mark is correct on MarkUs Solution posted on the course website. Remarking request form ú ú the solution, fill in the form, attach it to the test and submit to Larry. ú A subset of the tests have been scanned. Sticker winners: if you got >= 5 / 67 2

3 Reflections Details matter. Being precise is important. ú Off by a couple bits not much better than off by many bits. ú Correct is much much better than almost correct. ú Pay enough attention to details, be precise, and get it all right. ú the questions carefully! The midterm is a great opportunity to realize any inefficiency in your learning method. If you didn t do well or are not sure how to improve, you are encouraged to arrange a meeting with Larry to talk about it how to do better in this course. 3

4 Drop date: March 7 4

5 The Blueprint of a microprocessor The Controller Thing PCCond PC IorD Mem Mem MemtoReg IR Contr ol Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address Memor y [3-26] [25-2] [2-6] [5-] Instructi on Register register Register s reg reg 2 reg Sign extend 2 A B Shift left A B Zero result AL U Out The Storage Thing The Arithmetic Thing 5

6 The Controller Thing aka: the Control Unit 6

7 The Control Unit controls how flows in the path. Different executions have different flows. 7

8 Processor Datapath The path of a processor is a description/ illustration of how the flows between processor components during the execution of an operation. 8

9 Datapath example Note: this is just an abstraction J The simplified path for most processor operations has stages as shown in the diagram: ú ú ú ú ú fetch decode & register fetch Address/ calculation access back. Address (PC) Sign ext. Mux Mux +4 Register File Data Mux Mux 9

10 What happens when you run an executable on your computer?./a.out, ls, fornite.exe,. The OS loads a bunch of instructions into the memory at certain location. 2. CPU finds that location and executes the instructions stored there one by one.

11 What does an instruction look like? It s a 32-bit (4-byte) binary string.

12 How do we remember the location of the current instruction? The program counter (PC) is a special register that stores the location of the current instruction. ú Each instruction is 4 bytes long, thus we do +4 to increments the current PC location. ú PC values can also be loaded from the result of an operation (e.g. jumps to a memory address). 2

13 So, here is the instruction. Do it! What does the instruction mean? What operations do I do? Where do I get the inputs and put the output? We need to decode the instruction. 3

14 decoding The instructions themselves can be broken down into sections that contain all the information needed to execute the operation. ú Also known as a control word. Example: unsigned subtraction ss sssttttt ddddd Register 7 = Register Register 4

15 registers The instruction register takes in the 32-bit instruction fetched from memory, and reads the first 6 bits (known as the opcode) to determine what operation to perform. register 5

16 Opcodes The first six digits of the instruction (the opcode) will determine the instruction type. ú Except for R-type instructions (marked in yellow) ú For these, opcode is, and last six digits denote the function. Op/Func add addu addi addiu div divu mult multu sub subu and andi nor or ori xor xori sll sllv sra Op/Func srav srl srlv beq bgtz blez bne j jal jalr jr lb lbu lh lhu lw sb sh sw mflo 6

17 MIPS instruction types R-type: opcode rs rt rd shamt funct I-type: opcode rs rt immediate J-type: 6 5 opcode 5 6 address 6 26 the first 6 bits first, then you know how to break it down. 7

18 R-type instructions opcode rs rt rd shamt funct Short for register-type instructions. ú Because they operate on the registers, naturally. These instructions have fields for specifying up to three registers and a shift amount. ú Three registers: two source registers (rs & rt) and one destination register (rd). ú A field is usually coded with all bits when not being used. The opcode for all R-type instructions is. The function field specifies the type of operation being performed (add, sub, and, etc). 8

19 Examples opcode rs rt rd shamt funct R-type! Reg 6! Reg 7! Reg 5! XOR! Reg_5 = Reg_6 XOR Reg_7 R-type! Reg 7! Reg 5! 2 bits! Shift left (SLL)! Left shift what s in Reg_7 by 2 bits and store result in Reg_5 9

20 R-type instruction path For the most part, the funct field tells the what operation to perform. rs and rt are sent to the register file, to specify the operands. rd is also sent to the register file, to specify the location of the result. Address (PC) Sign ext. Mux Mux Register File Data Mux +4 Mux 2

21 I-type instructions opcode rs rt immediate These instructions have a 6-bit immediate field. This field a constant value, which is used for: ú an immediate operand, ú a branch target offset (e.g., in branch if equal op), or ú an offset for a memory operand (e.g., in load op). 2

22 I-type instructions opcode rs rt immediate For branch target offset operations, the immediate field contains the signed difference between the current address stored in the PC and the address of the target instruction. ú This offset is stored with the two low order bits dropped. The dropped bits are always since instructions are word-aligned. 22

23 Word-aligned Every instruction is 4-byte ( word) long, so the starting address of each instruction is always a multiple of 4, like () 4 () 8 () 2 () 444 () Note that the two lowest bits are always. Since we know they are always, we don t need to use two bits to remember them. 23

24 Examples opcode rs rt immediate Branch on equal (BEQ) Reg 6! Reg 7! Offset = = 52 If Reg_6 == Reg_7: PC += 52 Else: PC += 4 24

25 Examples opcode rs rt immediate Load byte! (LB) Reg 6! Reg 7! Offset = = 38 Load one byte from MEM[Reg_6+38] to Reg_7 25

26 I-type instruction path Example #: Immediate arithmetic operations, with result stored in registers. Address (PC) Sign ext. Mux Register File Mux +4 Data Mux Mux 26

27 Interlude: Sign extension Sign ext. The immediately value we get from an I-type instruction is 6- bit long. But all operands of are supposed to be 32-bit long. So fill the upper 6 bits of the number with the sign-bit E.g., becomes 27

28 I-type instruction path Example #2: Immediate arithmetic operations, with result stored in memory. Address (PC) Sign ext. Mux Register File Mux +4 Data Mux Mux 28

29 I-type instruction path Example #3: Branch instructions. ú Output is written to PC, which looks to that location for the next instruction. Address (PC) Sign ext. Mux Register File Data Mux +4 Mux Mux 29

30 J-type instructions opcode address Only two J-type instructions: ú ú jump (j) jump and link (jal) These instructions use the 26-bit coded address field to specify the target of the jump. ú ú ú 6 26 The first four bits of the destination address are the same as the current bits in the program counter. The bits in positions 27 to 2 in the address are the 26 bits provided in the instruction. The bits at positions and are always since instructions are word-aligned. 3

31 Examples opcode address 6 26 Jump (J) destination address= {PC[3:28], whats-above, } PC jumps to address {PC[3:28] (4 bits), what s above (26 bits), (2 bits)} (32 bits total) 3

32 J-type instruction path Jump and branch use the path in similar but different ways: ú Branch calculates new PC value as old PC value + offset. (relative) ú Jump loads an immediate value over top of the old PC value. (absolute) Address (PC) Sign ext. Mux Mux Register File Data Mux +4 Mux 32

33 Takeaway Different instructions flow in different paths. In other words, if we can control the paths of flow, then we can control what instruction to execute. 33

34 Datapath control 34

35 Datapath control These instructions are executed by turning various parts of the path on and off, to direct the flow of from the correct source to the correct destination. What tells the processor to turn on these various components at the correct times? 35

36 Control unit The control unit takes in the opcode from the current instruction, and sends signals to the rest of the processor. PCCond PC Control Unit Opcode Within the control unit is a finite state machine that can occupy multiple clock cycles for a single instruction. ú The control unit send out different signals on each clock cycle, to make the overall operation happen. IorD Mem Mem MemtoReg IR PCSource Op SrcB SrcA Reg RegDst 36

37 The control unit sends signals (green lines) to various processor components to enact all possible operations. PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register Registers reg reg 2 reg 2 A B A B Zero result Out register Sign extend Shift left 2 37

38 Signals à instructions A certain combination of signals will make flow from some source to some destination. ú Just need to figure out what signals produce what behaviour. 38

39 Control unit signals PC: the output to the PC. PCCond: the output to the PC, only if the Zero condition has been met. IorD: For memory access; short for or Data. Signals whether the memory address is being provided by the PC (for instructions) or an operation (for ). Mem: The processor is reading from memory. Mem: The processor is writing to memory. MemToReg: The register file is receiving from memory, not from the output. IR: The instruction register is being filled with a new instruction from memory. 39

40 More control unit signals PCSource: Signals whether the value of the PC resulting from an jump, or an operation. Op (3 wires): Signals the execution of an operation. SrcA: Input A into the is coming from the PC (value=) or the register file (value=). SrcB (2 wires): Input B into the is coming from the register file (value=), a constant value of 4 (value=), the instruction register (value=2), or the shifted instruction register (value=3). Reg: The processor is writing to the register file. RegDst: Which part of the instruction is providing the destination address for a register write (rt versus rd). 4

41 Example instruction addi $t7, $t, 42 ú PC = ú PCCond = ú IorD = X ú Mem = ú Mem = ú MemToReg = ú IR = ú PCSource = X ú Op = (add) ú SrcA = ú SrcB = ú Reg = ú RegDst = Setting these signals will result in adding register $t by 42 and storing result in register $t7 4

42 addi $t7, $t, 42 This is a line of assembly language 42

43 Controlling the Datapath 43

44 MIPS Datapath PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out So, how do we do the following? ú ú ú Increment the PC to the next instruction position. Store $t + 2 into the PC. Assuming that register $t3 is storing a valid memory address, fetch the from that location in memory and store it in $t5. 44

45 Controlling the signals Need to understand the role of each signal, and what value they need to have in order to perform the given operation. So, what s the best approach to make this happen? PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst 45

46 Basic approach to path. Figure out the source(s) and destination. 2. Determine the path of the. 3. Deduce the signal values that cause this path: a) Start with & signals (at most one can be high at a time). b) Then, mux signals along the path. c) Non-essential signals get an X value. 46

47 Example #: Incrementing PC PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Given the path above, what signals would the control unit turn on and off to increment the program counter by 4? 47

48 Example #: Incrementing PC PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Step #: Determine source and destination. ú Program counter provides source, ú Program counter is also destination. 48

49 Example #: Incrementing PC PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Step #2: Determine path for ú Operand A for : Program counter ú Operand B for : Literal value 4 ú Destination path: Through mux, back to PC 49

50 Example #: Incrementing PC PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Setting signals for this path:. & signals: PC is high, all others are low. 5

51 Example #: Incrementing PC PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Setting signals for this path: 2. Mux signals: PCSource is, AlUSrcA is, SrcB is all others are don t cares. 5

52 Example #: Incrementing PC PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Other signals for this path: ú Op is (Cin =, S =, S = : A+B) ú PCCond is X when PC is Otherwise it is except when branching. 52

53 Example # (final signals) PC = PCCond = X IorD = X Mem = Mem = MemToReg = X IR = PCSource = Op = SrcA = SrcB = Reg = RegDst = X 53

54 Another example add $r7, $r, $r2 PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Given the path above, what signals would the control unit turn on and off in order to add $r to $r2 and store the result in $r7? 54

55 add $r7, $r, $r2 PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Step #: Data source and destination ú Data starts in register block. ú Data goes to register block. 55

56 Question # (cont d) add $r7, $r, $r2 PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Step #2: Determine the path of the ú Data needs to go through the before heading back into the register file. 56

57 Question # (cont d) add $r7, $r, $r2 PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Step #3a: & signals ú Only Reg needs to be high. ú PC, PCCond, Mem, Mem, IR would be low. 57

58 Question # (cont d) add $r7, $r, $r2 PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register register Registers reg reg 2 reg Sign extend 2 A B Shift left A B Zero result Out Step #3b: Relevant mux signals ú Muxes before : SrcA à, SrcB à. ú Op à (Add) ú Mux before registers: MemToReg à 58

59 Question # (cont d) add $r7, $r, $r2 PCCond PC IorD Mem Mem MemtoReg IR Control Unit Opcode PCSource Op SrcB SrcA Reg RegDst Shift left 2 2 PC Address [3-26] [25-2] [2-6] [5-] Register Registers reg reg 2 reg 2 A B A B Zero result Out register Sign extend Shift left 2 Step #3c: Irrelevant mux signals ú No writing to PC: PCSource à X. ú No reading from memory: IorD à X. 59

60 Question # (cont d) PC = PCCond = IorD = X Mem = Mem = MemToReg = IR = PCSource = X Op = SrcA = SrcB = Reg = RegDst = Note: RegDst rule high for 3-register operations low for 2-register operations X if not using register file 6

61 The Tale of Hello world. You, the programmer, write a piece of code called hello.c/java/whatever 2. You compile the code, which translate the code into machine instructions and save the in an executable file (e.g., hello, hello.exe) 3. You run the executable, OS load the executable (the instructions) into memory, set PC. 4. CPU loads the instruction pointed by PC into instruction register. 5. Control Unit checks the opcode (first 6 bits), decode the rest of the instruction and send signals to setup the path (billions of MOSFETs switching ON/OFF). 6. Data flow through the path, electrons move around 7. And BOOM!, hello world shows up on your screen 6

62 The Tale of Hello world 62