Computer Hardware Engineering

Transcription

1 2 Course Structure Computer Hardware ngineering IS1200, spring 2015 Lecture 3: Languages Module 4: I/O Systems Module 1: Logic Design L DCÖ1 L DCÖ2 Lab:dicom L7 Module 2: C and Assembly Programming Associate Professor, KTH Royal Institute of Technology L1 L2 1 Assistant Research ngineer, University of California, Berkeley L3 2 3 L4 4 Slides version 10 L6 7 Lab: nios2io 9 Lab: nios2int Module 5: Memory Hierarchy L8 Home Lab: cache 8 Lab: nios2time Home lab: C Module 6: Parallel Processors and Programs Module 3: Processor Design L5 6 5 L9 L10 10 I II 3 4 Abstractions in Computer Systems Computer System Agenda Networked Systems and Systems of Systems Application Software Software I Negative Numbers Operating System Instruction Set Architecture Hardware/Software Interface Microarchitecture Logic and Building Blocks II Digital Hardware Design Digital Circuits Analog Circuits Devices and Physics Analog Design and Physics I II I II

2 5 6 Sign/Magnitude Numbers Negative Numbers How can we represent negative numbers? Idea: Let msb represent the sign (1 = negative, 0 = positive) and the remaining bits the magnitude This representation is called signed/magnitude numbers signed/magnitude numbers 6 7 = = = = Can we add two numbers using binary addition? Should be = 1 10 = but = = Problem 1: Binary addition does not work = and = Problem 2: Strange effect; we have two numbers for zero I II I II 7 8 Two s Complement Numbers (1/3) Solution: Two s complement numbers Which patterns can we find in the following 3-bit two s complement numbers Only one number represent 0 (Solution to problem 1) All negative numbers have msb set This is called the sign bit = = = = = = = = I Positive numbers are represented as usual Can represent one more negative number than positive numbers Negative numbers are listed in reverse order II Two s Complement Numbers (2/3) Why is it called two s complement? Because the negation of an N-bit value X is 2 N X Is binary addition working with two s complement numbers? two s complement numbers (check yourself) xample: N = 3 and X = 3 Then = 8 3 = 5 = Should be I = = = = = = = = = 1 10 = = = = = Yes, it works (general proof left as = an exercise) Note that the carry out is 1, but ignored here II

3 9 10 Two s Complement Numbers (3/3) Sign xtension But, in this case we need a subtract erator to get negative numbers Another way to take the two s complement of a number X with N bits: Invert all bit of number X and add 1 xample: N = 3 and X = 3 X = 3 = 0112 inv(x) = 1002, = 1012 (general proof omitted) I Sign extension Assume you have a binary number A with n bits We can sign extend A to have the length m+n bits, by cing A s most significant bit into the m most significant bits 0002 = = = = 310 xample Assume we have value -3 encoded as a two s complement 4-bit value Sign extend the 4-bit value into a 8-bit value 1002 = = = = -110 xercise Assume we have value -10 encoded as a two s complement 8-bit value Sign extend the 8-bit value into a 12-bit value Solution: The 12-bit value is II 11 Instruction ncoding I Word address C II II 12 Stored Programs with Formats 0f a0 93 fa a0 b0 4e 01 1b 12 aa MIPS programs are typically stored from address Physical xercise Sign extend the 4-bit value 2 into 8 bits Stand for , hands on the table for Solution: The 8-bit value is I Stored program concept Code is data Code is stored in memory as any other data, enabling general purpose computing I Solution The 8-bit value is Word 3 Word 2 Word 1 Word 0 For MIPS and NIOS2, there are 3 instruction formats: R-Type (register-type) I-Type (immediate-type) J-Type (jump-type) Although both MIPS and NIOS2 have R, I, and J formats, the exact bit encodings are different See the NIOS2 manual In MIPS and NIOS2, each instruction requires exactly one word (32 bits) of space MIPS code must be word-aligned (start at addresses 0,4, 8, C etc) X86 does not require word alignment I II

4 R-Type Instructions 13 I-Type Instructions 14 R-Type (register-type) instructions have three register erands: two sources and one destination rs 6 bits rt rd shamt stands for shift amount It is only used for shift instructions It has value 0 for other instructions shamt funct 6 bits I-Type (immediate-type) instructions have two register erands and one immediate erand rs 6 bits rt imm 16 bits 0 For R-Type, is always 0 source 1 xercise: Create the machine code for add $t2, $s1, $s2 Answer with a C code expression source 2 destination funct determines the specific R-type instruction Answer: Check the MIPS reference card for codes (10 << 11) (17 << 21) (18 << 16) 32 Opcode source 1 destination xercise: a) Create the machine code for lb $t0,-7($s1) Answer with a binary number b) b) Same as above, but answer with a C code expression for some inst (lw, addi), source 2 for others (sw) Immediate value (can also be negative using two s complement) Answer: a) b) (32 << 26) (17<<21) (8<<16) (-7 & 0xffff) I II I II J-Type Instructions J-Type (jump-type) instructions has one 26- bit address erand II 6 bits addr 26 bits 0 Opcode Address erand I II I II

5 Registers 17 Function Calls and Returns 18 MIPS (and NIOS2) have 32 registers Name Number Use $0 0 constant value of 0 $at 1 assembler temporary $v0-$v1 2-3 function return value $a0-$a3 4-7 function arguments $t0-$t temporary (caller-saved) $s0-$s saved variables (callee-saved) $t8-$t temporary (caller-saved) $k0-$k reserved for OS kernal $gp 28 global pointer 29 stack pointer $fp 30 frame pointer $ra 31 function return address I II int main(){ dummy(); void dummy(){ 0x main: jal dummy 0x x dummy: jr $ra What is the value of $ra when entering the function dummy? Answer: 0x The calling function is called the caller Function main() in this case The called function is called the callee Function dummy() in this case This simple example shows a function call without arguments or return values that returns immediately The jump and link instruction (jal) performs two tasks: 1 It stores the address of the next instruction in the return address register $ra 2 It jumps to the target address (updates the program counter, PC) The jump registers (jr) returns by jumping to the address stored in $ra I II Arguments and Return Values 19 The Stack (1/3) The Basic Idea 20 int main(){ int y; y = sum(3,8); int sum(int x, int y){ return x + y; Assume y is mapped to $s0 main: addi $a0, $0, 3 addi $a1, $0, 8 jal sum add $s0, $v0, $0 sum: add $v0, $a0, $a1 jr $ra Save arguments in $a0 and $a1 Save return value in $v0 Problem: We are limited to four arguments $a0, $a1, $a2, and $a3 Move the result to $s0 (mapped from y) Solution: A stack is used to store local variables and additional arguments A stack is a last-in-first-out (LIFO) queue 0x7FFF FF0C 0x7FFF FF08 0x7FFF FF04 0x7FFF FF00 0x B2 The stack grows traditionally down in memory 0x7FFF FF0C 0x7FFF FF08 0x7FFF FF04 0x7FFF FF00 The stack pointer points to the t of the stack 0x B2 0x x Before adding two words to the stack After adding two words to the stack I II I II

6 The Stack (2/3) Preserving Registers 21 The Stack (3/3) Preserving Registers, Continued 22 One usage of the stack is to save registers that are modified in the callee function xercise: Assume that a callee function foo modifies registers $s0 and $s1 Write the foo function in ASM, so that $s0 and $s1 are preserved when the function returns 0xAC 0xA8 0xA4 0xA0? 0xAC 0xA8 0xA4 0xA0? $s0 $s1 Before and after that the registers have been saved foo: addi,, -8 sw $s0, 4() sw $s1, 0() modifies $s0 and $s1 lw $s1, 0() lw $s0, 4() addi,, 8 jr $ra If the callee saves registers that are not used by the caller, this saving of registers is a waste The caller can use the save registers $s0 to $s7 before the function call, knowing that they are preserved when the function returns Name Number Use $t0-$t temporary (caller-saved) $s0-$s saved variables (callee-saved) $t8-$t temporary (caller-saved) The callee only saves the registers $s0 to $s7 If the caller use the $t registers and they are live before and after a function call, it must save these registers on the stack The callee can freely use the temporary registers $t0 to $t9, without saving them I II I II PC-Relative Addressing Pseudo-Direct Addressing Conditional branches compute their addresses relative to the program counter (PC) because the instructions have not enough address bits 0x40 lo: add $t1, $a0, $s0 0x44 lb $t1,0($t1) 0x48 add $t2, $a1, $s0 0x4c sb $t1, 0($t2) 0x50 addi $s0, $s0, 1 0x54 bne $t1, $0, lo 0x58 lw $s0,0() xercise: Compute the machine code for the bne instruction BTA for the bne instruction is 0x40 Calculate branch target address (BTA): BTA = PC imm * 4 rs rt 6 bits 16 bits I imm II The J and JAL instructions are encoded using the J-type But, the address is not 32 bits, only 26 bits 6 bits addr 26 bits A 32-bit Pseudo-Direct Address is computed as follows: Bits 1 to 0 (least significant) are always zero because word alignment of code Bits 27 to 2 is taken directly from the addr field of the machine code instruction Bits 31 to 28 are obtained from the four most significant bits from PC + 4 Note: JR instructions are not using Pseudo-Direct Addresses (it is in R- format) Compilers must make sure not to jump between segments of code I 0 II

7 25 26 Summary You are soon released from the lecture room Some key take away points: Two s complement is the standard way of representing negative and positive integer numbers (please do not fumble with the bags) MIPS and NIOS II main instruction formats are R-Type, I-Type, and J-Type Arguments and return values are passed in registers when calling functions If there are too many arguments, the stack is used Thanks for listening! I II I II