UNIT II PROCESSOR AND MEMORY ORGANIZATION

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processor, memory and I/O units; memory management Cache mapping techniques,

1 UNIT II PROCESSOR AND MEMORY ORGANIZATION Structural units in a processor; selection of processor & memory devices; shared memory; DMA; interfacing processor, memory and I/O units; memory management Cache mapping techniques, dynamic allocation - Fragmentation. OBJECTIVES: 2.1 STRUCTURAL UNITS IN A PROCESSOR:

3 BLOCK DIAGRAM OF STRUCTURAL UNITS:

4 ESSENTIAL CHARACTERISTICS:

5 SPECIFIC FEATURES:

6 2.2 Processor selection for an embedded system: Processor selection will be understood following cases:

7 2.3 MEMORY DEVICES:

10 2.4 MEMORY SELECTION FOR EMBEDEDD SYSTEM: 2.5 ALLOCATION OF MEMORY TO PROGRAM SEGMENTS AND BLOCKS AND MEMORY MAP OF A SYSTEM:

12 2.6DMA (Direct Memory Acess):

14 2.7INTERFACING PROCESSOR, MEMORIES AND I/O DEVICES:

15 2.8 MEMORY MANAGEMENT:

2.9 Cache mapping techniques: 2.9.1 Cache Usually designed with SRAM - faster but more expensive than DRAM Usually on same chip as processor space limited, so much smaller than off-chip main memory faster access (1 cycle vs.

16 2.9 Cache mapping techniques: Cache Usually designed with SRAM - faster but more expensive than DRAM Usually on same chip as processor space limited, so much smaller than off-chip main memory faster access (1 cycle vs. several cycles for main memory) Cache operation Request for main memory access (read or write) First, check cache for copy cache hit - copy is in cache, quick access cache miss - copy not in cache, read address and possibly its neighbors into cache Several cache design choices cache mapping, replacement policies, and write techniques

17 2.9.2 Cache Mapping is necessary as there are far fewer number of available cache addresses than the memory Are address contents in cache? Cache mapping used to assign main memory address to cache address and determine hit or miss Three basic techniques: Direct mapping Fully associative mapping Set-associative mapping Caches partitioned into indivisible blocks or lines of adjacent memory addresses usually 4 or 8 addresses per line 2.10 Direct Mapping Main memory address divided into 2 fields Index which contains - cache address,- number of bits determined by cache size Tag - compared with tag stored in cache at address indicated by index - if tags match, check valid bit Valid bit indicates whether data in slot has been loaded from memory Offset used to find particular word in cache line

2.11 Fully Associative Mapping Complete main memory address stored in each cache address All addresses stored in cache simultaneously compared

12 Set-Associative Mapping Compromise between direct mapping and fully associative mapping Index same as in direct mapping But, each cache

18 2.11 Fully Associative Mapping Complete main memory address stored in each cache address All addresses stored in cache simultaneously compared with desired address Valid bit and offset same as direct mapping 2.12 Set-Associative Mapping Compromise between direct mapping and fully associative mapping Index same as in direct mapping But, each cache address contains content and tags of 2 or more memory address locations Tags of that set simultaneously compared as in fully associative mapping Cache with set size N called N-way set-associative 2-way, 4-way, 8-way are common

19 2.12 Cache-Replacement Policy Technique for choosing which block to replace when fully associative cache is full when set-associative cache s line is full Direct mapped cache has no choice Random replace block chosen at random LRU: least-recently used replace block not accessed for longest time FIFO: first-in-first-out push block onto queue when accessed choose block to replace by popping queue 2.13 Cache Write Techniques When written, data cache must update main memory Write-through write to main memory whenever cache is written to Easiest to implement Processor must wait for slower main memory write Potential for unnecessary writes Write-back Main memory only written when dirty block replaced Extra dirty bit for each block set when cache block written to reduces number of slow main memory writes 2.14 Cache Impact on System Performance Most important parameters in terms of performance: Total size of cache - total number of data bytes cache can hold - tag, valid and other housekeeping bits not included in total Degree of associatively Data block size

20 Larger caches achieve lower miss rates but higher access cost 2.15 Cache Performance Trade-Offs Improving cache hit rate without increasing size Increase line size Change set-associativity 2.16 Memory Management Unit (MMU) Duties of MMU Handles DRAM refresh, bus interface and arbitration Takes care of memory sharing among multiple processors Translates logic memory addresses from processor to physical memory addresses of DRAM Modern CPUs often come with MMU built-in Single-purpose processors can be used 2.17 Dynamic Allocation Fragmentation: In computer science, dynamic memory allocation (also known as heap-based memory allocation) is the allocation of memory storage for use in a computer program during the runtime of that program. It can be seen also as a way of distributing ownership of limited memory resources among many pieces of data and code. Dynamically allocated memory exists until it is released either explicitly by the programmer, or by the garbage collector. This is in contrast to static memory allocation, which has a fixed duration. It is said that an object so allocated has a dynamic lifetime.

21 DETAILS: The task of fulfilling an allocation request consists of finding a block of unused memory of sufficient size. Problems exist during fulfilling allocation request o Internal and external fragmentation. Reduction needs special care, thus making implementation more complex (see algorithm efficiency). o Allocator's metadata can inflate the size of (individually) small allocations; Chunking attempts to reduce this effect. Usually, memory is allocated from a large pool of unused memory area called the heap (also called the free store). Since the precise location of the allocation is not known in advance, the memory is accessed indirectly, usually via a pointer reference. The precise algorithm used to organize the memory area and allocate and deallocate chunks is hidden behind an abstract interface and may use any of the methods described below. EFFICIENCY: The dynamic memory allocation algorithm actually used can impact performance significantly and a study conducted in 1994 by Digital Equipment Corporation illustrates the overheads involved for a variety of allocators. The lowest average instruction path length required to allocate a single memory slot was 52 (as measured with an instruction level profiler on a variety of software) CASE STUDY: Required Memory devices for an Automatic Washing machine, Chocolate vending machine and for a Digital Camera and Voice recorder.

22 Automatic Washing machine:

24 SUMMARY INTERNAL BUS: A set of paths that carry in parallel the signals between various internal structural units of processor. Its size is 64 bit in a 64-bit processor. ACCUMULATOR Also known as A or AC, or by other names. The register which holds the results of ALU operations. ADDRESSING MODE The math used to determine a memory location by the CPU, and the notation used to express it. ALU Arithmetic Logic Unit. Performs basic mathematical manipulations such as add, subtract, complement, negate, AND, OR. AND Logical operation where the result is 1 if ANDed terms both have the value 1. ANSI C American National Standards Institute standards for C language assembly language. BANK A logical unit of memory as determined by addressing modes and their restrictions. BIT FIELD A group of bits considered as a unit. A bit field may cross byte boundaries if supported by the compiler.

25 BLOCK Any section of C code enclosed by braces, { and }. A block is syntactically equivalent to a single instruction, but creates a new variable scope. BREAKPOINT A location to stop executing program code, enforced by internal or external hardware. Breakpoints are used in debugging programs. CAN Controller Area Network, developed by Bosch and Intel. It is an inter-module bus that links controlled devices. CHECKSUM A value which is the result of adding specific binary values. A checksum is often used to verify the integrity of a sequence of binary numbers. CROSS ASSEMBLER An assembler that runs on one type of computer and assembles the source code for a different target computer. For example, an assembler that runs on an Intel x86 machine and generates object code for Motorola's 68HC05. DEBUGGER A program which helps with system debugging where program errors are found and repaired. Debuggers support such features as breakpoints, dumping, memory modify. EMBEDDED Fixed within a surrounding system or unit. Also, engineered or intended to perform one specific function in a specific environment.

26 ENDIAN-NESS The distinction of multi-byte data storage convention. Little-endian store the leastsignificant byte first in memory. Big-endian stores the most-significant byte first in memory. HYSTERESIS The delay between the switching action of a control and the effect. Can be enforced to prevent rapid short-term reversals in the control's state. INDEX REGISTER Also known as X, IX or by other names. The register used to hold a value that becomes a factor in an indexed addressing mode. Frequently used for arithmetic operations, though without as many capabilities as an accumulator. INTERRUPT A signal sent to the CPU to request service. Essentially a subroutine outside the normal flow of execution, but with many extra considerations. LOGICAL OPERATOR Operators which perform logical operations on their operands. For example,!, &&,. MACHINE LANGUAGE Binary code instructions which can be "understood" by a specific CPU. More pedantically, binary numbers which, when represented as voltage signals within a microcontroller, drive the internal circuitry to perform further state changes.

27 MEMORY-MAPPED A virtual address or device is associated with an actual address in memory. CPU registers are often not memory-mapped. WATCHPOINT Like a breakpoint, except in the data area of memory rather than the code. Any access to this location with the specified access type (read, write,read/write) stops execution and switches control to the debugger.hardware support is required for realization of watchpoints. Watchpointsare not supported by all debugging tools. VOLATILE The quality of a value that changes unexpectedly. The compiler cannot trust that the value of a volatile variable remains constant over time, and therefore cannot perform certain optimizations. Declared explicitly by the programmer, or determined by the compiler. EMBEDDED SOFTWARE A software system that permanently resides in a device whose operations it controls. Typically, embedded systems are housed on flash memory or ROM chip and may be found in systems like cellular phones, household and office appliances having digital interfaces, medical equipment, automotive components, avionics etc. CROSS COMPILER A compiler that runs on one type of computer and compiles source code for a different target computer. For example, a compiler that runs on an Intel x86 and generates object code for Motorola's 68HC05.

28 COMPUTER OPERATING PROPERLY (COP) A peripheral or function that resets microcontroller function under questionable execution conditions. COP, as a word, is the name of the COP8 microcontroller product line from National Semiconductor. MASK A group of bits designed to set or clear specific positions in another group of bits when used with a logical operator.

29 POSSIBLE BIG QUESTIONS: 1.Explain about the different types of I/O devices with examples. (P.NO.98) 2.Differentiate synchronous, iso synchronous and asynchronous communications from serial devices. (P.NO. 99) 3.Give the examples of internal serial communication devices.(p.no.104) 4.Illustrate the parallel port devices. (P.NO.106) 5.What are all the sophisticated interfacing features in device ports. (P.NO.108). 6.Briefly explain about the timer and counting devices. (P.NO.109). 7.How can you make the serial communication using I 2 C, CAN and advanced I/O buses between the networked multiple devices? (P.NO.114) 8.Explain about the host system between the networked I/O multiple devices using the ISA,PCI,PCI-X and advanced buses. (p.no.118). 9.Modify the PCI and PCI/X buses. (P.NO.119). 10.Give short notes on advanced parallel high speed buses.(p.no.121) TEXT BOOK : Embedded Systems by Raj Kamal.

30 TWO MARK QUESTIONS: 1.Define parallel and serial port. A port for read and write operations on multiple bits at an instance is a parallel port. A port read and writes operations with one bit at an instance and where each bit of the message is separated by constant time interval. 2.What is mean by input buffer? A buffer where an input device puts a byte and the processor reads it later. 3.Define output buffer. A register buffer from where an output device receives the byte after a processor write operation. 4.Modify the handshaking signals. The signals before storing the bits at the port buffer or before accepting the bits from the port buffer. 5.What is the work of device? A unit that connects to the processing unit through the ports. It has fixed preassigned port addresses according to its interfacing circuit. 6.Write short notes on control and status register. A register for bits, which controls the actions of a device. It is for a write operation only. A register for bits, which reflects the current status at the port buffer. It is for a read operation only. The bit may or may not audio reset on device servicing. 7.What is half and full duplex mode? A serial port having one common I/O line. Example, a telephone line, message flows one way at an instance.

31 A serial port having two distinct I/O lines. Example a modem connection to the computer COM port. 8.Write the function of device decoder. A circuit to take the address bus signals as the input and generate a chip select signal, CS, for the port address selection. 9.Define UART. A standard asynchronous serial input and output port for serial bits. UART usually sends a byte in 10 bits format or 11 bits format. The 10 bits format is when a start bit precedes the 8 bit message ( character) and a stop bit succeeds the message. An 11-bit format is when a special bit also precedes the stop bit. 10.What is the use of TxD? A line used for transmission of UART serial bits. The 0 and 1 signals are at RS232C voltage levels when RS232C COM port is used or at the TTL levels in microcontrollers. 11. What is mean by COM port? port. A port at the computer where a mouse, modem or serial printers connects is a COM 12.Define protocol. A way of transmitting messages on a network by using a software for adding the additional bits like starting bits, headers, addresses of source and destination, error control bits and ending bits. Each layer or sub layer uses its protocol before a message transmits on a network. 13.Write short notes on HDLC. High Level Data Link Control protocol for synchronous communication between primary and secondary i.e master and slave. It is a bit oriented protocol.

32 14.Define real time. A time which always increments without stopping or resetting. 15.What is RTC? It is Real Time Clock that continuously generates interrupts at regular intervals endlessly. It ticks the other timers of the system. 16.Write the work of system clock. A clock scaled to the processor clock and which always increments without stopping or resetting and generates interrupts at present time intervals. 17.Write the function of time overflow or time out. A state in which the number of count inputs exceeded the last acquirable value and on reaching that state an interrupt can be generated. 18.Define time finish. A state after the timer acquired the present count value and stopped. An interrupt generates on finishing. 19.What is mean by counter. intervals. Unit for getting the count inputs on occurance of events that may be at irregular 20.Deine TDM. Time Division Multiplexing. A way in which in different time slots the message from different channels can be sent. 21.What is mean by demultiplexing? A way to separate a multiplexed input and direct the messages to multiple channels.

33 22.What is PSK? It is Phase Shifted Keying modulation. The 0 and 1 logic have different phases in a high frequency signal 23.Define QPSK. Quadrature Phase Shiht Keying. The pair of bits 00,01,10 and 11 are sent at different quadrant phase differences of a voice frequency signal. 24.What is PCI bus? A standard bus used as Peripheral Component Interconnect bus 25.Write the function of CAN bus. A standard bus used at the control area network in automotive electronics.

EE414 Embedded Systems Ch 5. Memory Part 2/2

EE414 Embedded Systems Ch 5. Memory Part 2/2 Byung Kook Kim School of Electrical Engineering Korea Advanced Institute of Science and Technology Overview 6.1 introduction 6.2 Memory Write Ability and Storage