Chip Errata for the MB96300/MB96600 Series MOVS/MOVSW Overlap of source and destination region, F 2 MC-16FX Microcontroller

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1 September 20, 2012 Chip Errata for the MOVS/MOVSW Overlap of source and destination region, F 2 MC-16FX Microcontroller This document describes the errata for the MOVS/MOVSW Overlap of source and destination region, F 2 MC-16FX Microcontroller. Compare this document to the device s data sheet for a complete functional description. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Problem Description This Customer information replaces CI E-MOVS_Overlap Part Number 16FXFL0049 (included in CI E-V32-MB96300_List_of_functional_limitations.pdf) CI This limitation describes a deviation from the instruction execution rule of the CPU (MOVS/I and MOVSW/I instruction) in rare special cases. If the source and destination areas are overlapping, the instructions MOVS/I and MOVSW/I may show different behaviour with respect to the instruction execution rules. The effect depends on the condition, if or a bank register is changed short before the execution. In case the source and destination area is not overlapping, the result of the execution is not affected. The C compiler will not generate code, which could produce such a deviation from the execution rule. It is also very unlikely to find such a sequence in normal written assembler code. However, the possibility exists for such a scenario and depends on special usage. Problem Conditions Problem may occur if all of the following conditions are met Instruction MOVS/I or MOVSW/I is used Source and destination address overlap or a bank register is changed short before execution of MOVS/I resp. MOVSW/I Cypress Semiconductor Corporation 198 Champion Court San Jose, CA April 23, 2016 Document No Rev. *A 1

2 Affected Devices Series Product name MB96300 Series EVA chip MB96V300, MB96V300B, MB96V300C MB96310 MB96F313ASA, MB96F313ASB, MB96F313AWA, MB96F313AWB, MB96F313RSA, MB96F313RSB, MB96F313RWA, MB96F313RWB, MB96F313YSA, MB96F313YSB, MB96F313YWA, MB96F313YWB, MB96F315ASA, MB96F315ASB, MB96F315AWA, MB96F315AWB, MB96F315RSA, MB96F315RSB, MB96F315RWA, MB96F315RWB, MB96F315YSA, MB96F315YSB, MB96F315YWA, MB96F315YWB MB96320 MB96F326ASA, MB96F326ASB, MB96F326AWA, MB96F326AWB, MB96F326RSA, MB96F326RSB, MB96F326RWA, MB96F326RWB, MB96F326YSA, MB96F326YSB, MB96F326YWA, MB96F326YWB MB96330 MB96F336USA, MB96F336UWA, MB96F338RSA, MB96F338RWA, MB96F338USA, MB96F338UWA, MB96F338YSA, MB96F338YWA MB96340 MB96345RSA, MB96345RWA, MB96345YSA, MB96345YWA, MB96346RSA, MB96346RWA, MB96346YSA, MB96346YWA, MB96F345DSA, MB96F345DSB, MB96F345DWA, MB96F345DWB, MB96F345FSA, MB96F345FSB, MB96F345FWA, MB96F345FWB, MB96F346ASA, MB96F346ASB, MB96F346ASC, MB96F346AWA, MB96F346AWB, MB96F346AWC, MB96F346RSA, MB96F346RSB, MB96F346RSC, MB96F346RWA, MB96F346RWB, MB96F346RWC, MB96F346YSA, MB96F346YSB, MB96F346YSC, MB96F346YWA, MB96F346YWB, MB96F346YWC, MB96F347ASA, MB96F347ASB, MB96F347ASC, MB96F347AWA, MB96F347AWB, MB96F347AWC, MB96F347RSA, MB96F347RSB, MB96F347RSC, MB96F347RWA, MB96F347RWB, MB96F347RWC, MB96F347YSA, MB96F347YSB, MB96F347YSC, MB96F347YWA, MB96F347YWB, MB96F347YWC, MB96F348ASA, MB96F348ASB, MB96F348ASC, MB96F348AWA, MB96F348AWB, MB96F348AWC, MB96F348CSA, MB96F348CSB, MB96F348CSC, MB96F348CWA, MB96F348CWB, MB96F348CWC, MB96F348HSA, MB96F348HSB, MB96F348HSC, MB96F348HWA, MB96F348HWB, MB96F348HWC, MB96F348RSA, MB96F348RSB, MB96F348RSC, MB96F348RWA, MB96F348RWB, MB96F348RWC, MB96F348TSA, MB96F348TSB, MB96F348TSC, MB96F348TWA, MB96F348TWB, MB96F348TWC, MB96F348YSA, MB96F348YSB, MB96F348YSC, MB96F348YWA, MB96F348YWB, MB96F348YWC MB96350 MB96F353ASA, MB96F353ASB, MB96F353AWA, MB96F353AWB, MB96F353RSA, MB96F353RSB, MB96F353RWA, MB96F353RWB, MB96F353YSA, MB96F353YSB, MB96F353YWA, MB96F353YWB, MB96F355ASA, MB96F355ASB, MB96F355AWA, MB96F355AWB, MB96F355RSA, MB96F355RSB, MB96F355RWA, MB96F355RWB, MB96F355YSA, MB96F355YSB, MB96F355YWA, MB96F355YWB, MB96F356ASA, MB96F356ASB, MB96F356AWA, MB96F356AWB, MB96F356RSA, MB96F356RSB, MB96F356RWA, MB96F356RWB, MB96F356YSA, MB96F356YSB, MB96F356YWA, MB96F356YWB MB96370 MB96375RSA, MB96375RWA, MB96F378HSA, MB96F378HSB, MB96F378HWA, MB96F378HWB, MB96F378TSA, MB96F378TSB, MB96F378TWA, MB96F378TWB, MB96F379RSA, MB96F379RSB, MB96F379RWA, MB96F379RWB, MB96F379YSA, MB96F379YSB, MB96F379YWA, MB96F379YWB April 23, 2016 Document No Rev. *A 2

3 Series Product name MB96380 MB96384RSA, MB96384RSB, MB96384RSC, MB96384RWA, MB96384RWB, MB96384RWC, MB96384YSA, MB96384YSB, MB96384YSC, MB96384YWA, MB96384YWB, MB96384YWC, MB96385RSA, MB96385RSB, MB96385RSC, MB96385RWA, MB96385RWB, MB96385RWC, MB96385YSA, MB96385YSB, MB96385YSC, MB96385YWA, MB96385YWB, MB96385YWC, MB96F385RSA, MB96F385RSB, MB96F385RWA, MB96F385RWB, MB96F385YSA, MB96F385YSB, MB96F385YWA, MB96F385YWB, MB96F386RSA, MB96F386RSB, MB96F386RSC, MB96F386RWA, MB96F386RWB, MB96F386RWC, MB96F386YSA, MB96F386YSB, MB96F386YSC, MB96F386YWA, MB96F386YWB, MB96F386YWC, MB96F387RSA, MB96F387RSB, MB96F387RSC, MB96F387RWA, MB96F387RWB, MB96F387RWC, MB96F387YSA, MB96F387YSB, MB96F387YSC, MB96F387YWA, MB96F387YWB, MB96F387YWC, MB96F388HSA, MB96F388HSB, MB96F388HWA, MB96F388HWB, MB96F388TSA, MB96F388TSB, MB96F388TWA, MB96F388TWB, MB96F389RSA, MB96F389RSB, MB96F389RWA, MB96F389RWB, MB96F389YSA, MB96F389YSB, MB96F389YWA, MB96F389YWB MB96390 MB96393RSA, MB96393RWA, MB96395RSA, MB96395RWA, MB96F395RSA, MB96F395RSB, MB96F395RWA, MB96F395RWB, MB96F395YSA, MB96F395YSB, MB96F395YWA, MB96F395YWB MB96600 Series MB96610 MB96620 MB96630 MB96640 MB96650 MB96670 MB96680 MB96690 MB966A0 MB966B0 MB966C0 MB96F612RA, MB96F612RB, MB96F612AA, MB96F612AB MB96F613RA, MB96F613RB, MB96F613AA, MB96F613AB MB96F615RA, MB96F615RB, MB96F615AA, MB96F615AB MB96F622RA, MB96F622RB, MB96F622AA, MB96F622AB MB96F623RA, MB96F623RB, MB96F623AA, MB96F623AB MB96F625RA, MB96F625RB, MB96F625AA, MB96F625AB MB96F633RA, MB96F633RB, MB96F633AA, MB96F633AB MB96F635RA, MB96F635RB, MB96F635AA, MB96F635A5 MB96F636RA, MB96F636RB MB96F637RA, MB96F637RB MB96F643RA, MB96F643RB, MB96F643AA, MB96F643AB MB96F645RA, MB96F645RB, MB96F645AA, MB96F645AB MB96F646RA, MB96F646RB MB96F647RA, MB96F647RB MB96F653RA, MB96F653RB, MB96F653AA, MB96F653AB MB96F655RA, MB96F655RB, MB96F655AA, MB96F655AB MB96F656RA, MB96F656RB MB96F657RA, MB96F657RB MB96F673RA, MB96F673RB, MB96F673AA, MB96F673AB MB96F675RA, MB96F675RB, MB96F675AA, MB96F675AB MB96F683RA, MB96F683RB, MB96F683AA, MB96F683AB MB96F685RA, MB96F685RB, MB96F685AA, MB96F685AB MB96F693RA, MB96F693RB, MB96F693AA, MB96F693AB MB96F695RA, MB96F695RB, MB96F695AA, MB96F695AB MB96F696RA, MB96F696RB MB96F6A5RA, MB96F6A5RB, MB96F6A5AA, MB96F6A5AB MB96F6A6RA, MB96F6A6RB MB96F6B5RA, MB96F6B5RB, MB96F6B5BA, MB96F6B5BB MB96F6B6RA, MB96F6B6RB MB96F6C5RA, MB96F6C5RB, MB96F6C5BA, MB96F6C5BB MB96F6C6RA, MB96F6C6RB April 23, 2016 Document No Rev. *A 3

4 Affected Modules This problem is affecting the CPU. Detailed explanation Problem conditions (1) Instruction is one of the affected instructions MOVS (MOVSI) MOVSW (MOVSWI) (2) Overlap of source and destination area The source and destination array is in the same memory bank The source and destination area are overlapping, so that the source data gets destroyed during the operation o o o < (for MOVS/I) < 2* (for MOVSW/I) < (only for the case of wrap-around where =0xFFFF and =00) (3) Changing or a bank register before MOVS/MOVSW gets executed if all following conditions are met Change of a bank register (,, PCB, SSB, USB) at the instruction one or two instructions before MOVS/I,MOVSW/I and the changed bank register is used by the MOVS/I,MOVSW/I instruction (either it is source bank or destination bank for the data transfer) or change of one or two instructions before the MOVS/I, MOVSW/I instruction is not changed. In case of changing at the same moment or after or the bank, correct operation is ensured. The execution waits until is updated. is not changed after or the bank. The execution waits until is updated. Root cause 1. F²MC-16FX MCUs are using buffered accesses for continuous data transfers. The bus interface re-adjusts the data transfers address alignments and uses optimum transfer size for better utilization of the available bus bandwidth. 2. In case of overlap of the source and destination array, these optimizations are disabled. The target is to reach exact matching of the execution rules, because the use of a buffer or change of the transfer size would change the result of operation in such a case. 3. The overlap condition has missing stall condition of the processor pipeline. and bank register changes are not considered. and changes are taken into account by the execution of MOVS/I, MOVSW/I. April 23, 2016 Document No Rev. *A 4

5 Normal function The execution according the rules defined in the F²MC-16FX programming manual is as follows. MOVS/I The following is repeated until becomes equal to "0" () () (Byte transfer) () ()+1, () ()+1 () () 1 MOVSW/I The following is repeated until becomes equal to "0" () () (Word transfer) () ()+2, () ()+2 () () 1 Thus the result of the operation has to be in a way, as it would be copied byte-wise (MOVS/I) or word-wise (MOVSW/I). Wrong behavior The missing stall condition (not detecting the required wait time, until and the bank registers have stabilized) may cause wrong calculation, that there is an overlap of the source and destination region or not. This could lead to cases, where the optimizations (buffered access and changed transfer size) are not switched off. Thus the result of the operation may look different in case of overlapping source and destination arrays. April 23, 2016 Document No Rev. *A 5

6 Example The following sequence of assembler instructions produces wrong overlap detection by changing the bank pointer short before the MOVS instruction. is changed from 0x01 to, thus is equal to. The source address () is H and destination address () is H. MOVL A,# H MOV,A ; set the source bank to MOVW A,#1 MOV,A ; set the destination bank to 0x01 MOVW,#73 ; byte count MOVW A,#0 ; =00 (source pointer), =01 ; (destination pointer) NOP MOV,A ; set the destination bank to MOVS, The following table shows the content of memory before and after the execution. Bold and cursive values are the result of the copy in the destination region. Correct behaviour Wrong behaviour Address Initial memory Memory after execution (16FX implementation. without changing or a bank register, or with changing RL0 or, right before MOVS gets executed) Memory after execution (16FX 0x55.. Remarks At other address offsets ( - > 1) of the source and target region, the result is not an exact copy of the source data. However a deviation from the execution rule is noticeable in some cases. The reason for the exact copy in the special case ( = 1; together with special code sequences, which let the overlap detection fail as late change of or bank) is the existence of a buffer in the bus interface of 16FX. Thus the first write transfer will not overwrite the source data before reading the next. April 23, 2016 Document No Rev. *A 6

7 MOVS flow of correct behaviour example MOVS flow of wrong @ x11 Initial Memory 01 @ x11 Initial Memory @ Memory (after MOVS 1 st step) 0x11-> 01->02 @ Memory (after MOVS 1 st step) 0x11-> 01->03 00->02 @ Memory (after MOVS 2 nd step) -> 02->03 @ Memory (after MOVS 3 rd step) -> 03->04 @ Memory (after MOVS 2 nd step) ->0x11 -> 03->05 02->04 #70->#68 @ Memory (after MOVS 4 th step) -> 04->05 03->04 #69->#68 Transfer two bytes at once. Use aligned word transfers on internal bus. The re-alignment requires @ Memory (result) 048 @ x11 Memory (result) #00 Empty April 23, 2016 Document No Rev. *A 7

8 Possible workaround Do not overlap source and destination area There is no limitation when the source and destination region not overlaps. Either < (except the following case =0xFFFF and =00) or (MOVS), 2 * (MOVSW). Usually this is ensured by the normal use of the instruction. If the source and destination areas are not overlapping, always an exact copy of the source region to the target region is done. Change and bank registers latest 3 instructions before MOVS/MOVSW If and,, SSB, USB or PCB are stable in the pipeline Stage 3 of the processor pipeline, before decoding of MOVS/I, MOVSW/I starts in Stage 0, then the overlap detection calculates the correct result and the copy process will follow the execution rule. Corrective action by Cypress Semiconductor Cypress Semiconductor does not plan a redesign of the affected devices for this issue. April 23, 2016 Document No Rev. *A 8

9 Document History Page Document Title Chip Errata for the MOVS/MOVSW Overlap of source and destination region, F 2 MC-16FX Microcontroller Document Number Rev. ECN No. Orig. of Change Description of Change ** KHAS Revision 1.0 1). Used latest template 2). Added Product name MB96300 Series Revision 1.1 Notes revised *A KHAS Migrated to Cypress format Cypress Semiconductor 198 Champion Court San Jose, CA Phone Fax http// Cypress Semiconductor Corporation, This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ( Cypress ). This document, including any software or firmware included or referenced in this document ( Software ), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ( Unintended Uses ). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. April 23, 2016 Document No Rev. *A 9

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