ECEN 468 Advanced Digital System Design

Transcription

1 ECEN 468 Advanced Digital System Design Lecture 19: Logic Design with Verilog

2 Verilog Module v Description of internal structure/function o Implicit semantic of time associated with each data object/ signal o Implementation is hidden to outside world v Communicate with outside through ports o Port list is optional v Achieve hardware encapsulation module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); a b sum c_out_bar c_out 2

3 Implicit Structural Description module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; assign { c_out, sum } = a + b; // Continuous assignment Concatenation a b Add_half sum c_out 3

4 Module Instantiation v Accomplished by entering o Module name as a module item within a parent module o Signal identifiers at appropriate ports v Module instantiation needs a module identifier v A module is never declared within another module v The order of ports in instantiation usually matches the order in module declaration 4

5 Design a Full Adder sum HA = a b c_out HA = a b sum FA = a b c_in c_out FA = a b + b c_in + a c_in sum FA = (a b) c_in c_out FA = (a b) c_in + a b a + b = a(b+b ) + (a+a )b = ab + ab + a b ab + bc + ac = ab + (a+b)c = ab + (a b+ab)c = ab + a bc+abc = ab + (a b)c 5

6 Full Adder 2 Half Adders sum HA = a b c_out HA = a b sum FA = (a b) c_in c_out FA = (a b) c_in + a b c_in Add_half (a b) c_in a Add_half a b (a b) c_in b a b (a b) c_in + a b 6

7 Full Adder in Verilog c_in a b Add_half w1 a b w2 a b Add_half sum (a b) c_in w3 (a b) c_in c_out (a b) c_in + a b module Add_full ( sum, c_out, a, b, c_in ); // parent module input a, b, c_in; output c_out, sum; wire w1, w2, w3; Module instance Add_half M1 ( w1, w2, a, b name ); Add_half M2 ( sum, w3, w1, c_in ); // child module or ( c_out, w2, w3 ); // primitive instantiation 7

8 Verilog Primitives v Basic element to build a module, such as nand, nor, buf and not gates v Never used stand-alone in design, must be within a module v Pre-defined or user-defined v Identifier (instance name) is optional v Output is at left-most in port list v Default delay = 0 8

9 Delay Assignment module AOI_4 ( y, x1, x2, x3, x4 ); input x1, x2, x3, x4; output y; wire y1, y2; and #1 ( y1, x1, x2 ); and #1 ( y2, x3, x4 ); nor #1 ( y, y1, y2 ); x1 x2 x3 x4 y2 y1 y 9

10 Explicit Structural Descriptions module AOI_4 ( y, x1, x2, x3, x4 ); input x1, x2, x3, x4; output y; wire y1, y2; and #1 ( y1, x1, x2 ); and #1 ( y2, x3, x4 ); nor #1 ( y, y1, y2 ); x1 x2 x3 x4 y2 y1 y 10

11 Implicit Structural Description module nand2_rtl ( y, x1, x2 ); input x1, x2; output y; assign y = x1 ~& x2; module nand2_rtl ( y, x1, x2 ); input x1, x2; output y; wire y = x1 ~& x2; Explicit continuous assignment Implicit continuous assignment Continuous assignment Static binding between LHS and RHS No mechanism to eliminate or alter the binding 11

12 Multiple Assignments module multiple_gates ( y1, y2, y3, a1, a2, a3, a4 ); input a1, a2, a3, a4; output y1, y2, y3; assign y1 = a1 ^ a2, y2 = a2 a3, y3 = a1 + a4; 12

13 Structural Connections v By order v By name v Empty port module child( a, b, c ); module parent; wire u, v, w; child m1( u, v, w ); child m2(.c(w),.a(u),.b(v) ); child m3( u,, w ); 13

14 Behavioral Descriptions: Data Flow module comparetor ( lt, gt, eq, A, B ); input A, B; output lt, gt, eq; reg lt, gt, eq; ( A, B ) begin lt = (A < B); gt = (A > B); eq = (A == B); end 14

15 Behavioral Descriptions: Algorithm-based module comparetor ( lt, gt, eq, A, B ); input A, B; output lt, gt, eq; reg lt, gt, eq; ( A, B ) begin lt = 0; gt = 0; eq = 0; if ( A == B ) eq = 1; else if ( A > B ) gt = 1; else lt = 1; end 15

16 Description Styles v Structural o Explicit structural o Implicit structural Explicit continuous assignment Implicit continuous assignment v Behavioral o Data flow/rtl o Algorithm-based 16

17 Arrays of Instances module flop_array(q, in, clk, rst); input [7:0] in; rst input clk, rst; output [7:0] q; Flip_flop M[7:0] (q, in, clk, rst); in[7:0] pipe[7:0] pipe[23:16] q[7:0] module pipeline(q, in, clk, rst ); input [7:0] in; input clk, rst; output [7:0] q; clk wire [23:0] pipe; flop_array M[3:0] ({q, pipe}, {pipe, in}, clk, rst); 17

18 Verilog for Synthesis module comp(lt,gt,eq,a0,a1,b0,b1); input a0, a1, b0, b1; output lt, gt, eq; wire w1, w2, w3, w4, w5, w6, w7; or (lt, w1, w2, w3); nor (gt, lt, eq); and (w1, w6, b1); and (w2, w6, w7, b0); and (w3, w7, b0, b1); not (w6, a1); not (w7, a0); xnor (w4, a1, b1); xnor (w5, a0, b0); module comp(lt, gt, eq, a, b); input [1:0] a, b; output lt, gt, eq; assign it = ( a < b ); assign gt = ( a > b ); assign eq = ( a == b ); 18

19 Language Conventions v Case sensitive v Instance of a module must be named v Keywords are lower-case v Comments start with //, or blocked by /* */ 19