Section 5 SERCOM. Tasks SPI. In this section you will learn:

Transcription

1 Section 5 SERCOM SPI Tasks In this section you will learn: SPI protocol SERCOM Engine on SAMD20 How to use SERRCOM in SPI mode Implementation of SPI communication 04/12/2013

2 Table of Contents 1. The SPI Protocol SPI data transmission The SERCOM Serial Communication Interface Port Configuration for SERCOM SERCOM Clock Baud Rate Generator SERCOM in SPI mode Port Configuration for SERCOM in SPI mode SERCOM Registers SERCOM clock in SPI mode Address Recognition in Slave mode SPI Interrupts SPI Data Transmission in SAMD Initializing the SERCOM in SPI mode Task 1: Transfer a byte in Master Mode Which Registers Configure SERCOM in SPI mode? Understanding the SAMD20 System level header files component_sercom.h Configuring SERCOM to operate as SPI Master Accessing the SERCOM Registers for SPI Transmitting data as SPI Master Conclusion ii

3 1. The SPI Protocol Serial Peripheral Interface (SPI) is a synchronous, serial, full duplex communication protocol established by Motorola. It is a Master-Slave type protocol in which the Master initiates the communication with one or more slaves. SPI is a serial communication protocol, hence a clock signal is required to control data exchange. Since the Master initiates the data transfer, it provides the clock signal for synchronization. No data is transferred without the clock signal. The SPI protocol has the following signals as shown in Figure 1: SCLK Provides the Serial Clock. MOSI (Master Out Slave In) Serial data transmitted out of the Master and received by the Slave. MISO (Master In Slave Out) Serial Data received by the Master and Transmitted out of the Slave. SS/CS (Slave Select/Chip Select) Each Slave has a unique chip select line. When the Master drives this low, the corresponding Slave will respond to the Master s clock and data signal. Figure 1. Master and Slave devices in SPI 1 SPI is a full-duplex communication protocol, hence data is transmitted or exchanged in both directions. When either the Master or Slave is transmitting some data through the Serial Data Out (SDO) line, data is also being simultaneously received through the Serial Data In (SDI) line. Therefore, before attempting to transfer the second bit, the incoming data must be read (even if the received data is a dummy). 1 References: Page 1 of 14

4 1.1 SPI data transmission Data transmission starts with the Master holding down the chip select line of the slave it wants to talk to. Then, for each SPI transaction full-duplex communication occurs as follows: The Master starts toggling the CLK line at a set frequency and sends a bit out on its SDO (Master Out) line. The Slave immediately reads this bit from its SDI (Slave IN) line. The Slave then sends a bit out on its SDO (Slave Out) line. The Master immediately reads this bit from its SDI (Master IN) line. Therefore even if a device wants to only transmit, it MUST receive data which can then be discarded. Thus a data loop is created between the two devices as shown in Figure 2. Figure 2. Data transmission in SPI 2 Data transmission can take multiple clock cycles. Once transmission in completed, the Master stops issuing CLK signal and de-asserts the Chip Select line. Data is propagated by the transmitter during the rising or falling edge of the CLK signal and is latched by the receiver during the opposite edge, as shown in Figures 3-6. Based on how data is propagated and sampled w.r.t. clock, two parameters are defined: Clock Polarity (CPOL) and Clock Phase (CPHA). When CPOL=1, if CPHA=1, data is propagated on the clock s falling edge and captured on the rising edge, as shown in Figure 3. The four possible modes of data transmission are shown in Table 1. 2 References: Page 2 of 14

5 Figure 3. CPOL=1 CPHA=1 Figure 5. CPOL=0 CPHA=1 Figure 4. CPOL=0 CPHA=0 Figure 6. CPOL=1 CPHA=0 Table 1. SPI modes Mode CPOL CPHA Leading Edge Trailing Edge Rising, sample Falling, setup Rising, setup Falling, sample Falling, sample Rising, setup Falling, setup Rising, sample Leading edge is the first clock edge in a clock cycle, while trailing edge is the second clock edge in a clock cycle. 2. The SERCOM Serial Communication Interface The SAMD20 has a Serial Communication Interface, dubbed SERCOM, which supports a number of communication protocols such as SPI, TWI, and USART. The SERCOM engine has common resources which can be used for all three communication protocols. Figure 7 shows the SERCOM block diagram. Page 3 of 14

6 Figure 7. SERCOM block diagram It has common hardware for Baud Rate Generator, Transmitter/Receiver, and other hardware control block such as Address Matching. The Control logic to configure each of these hardware entities is also common and are configured according to the mode in which they are being used. SERCOM interrupt services are also available for which the interrupt controller needs to be configured. 2.1 Port Configuration for SERCOM There are four hardware pins dedicated to the SERCOM engine PAD[3:0]. The signals from I 2 C, SPI and USART are routed through these pins via a multiplexer. However, they need to be configured to be used in each of these modes. We have already learned Port Control in SAMD20 in the previous sections, including how to use them to perform a peripheral function. Referring to Table 6-1 of the SAMD20 datasheet, for a hardware pin to perform as SERCOM, which peripheral function must be chosen? 2.2 SERCOM Clock SERCOM uses the bus clock (APB clock) and two generic clocks core clock and slow clock. The core clock is used when the SERCOM is running as a Master and the slow clock is used to perform certain specific functions. 2.3 Baud Rate Generator Read section on page 341 of the SAMD20 datasheet and learn about the SERCOM baud-rate generator. Page 4 of 14

7 3. SERCOM in SPI mode Figure 8 shows the SERCOM transmitter and receiver in SPI mode. A SPI device, whether Master or Slave, has a transmit buffer, a shift register, and 2 receive buffers. In addition, when operating as a Master, a baud rate generator is utilized to provide clock signal. When operating as a slave, address matching logic is used to figure out if that particular slave was the intended recipient of the data transmitted by the Master. The SAMD20 SERCOM supports all four SPI modes and can operate both LSB and MSB first data transmissions. Figure 8. SERCOM in SPI mode 3.1 Port Configuration for SERCOM in SPI mode For the hardware pins to be used in SPI mode, the I/O lines must be configured to operate in peripheral mode. This has already been covered in the Port Control Section. Referring to Table 6-1 of the SAMD20 datasheet, for a hardware pin to perform as SERCOM, which peripheral function must be chosen? 3.2 SERCOM Registers The registers to configure the SERCOM engine to operate in SPI mode is as shown in Table 2. Page 5 of 14

8 Table 2. SERCOM registry summary Offset Register Name Access 0x00 Control A CTRLA R, R/W 0x04 Control B CTRLB R, R/W 0x08 Debug Control DBGCTRL R, R/W 0x0A Baud Rate BAUD R/W 0x0C Interrupt Enable Clear INTENCLR R, R/W 0x0D Interrupt Enable Set INTENSET R, R/W 0x0E Interrupt Flag Status Clear INTFLAG R, R/W 0x10 Status STATUS R, R/W 0x14 Address ADDR R, R/W 0x18 Data DATA R, R/W Read the Register Description section on page 380 of Section 26 in the SAMD20 datasheet and learn the functions of the different registers. 3.3 SERCOM clock in SPI mode In SPI master mode, the serial clock (SCK) is generated internally using the SERCOM baud rate generator. In SPI slave, the clock is provided by an external master on the SCK pin. 3.4 Address Recognition in Slave mode When the SPI is configured for slave operation with address recognition, the SERCOM address recognition logic is enabled. When address recognition is enabled, the first character in a transaction is checked for an address match. If there is a match, then the Receive Complete Interrupt flag in the Interrupt Flag Status and Clear register is set, the MISO output is enabled and the transaction is processed. If there is no match, the transaction is ignored. 3.5 SPI Interrupts The SPI has the following interrupt sources: Receive Complete Transmit Complete Data Register Empty Page 6 of 14

9 Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled setting the corresponding bit in the Interrupt Enable Set register and disabled by setting the corresponding bit in the Interrupt Enable Clear register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the SPI is reset. The SPI module has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which interrupt condition has occurred. 3.6 SPI Data Transmission in SAMD20 Read the Transferring Data section on page 375 of Section 26 in the SAMD20 datasheet and learn how data is transmitted as Master and Slave in SAMD20 using SPI protocol. 3.7 Initializing the SERCOM in SPI mode The basic steps in configuring the SERCOM engine to operate in SPI mode are as follows: 1. The SPI mode must be set as Slave or Master by writing 0x2 or 0x3 to the operating mode bit in Control A register (CTRLA.MODE). 2. Transfer mode must be selected by writing Clock Polarity Bit and Clock Phase bit in the Control A register (CTRLA.CPOL and CTRLA.CPHA). The different SPI modes are already covered in Table Transaction format must be selected by writing the Frame Format bit group in the Control A register (CTRLA.FORM). 4. SERCOM pad to use for the receiver must be selected by writing the Data In Pinout bit in the Control A register (CTRLA.DIPO). 5. SERCOM pads to use for the transmitter, slave select, and serial clock must be selected by writing the Data Out Pinout bit group in the Control A register (CTRLA.DOPO). 6. Character size must be selected by writing the Character Size bit in the Control B register (CTRLB.CHSIZE). 7. Data direction must be selected by writing the Data Order bit in the Control A register (CTRLA.DORD). 8. If SPI is used in master mode, the Baud register (BAUD) must be written with the right value to generate the desired baud rate. 9. The receiver can be enabled by writing a one to the Receiver Enable bit in the Control B register (CTRLB.RXEN). 10. Once the entire configuration is finished, the SPI module can be enabled by setting the Enable bit in the Control A register (CTRLA.ENABLE). The SPI module can be disabled by clearing the Enable bit in the Control A register (CTRLA.ENABLE). 11. The SPI is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST). All SPI registers except DBGCTRL, will be reset to their initial state, and the SPI module will be disabled. 4. Task 1: Transfer a byte in Master Mode Your task is to write a function that will configure the SAMD20 registers to operate the SERCOM engine in SPI mode. The I/O lines have to be set to perform the SPI peripheral function. The SAMD20 device should be set to work as a SPI Master and transmit a byte of data. Page 7 of 14

10 4.1 Which Registers Configure SERCOM in SPI mode? We have already studied how to configure the SERCOM engine in SAMD20 to operate in SPI mode. We also know the registers available that configure and control the SERCOM. Let us recollect what has been covered so far: 1. Enable Core Clock and APB clock: Since we have not explained clocks in SAMD20, the function to perform this will be provided to you. 2. Port Configuration: There four I/O lines that participate in SPI transmission MISO, MOSI, SCLK, and SS. These should be configured as per Table 3. Along with setting the I/O direction, the additional settings required to perform the peripheral functions are: a. Set the PMUXEN bit of the PINCFGy register b. Configure the PMUXn register such that the I/O pins serve as SERCOM Table 3. SPI I/O lines configuration Pin Master SPI Slave SPI MOSI Output Input MISO Input Output SCK Output Input SS Output Input 3. SERCOM Configuration: The SERCOM related configuration to operate SERCOM in SPI mode are as follows: a. Set the SPI mode of the device Master or Slave b. Set the clock polarity and phase, i.e., SPI mode of transmission as covered in Table 1 c. Set the transaction format d. Set the DIPO and DOPO bits e. Set the byte size for transmission 8 bits or 9 bits f. Decide whether MSB or LSB should be transmitted first g. Assign the right value to the BAUD register h. Enable SPI module For I/O pins to serve as SERCOM, based on the table 6-1 on Page 15 of the SAMD20 datasheet, Peripheral D should be chosen. Therefore in Step #2.b what should be the value of the PMUXn register? Which registers from Table 2 can be used to accomplish Step #3 mentioned above? Now complete the Table 4 below. Page 8 of 14

11 Table 4. Registers to configure SERCOM in SPI mode Register Function 4.2 Understanding the SAMD20 System level header files You have been provided with an Atmel Studio project template to work on. To use this project, you need to understand the header file that describes everything required to configure the SERCOM engine to operate in SPI mode component_sercom.h The component_sercom.h header file has important definitions pertaining to the SERCOM engine. It defines a Union called Sercom that lists all the serial communication protocols as shown below: typedef union { SercomI2cm I2CM; /**< Offset: 0x00 I2C Master Mode */ SercomI2cs I2CS; /**< Offset: 0x00 I2C Slave Mode */ SercomSpi SPI; /**< Offset: 0x00 SPI Mode */ SercomUsart USART; /**< Offset: 0x00 USART Mode */ } Sercom; Since we are dealing with the SPI protocol in this section we are concerned with only the following member: SercomSpi SPI; The SercomSpi member is basically a structure that defines all the registers related to the SPI protocol as shown below: typedef struct { /* SPI Mode */ IO SERCOM_SPI_CTRLA_Type CTRLA; /**< Offset: 0x00 (R/W 32) SPI Control Register A */ IO SERCOM_SPI_CTRLB_Type CTRLB; /**< Offset: 0x04 (R/W 32) SPI Control Register B */ IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< Offset: 0x08 (R/W 8) SPI Debug Register */ RoReg8 Reserved1[0x1]; IO SERCOM_SPI_BAUD_Type BAUD; /**< Offset: 0x0A (R/W 8) SPI Baud Rate Register */ RoReg8 Reserved2[0x1]; IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< Offset: 0x0C (R/W 8) SPI Interrupt Enable Clear Register */ IO SERCOM_SPI_INTENSET_Type INTENSET; /**< Offset: 0x0D (R/W 8) SPI Interrupt Enable Set Register */ IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< Offset: 0x0E (R/W 8) SPI Interrupt Flag Status and Clear Register */ RoReg8 Reserved3[0x1]; IO SERCOM_SPI_STATUS_Type STATUS; /**< Offset: 0x10 (R/W 16) SPI Status Register */ RoReg8 Reserved4[0x2]; IO SERCOM_SPI_ADDR_Type ADDR; /**< Offset: 0x14 (R/W 32) SPI Address Register */ IO SERCOM_SPI_DATA_Type DATA; /**< Offset: 0x18 (R/W 16) SPI Data Register */ } SercomSpi; You should already be familiar with these registers which were listed in Table 2 of this section. The comment alongside each register mentions the register memory offset, read/ write permissions, register size in bits, and description of the register. Page 9 of 14

12 Each register is assigned a type such as SERCOM_SPI_CTRLA_Type: typedef union { struct { uint32_t SWRST:1; /*!< bit: 0 Software Reset */ uint32_t ENABLE:1; /*!< bit: 1 Enable */ uint32_t MODE:3; /*!< bit: Operating Mode */ uint32_t :2; /*!< bit: Reserved */ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ uint32_t :8; /*!< bit: Reserved */ uint32_t DOPO:1; /*!< bit: 16 Data Out Pinout */ uint32_t :3; /*!< bit: Reserved */ uint32_t DIPO:2; /*!< bit: Data In Pinout */ uint32_t :2; /*!< bit: Reserved */ uint32_t FORM:4; /*!< bit: Frame Format */ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ uint32_t DORD:1; /*!< bit: 30 Data Order */ uint32_t :1; /*!< bit: 31 Reserved */ } bit; /*!< Structure used for bit access */ uint32_t reg; /*!< Type used for register access */ } SERCOM_SPI_CTRLA_Type; Clearly, this is a bit-wise description of the register. Refer to Figure 9 below which shows the bit wise description of the Control A register. Figure 9. Control A register. You can access the ControlA register using uint32_t reg in the following way: sercomp->spi.ctrla.reg = <value to be assigned>; Here sercomp is the pointer variable to the Sercom structure and we are implementing the SPI protocol. Page 10 of 14

13 The bitwise description of the registers is also provided in the header file. For example, the Control A register is described as below: #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< (SERCOM_SPI_CTRLA) Software Reset */ #define SERCOM_SPI_CTRLA_SWRST (0x1u << SERCOM_SPI_CTRLA_SWRST_Pos) #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< (SERCOM_SPI_CTRLA) Enable */ #define SERCOM_SPI_CTRLA_ENABLE (0x1u << SERCOM_SPI_CTRLA_ENABLE_Pos) #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< (SERCOM_SPI_CTRLA) Operating Mode */ #define SERCOM_SPI_CTRLA_MODE_Msk (0x7u << SERCOM_SPI_CTRLA_MODE_Pos) #define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))) #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (0x0u << 2) /**< (SERCOM_SPI_CTRLA) USART mode with external clock */ #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (0x1u << 2) /**< (SERCOM_SPI_CTRLA) USART mode with internal clock */ #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (0x2u << 2) /**< (SERCOM_SPI_CTRLA) SPI mode with external clock */ #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (0x3u << 2) /**< (SERCOM_SPI_CTRLA) SPI mode with internal clock */ #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (0x4u << 2) /**< (SERCOM_SPI_CTRLA) I2C mode with external clock */ #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (0x5u << 2) /**< (SERCOM_SPI_CTRLA) I2C mode with internal clock */ #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< (SERCOM_SPI_CTRLA) Run during Standby */ #define SERCOM_SPI_CTRLA_RUNSTDBY (0x1u << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< (SERCOM_SPI_CTRLA) Data Out Pinout */ #define SERCOM_SPI_CTRLA_DOPO (0x1u << SERCOM_SPI_CTRLA_DOPO_Pos) #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< (SERCOM_SPI_CTRLA) Data In Pinout */ #define SERCOM_SPI_CTRLA_DIPO_Msk (0x3u << SERCOM_SPI_CTRLA_DIPO_Pos) #define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))) #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< (SERCOM_SPI_CTRLA) Frame Format */ #define SERCOM_SPI_CTRLA_FORM_Msk (0xFu << SERCOM_SPI_CTRLA_FORM_Pos) #define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))) #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< (SERCOM_SPI_CTRLA) Clock Phase */ #define SERCOM_SPI_CTRLA_CPHA (0x1u << SERCOM_SPI_CTRLA_CPHA_Pos) #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< (SERCOM_SPI_CTRLA) Clock Polarity */ #define SERCOM_SPI_CTRLA_CPOL (0x1u << SERCOM_SPI_CTRLA_CPOL_Pos) #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< (SERCOM_SPI_CTRLA) Data Order */ #define SERCOM_SPI_CTRLA_DORD (0x1u << SERCOM_SPI_CTRLA_DORD_Pos) #define SERCOM_SPI_CTRLA_MASK 0x7F31009Fu /**< (SERCOM_SPI_CTRLA) MASK Register */ To summarize the component_sercom.h completely defines the SERCOM related registers. 4.3 Configuring SERCOM to operate as SPI Master Do you know how to configure the I/O lines to perform SPI peripheral function based on exercise from the previous sections? Can you write the C function to achieve this on your own? Have you decided which registers you will use to configure SERCOM to operate in SPI mode? Page 11 of 14

14 As already mentioned, you have already been provided with the code to enable the clocks required by SERCOM Accessing the SERCOM Registers for SPI The Sercom structure defines all the communication protocols supported. One of its members, SercomSpi, defines all the structures for SPI protocol configuration. typedef struct { /* SPI Mode */ IO SERCOM_SPI_CTRLA_Type CTRLA; /**< Offset: 0x00 (R/W 32) SPI Control Register A */ IO SERCOM_SPI_CTRLB_Type CTRLB; /**< Offset: 0x04 (R/W 32) SPI Control Register B */ IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< Offset: 0x08 (R/W 8) SPI Debug Register */ RoReg8 Reserved1[0x1]; IO SERCOM_SPI_BAUD_Type BAUD; /**< Offset: 0x0A (R/W 8) SPI Baud Rate Register */ RoReg8 Reserved2[0x1]; IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< Offset: 0x0C (R/W 8) SPI Interrupt Enable Clear Register */ IO SERCOM_SPI_INTENSET_Type INTENSET; /**< Offset: 0x0D (R/W 8) SPI Interrupt Enable Set Register */ IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< Offset: 0x0E (R/W 8) SPI Interrupt Flag Status and Clear Register */ RoReg8 Reserved3[0x1]; IO SERCOM_SPI_STATUS_Type STATUS; /**< Offset: 0x10 (R/W 16) SPI Status Register */ RoReg8 Reserved4[0x2]; IO SERCOM_SPI_ADDR_Type ADDR; /**< Offset: 0x14 (R/W 32) SPI Address Register */ IO SERCOM_SPI_DATA_Type DATA; /**< Offset: 0x18 (R/W 16) SPI Data Register */ } SercomSpi; We could easily access these registers the following way: Sercom *sercomp = SERCOM0; Here SERCOM0 is the base address definition: #define SERCOM0 (0x U) /**< (SERCOM0) APB Base Address */ How will you use the structure variable sercomp to configure the SERCOM in SPI mode as discussed in Section 4.1 of this section? 4.4 Transmitting data as SPI Master Now that you are familiar with the SPI related registers, you probably already know that writing something to the Data register will be transmitted via the transmit data buffer. This register should be written only when the Data Register Empty Interrupt Flag bit in the Interrupt Flag Status and Clear register (INTFLAG.DREIF) is set. Figure 10 below shows a scope capture of SPI data transmission by a SPI Master device. The data transmitted is 0x02. Page 12 of 14

15 Figure 10. SPI Master data transmission Page 13 of 14

16 5. Conclusion In this section we have focused on SPI, one of the communication protocols supported by SERCOM on the SAMD20. Data is transmitted and received synchronously in a master-slave configuration. We are now familiar with the following: 1. The fundamental process of SPI data protocol. 2. The various modes of SPI data transmission. 3. SERCOM transmit and receive in SPI mode. 4. Port configuration for SERCOM. 5. How to transfer a byte in master mode. 6. SERCOM system level header files. Page 14 of 14

17 Atmel Corporation 1600 Technology Drive San Jose, CA USA Tel: (+1)(408) Fax: (+1)(408) Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) Fax: (+852) Atmel Munich GmbH Business Campus Parkring 4 D Garching b. Munich GERMANY Tel: (+49) Fax: (+49) Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg Osaki, Shinagawa-ku Tokyo JAPAN Tel: (+81)(3) Fax: (+81)(3) Atmel Corporation. All rights reserved. / Rev.: 04/12/2013 Atmel, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.