Software-Controlled Multithreading Using Informing Memory Operations

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1 Software-Controlled Multithreading Using Informing Memory Operations Todd C. Mowry Computer Science Department University Sherwyn R. Ramkissoon Department of Electrical & Computer Engineering University of HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon Copyright, 1996 Dale Carnegie & Associates, Inc.

2 The Latency Problem in Hardware DSMs (Simulated performance on a machine similar to a 2-processor SGI Origin.) Remote memory accesses and communication are fairly expensive hundreds of cycles on state-of-the-art machines expected to get even worse in the future 5 of 7 applications waste > 50% of their time on memory & sync stalls One potential solution: multithreading HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

3 Multithreading Basic Idea: overlap an expensive miss with work from another parallel thread Several Hardware-Based Variations Exist: fine-grained switch between threads on every cycle (e.g., HEP, TERA) coarse-grained switch only upon cache misses (e.g., MIT Alewife) simultaneous (aka SMT) run threads concurrently, exploiting register renaming HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

4 Tradeoffs with Existing Multithreading Techniques The Good News: multithreaded workloads enjoy higher throughputs The Bad News: single-threaded performance gets worse! Why? Because larger register files (and added complexity) are likely to either increase cycle times or lengthen the pipeline e.g, it may take an extra cycle to access the register file, etc. A Potential Concern: programs without sufficient thread-level parallelism may run slower (rather than faster) on multithreaded processors HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

5 Our Approach: Software-Controlled Multithreading Goals of Our Design: target the expensive remote latencies in multiprocessors (unlike SMT, we are NOT targeting the wide-issue problem) no degradation of single-thread performance minimal hardware support that is unique to multithreading Our Approach: use software to do most of the work pay multithreading overhead only when it buys you something a variation on coarse-grained (i.e. switch-upon-miss) multithreading Research Question: can such a design achieve positive performance gains? HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

6 Overview Software-Controlled Multithreading how it works implementation issues Performance Results Conclusions HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

7 Functionality Needed for Multithreading 1. The ability to switch between threads software can easily do this by saving & restoring machine state 2. Knowing when a thread switch should occur software must be able to observe & react quickly to cache misses this functionality has been missing in the past Cache Hit Cache Miss Time Load Load Busy Stalled Indistinguishable to software! one solution: use informing memory operations HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

8 Informing Memory Operations Conceptually, an informing memory operation consists of: memory operation + conditional branch-&-link if miss Cache Hit Cache Miss Inf-Load Inf-Load Time React to Miss Miss handler code is executed underneath the cache miss Has many potential uses [ISCA 96, ACM TOCS 98]: e.g., better performance monitoring & feedback tools, improving software prefetching, faster software-based cache coherence, etc. HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

9 Further Details on Informing Memory Operations Version Based on Fast User-Level Traps: [ISCA 96, ACM TOCS 98] two new user-visible registers are introduced: Miss Handler Address Register (MHAR) Miss Handler Return Register (MHRR) trap mechanism is extremely lightweight only a link register (MHRR) is saved; no OS code is invoked overhead is similar to a conditional branch-&-link 0x20: MHAR = 0x x44: Load r1,4(r2) Hit: proceed as normal 0x48:... Miss: jump to MHAR (0x80); set MHRR to 0x48 0x80: # miss handler... 0x98: Jump MHRR return to original control flow HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

10 Using Inf. Memory Ops to Implement Multithreading Rather than returning directly to the original thread, the miss handler: saves the state of the current thread (including the MHRR) restores the state of another parallel thread (& jumps to it) This thread switch occurs during the original cache miss Original Case With Software-Controlled Multithreading Load A Load A Switch Threads Thread 1 Thread 2 Time Fetch A Fetch A Load B Stalled Miss Handler Fetch B Control Flow HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

11 Additional Hardware Support 1. Load that triggers miss handler is converted into a prefetch otherwise the reorder buffer will fill up waiting for it to graduate its destination register is freed, breaking any register dependences fairly straightforward to implement: can be specified as an option when setting the MHAR all information needed to convert to prefetch is already in MSHR 2. Miss handler can test whether reference also missed in secondary cache to avoid switching threads upon primary-to-secondary misses this option was discussed in earlier papers [ISCA 96, ACM TOCS 98] Note: these changes only affect actions taken upon miss handler invocation not likely to slow down the critical path of normal execution HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

12 Design of the Miss Handler A single miss handler is used, which does the following: subtracts 4 bytes from the MHRR (i.e. the link register) to re-execute the load that missed when thread is restarted tests whether the reference suffered a secondary cache miss if not, then return immediately disables informing memory traps while in the miss handler i.e. sets MHAR = 0 saves current thread; restores and resumes another thread We implemented fully functional code for the MIPS instruction set Contains a total of 104 instructions, including 94 loads/stores in our experiments, the average switch time is roughly 55 cycles HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

13 Overview Software-Controlled Multithreading Performance Results baseline scheme reducing overheads through register partitioning comparison with hardware-controlled multithreading Conclusions HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

14 Experimental Framework Benchmarks: 7 applications from the SPLASH-2 suite Architecture: system model based on the SGI Origin 32KB/2MB 2-way set-associative caches remote miss latencies: cycles (plus contention) MIPS R10000-like processors (augmented to have 2 memory units) Multithreading Configuration: up to 2 threads per processor (we observed that more than 2 threads was not useful) Simulator: detailed, cycle-by-cycle simulations, including contention, etc. models full details of executing the real miss handler code HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

15 Performance of Software-Controlled Multithreading 4 of 7 applications speed up by 10%-14%; the other 3 by 1%-2% memory stall time decreases by over 35% in most cases synch overhead dominated by load imbalance, so little benefit thread switching overhead is significant in several cases primarily due to saving & restoring registers (i.e. TS Regs ) HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

16 Register Partitioning Basic Idea: statically assign each thread a disjoint subset of the user registers can avoid saving/restoring these registers upon thread switches Implementation within MIPS ISA: the following special-purpose registers cannot be partitioned: at, v0-v1, a0-a3, gp, sp, fp, ra, & fcr31 the remaining 21 GP and 32 FP registers can be partitioned used the -ffixed flag within gcc to manipulate register allocation Impact on Miss Handler Code: reduced to 34 instructions (vs. 104), with 24 loads/stores (vs. 94) switching latency reduced by 2.5X, to as little as 18 cycles HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

17 Performance Impact of Register Partitioning Results are mixed: FFT & RADIX enjoy significant performance gains several other cases get worse due to excessive register spilling Potential solution: (B = baseline scheme; R = with register partitioning) compiler could automatically suppress register partitioning if it detects that spilling will be a problem HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

18 Software vs. Hardware Control Goal: quantify the overheads of software control more precisely (execution time breakdowns tricky for an O-o-O pipeline) Experiment: compare our scheme with a similar hardware-controlled approach i.e. hardware-controlled coarse-grained multithreading Hardware-control is strictly faster: (on multithreaded workloads) switch triggered directly by L2 cache miss (vs. testing L2 hit/miss status inside miss handler) new thread starts executing immediately (vs. executing thread switching code) How much slower is software- vs. hardware-controlled multithreading? HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

19 Performance of Software vs. Hardware Control (O = original (i.e.1 thread/proc); S = software-control; H = hardware-control) Software gets 50% of the gain of hardware-control in most cases average speedups: 8% (SW-control) vs. 17% (HW-control) thread switching code is partially overlapped with fetching and executing the next thread (due to ILP) SMT would be even faster, but would require even more HW support HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

20 Conclusions Software-controlled multithreading can improve performance 4 of 7 applications speed up by 10% or more (one by 14%) Register partitioning can help it improve performance further e.g., increases the speedup of FFT to 23% however, care must be taken to avoid register spilling Hardware cost is dramatically lower than other existing schemes very little support required beyond informing memory operations which have many other uses is not expected to degrade single-thread performance at all Should become even more attractive in the future as instruction overhead becomes less expensive relative to memory latency Another compelling reason to support informing memory operations! HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

21 Avoiding Deadlock Cache Conflicts between Concurrent Threads: Deadlock Scenario: thread 1 misses on location A which maps to cache entry X thread 2 misses on location B which also maps to entry X thus displacing A from the cache thread 1 restarts; suffers miss on A; displaces B, etc. Solution: switch threads at most once for each reference Spin-Waiting Synchronization: Deadlock Scenario: current thread is spin-waiting for a lock lock is held by a swapped-out thread on the same processor Solution: switch threads as part of the spin-waiting loop HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

22 Additional Baseline SWMT Statistics Avg. L2 Cache Miss Latency L (cycles) Average Run Length R (cycles) Average Thread Switch Time C (cycles) Benchmark CHOLESKY FFT LU-CONT LU-NCONT OCEAN-CONT OCEAN-NCONT RADIX Highlights: avg. L2 miss latency >> avg. thread switch time large switch time for RADIX & CHOLESKY thread state displaced in cache Since L < R + C, one additional thread sufficient to tolerate latency 2 threads/processor is beneficial, more is undesirable HPCA-6: Software-Controlled Multithreading Mowry & Ramkissoon

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