PART I: Adding Instructions to the Datapath. (2 nd Edition):

Transcription

1 EE57 Instrctor: G. Pvvada ===================================================================== Homework #5b De: check on the blackboard ===================================================================== All stdents need to have to (a) sec. 5. from the st edition as well as either (b.) sec. 5.5 of the rd edition or (b.) sec. 5. of the nd edition. We cover mlticycle implementation from the first edition as well as the third edition. The second and the third editions are essentially the same. Lab # and qestions at the end of lab # are based on the st edition. However this homework (HW#5b) is based on the nd / rd edition. In the nd / rd edition, the athors have introdced new temporary s A, B, ot, DR ( Data Register). They have removed the TAR- GET temporary of the st edition as the new ot served the prpose of the TARGET. Becase of the presence of the new temporary s, nlike in st edition design, we do NOT have to KEEP PERFORING the same operation over several clocks. For eample, the comptes the memory address in state and drops it off in the ot. In states and 5 (dring memory ), the does NOT need to keep compting the memory address as it was "safely" held in the ot. Yo notice that the control signals of state are NOT repeated in states and 5 of fig. 5.8 in rd edition (of fig. 5. in nd edition). ===================================================================== Eercises for this homework are provided from both nd edition and rd edition of tetbook. The qestions are reprodced below. Please do eercise 5.5 from the nd edition and eercises 5., 5., 5., 5.5, 5.7 and 5.8 from rd edition. Please se photocopies of the tetbook figres to answer design qestions by modifying the figres as necessary. Yo can either photocopy the necessary figres or download the figres of second edition from the web-site The two figres needed from the nd edition (figres 5. and 5.) are posted at the above location as (lti_cycle_dp.pdf and lti_cycle_sd.pdf ). They are password protected and the password is given on the BB). The figres are also given at the end of this homework. The corresponding figres in the rd edition are figres 5.8 and 5.7 (COD_rd_Figre_5.8.jpg and COD_rd_Figre_5.7.jpg posted above). PART I: Adding s to the Datapath ( nd Edition): 5.5 [5] <ß5.> We wish to add the instrction addi (add immediate) to the mlticycle path described in this chapter. Add any necessary paths and control signals to the mlticycle path of Figre 5. on page 8 in nd edition (fig. 5.8 in rd edition) and show the necessary modifications to the finite state machine of Figre 5. on page 96 in nd edition (fig. 5.8 on page 9 in rd edition). Yo may find it helpfl to eamine the eection steps shown on pages 85 throgh 88 in nd edition (pages 5 throgh 9 in rd edition) and consider the steps that ee57_hw5b.fm /8/

2 will need to be performed to eecte the new instrction. Yo can photocopy eisting figres to make it easier to show yor modifications. Try to find a soltion that minimizes the nmber of clock cycles reqired for the new instrction. Please eplicitly state how many cycles it takes to eecte the new instrction on yor modified path and finite state machine. ( rd Edition): 5. [5] <ß5.5> This qestion is similar to previos eercise (Eercise 5.5 of the nd edition) ecept that we wish to add the instrction jal (jmp and link), which is described in Chapter. 5. [5] <ß5.5> This qestion is similar to Eercise 5. ecept that we wish to add a new instrction, wai (where am I), which pts the instrction s location (the vale of the PC when the instrction was fetched) into a specified by the rt field of the machine langage instrction. Assme that the path has not changed and that, as sal, the clock cycle is too short to allow an operation and a file in a single clock cycle if one of them is dependent on the reslts of the other. 5. [5] <ß5.5> This qestion is similar to Eercise 5. ecept that we wish to add a new instrction, jm (jmp memory). Its instrction format is similar to that of load word ecept that the rt field is not sed becase the loaded from memory is pt in the PC instead of the target. 5.5 [] <ß5.5> This qestion is similar to Eercise 5. ecept that we wish to add spport for for-operand arithmetic instrctions sch as add, which adds three nmbers together instead of two: add $t5, $t6, $t7, $t8 # $t5 = $t6 + $t7 + $t8 Assme that the instrction set is modified by introdcing a new instrction format similar to the R-format ecept that bits [-] are sed to specify the additional (we still se rs, rt, and rd) and of corse a new opcode is sed. Yor soltion shold not rely on adding additional read ports to the file, nor shold a new be sed. PART II: (rd Edition): PART II CANCELLED 5.7 [5] <ß5.5> Describe the effect that a single stck-at- falt (i.e., regardless of what it shold be, the signal is always ) wold have on the mltipleors in the mltiple-cycle path in Figre 5.8 on page. Which instrctions, if any, wold still work? Consider each of the following falts separately: RegDst =, emtoreg =, IorD =, SrcA =. 5.8 [5] <ß5.5> This eercise is similar to Eercise 5.7, bt this time consider stck-at- falts (the signal is always ). ee57_hw5b.fm /8/

3 address comptation SrcA = SrcB = Op = Start fetch em SrcA = IorD = IR SrcB = Op = PCSorce = 6 (Op = 'LW') or (Op = 'SW') Eection SrcA = SrcB = Op= 8 (Op = R-type) Branch SrcA = SrcB = Op = Cond PCSorce = decode/ fetch (Op = 'BEQ') 9 SrcA = SrcB = Op = (Op = 'J') Jmp PCSorce = (Op = 'LW') (Op = 'SW') 5 7 R-type em IorD = em IorD = RegDst = emtoreg = -back step RegDst= emtoreg=

4 PC Address emdata Cond IorD Otpts em em Control emtoreg IR Op [5 ] [5 ] [-6] [5 ] [ 6] [5 ] [5 ] [5 ] PCSorce Op SrcB SrcA RegDst Registers 6 Sign etend [5 ] A B 6 8 PC [-8] Zero reslt control Jmp address [-] Ot

5 address comptation SrcA = SrcB = Op = Start fetch em SrcA = IorD = IR SrcB = Op = PCSorce = 6 (Op = 'LW') or (Op = 'SW') Eection SrcA = SrcB = Op= 8 (Op = R-type) Branch SrcA = SrcB = Op = Cond PCSorce = decode/ fetch (Op = 'BEQ') 9 SrcA = SrcB = Op = (Op = 'J') Jmp PCSorce = (Op = 'LW') (Op = 'SW') 5 7 R-type em IorD = em IorD = RegDst = emtoreg = -back step RegDst= emtoreg=

6 address comptation SrcA = SrcB = Op = Start fetch em SrcA = IorD = IR SrcB = Op = PCSorce = 6 (Op = 'LW') or (Op = 'SW') Eection SrcA = SrcB = Op= 8 (Op = R-type) Branch SrcA = SrcB = Op = Cond PCSorce = decode/ fetch (Op = 'BEQ') 9 SrcA = SrcB = Op = (Op = 'J') Jmp PCSorce = (Op = 'LW') (Op = 'SW') 5 7 R-type em IorD = em IorD = RegDst = emtoreg = -back step RegDst= emtoreg=

7 PC Address emdata Cond IorD Otpts em em Control emtoreg IR Op [5 ] [5 ] [-6] [5 ] [ 6] [5 ] [5 ] [5 ] PCSorce Op SrcB SrcA RegDst Registers 6 Sign etend [5 ] A B 6 8 PC [-8] Zero reslt control Jmp address [-] Ot

8 address comptation SrcA = SrcB = Op = Start fetch em SrcA = IorD = IR SrcB = Op = PCSorce = 6 (Op = 'LW') or (Op = 'SW') Eection SrcA = SrcB = Op= 8 (Op = R-type) Branch SrcA = SrcB = Op = Cond PCSorce = decode/ fetch (Op = 'BEQ') 9 SrcA = SrcB = Op = (Op = 'J') Jmp PCSorce = (Op = 'LW') (Op = 'SW') 5 7 R-type em IorD = em IorD = RegDst = emtoreg = -back step RegDst= emtoreg=

9 PC Address emdata Cond IorD Otpts em em Control emtoreg IR Op [5 ] [5 ] [-6] [5 ] [ 6] [5 ] [5 ] [5 ] PCSorce Op SrcB SrcA RegDst Registers 6 Sign etend [5 ] A B 6 8 PC [-8] Zero reslt control Jmp address [-] Ot

10 address comptation SrcA = SrcB = Op = Start fetch em SrcA = IorD = IR SrcB = Op = PCSorce = 6 (Op = 'LW') or (Op = 'SW') Eection SrcA = SrcB = Op= 8 (Op = R-type) Branch SrcA = SrcB = Op = Cond PCSorce = decode/ fetch (Op = 'BEQ') 9 SrcA = SrcB = Op = (Op = 'J') Jmp PCSorce = (Op = 'LW') (Op = 'SW') 5 7 R-type em IorD = em IorD = RegDst = emtoreg = -back step RegDst= emtoreg=