Digital Systems Testing

Transcription

1 Digital Systems Testing Verilog HDL for Design and Test Moslem Amiri, Václav Přenosil Embedded Systems Laboratory Faculty of Informatics, Masaryk University Brno, Czech Republic Fall, 2014

2 Motivations of Using HDLs for Developing Test Methods Tools and methodologies design and test engineers use are different A gap between design and test tools and methods This gap results in inconsistencies in process of design and test E.g., designs that are hard to test, or time needed to convert design to format compatible for testing On the other hand, incorporating test in design must start from beginning of design process Desirable to bring testing in hands of designers Requires that testing is applied at level and with language of designers This way, designers can combine design and test phases Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

3 Motivations of Using HDLs for Developing Test Methods Advantages of using RT-level HDLs in test and DFT Helps advancing test methods to RT level Alleviates the need for use of software languages and reformatting designs for evaluation and application of test techniques Actual test data can be applied to post-manufacturing model of a component, while keeping other component models at design level, and simulating in the same environment and keeping the same testbench This allows reuse of design test data, and migration of testbenches from design stage to post-manufacturing test In a mixed-level design, possible to test a single component described at gate level while leaving others in RTL or even at system level Limitations of HDL simulation tools when developing test methods in an HDL environment Overhead that test methods put on simulation speed Inability to describe complex data structures PLI overcomes HDL limitations It provides a library of C language functions that can directly access data within an instantiated Verilog data structure Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

4 Using Verilog for Simulation Testbench written in Verilog Response analysis/display Test data generation Circuit Under Test in Verilog Hardware Description Verilog Simulator Figure 1: Simulation in Verilog. Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

5 Using Verilog for Simulation Module Basic structure of Verilog in which hardware components or testbenches are described Fig. 1 Shows a simulation model that consists of a design with a Verilog testbench Verilog constructs are shown by dotted lines They form inside of a module Constructs of the Verilog model being tested describe its hardware Constructs used in a testbench provide appropriate input data or apply data stored in a text file to the module being tested, and analyze or display its outputs Simulation output is generated in the form of waveform or data files Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

6 Using Verilog for Synthesis After a design passes functional validations, it is synthesized into a netlist of components of a target library Verilog constructs used in description of a design for its verification or those for timing checks and timing specifications are not synthesizable Verified Circuit in Verilog Hardware Description Target Library Verilog Synthesis A netlist of gates and flip-flops Timing files and other hardware details Figure 2: Synthesis of a Verilog design. Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

7 Using Verilog for Synthesis Testbench written in Verilog Response analysis/display Test data generation Netlist of gates and flip-flops in Verilog SET Q S R CLR Q SET Q S R CLR Q SET S Q R CLR Q Verilog Simulator Timing files and other hardware details Figure 3: Postsynthesis simulation in Verilog. Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

8 Using Verilog for Synthesis Postsynthesis simulation in Fig. 3 The netlist provided by synthesis tool, that uses Verilog for description of the netlist components, is used here The same testbench prepared for pre-synthesis simulation can be used with this gate-level description This simulation uses timing information generated by the synthesis tool and yields simulation results with detailed timing Since the same testbench of high-level design is applied to gate-level description, resulted waveform or printed data must be the same This can be seen when comparing Fig. 1 with Fig. 3 The only difference is that post-synthesis simulation includes timing details Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

9 Good Circuit Analysis An important tool in testing is one that generates good circuit responses from a circuit s golden model This response is to be compared with responses from faulty circuits By applying testbench data to golden model, we record good behavior of circuit for future use Golden signatures can also be created this way A signature is result of an accumulative compression on all outputs of golden model Later, when checking if a circuit is faulty or not, the same input data and the same signature collection algorithm must be applied to design under test By comparing obtained signature with recorded golden signature, presence or absence of faults can be verified Another application of HDL simulation is signature generation for various test sets or for different test procedures Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

10 Good Circuit Analysis Testbench written in Verilog/PLI Response analysis/display Test data generation Circuit Under Test in Verilog High-Level Hardware Description Verilog Simulator Good Behavior Report Golden Signatures Signature Generation Figure 4: Good circuit analysis using Verilog. Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

11 Fault List Compilation and Testability Analysis Fault list compilation is one of the basic utilities needed to perform test applications For this purpose, the design described at gate level is used Having fault models available for gate models used in gate-level description, possible faults for entire design can be generated By exploring the netlist, fault list of design under test is generated and recorded in a text file To reduce test time, fault collapsing, which is implementable in HDL environment, is performed Methods used for fault compilations can also be used for applications which need measurements to estimate how testable their internal nodes are Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

12 Fault List Compilation and Testability Analysis Testbench written in Verilog/PLI Netlist of gates and flip-flops in Verilog Q SET Verilog Simulator Fault List Generation Fault Collapsing Testability Analysis SET CLR Q S Q R SET CLR Q S Q R S Q CLR R Figure 5: Fault list compilation and testability measurement using Verilog. Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

13 Fault Simulation Fault list generated by an HDL environment can be used in an HDL simulation environment for fault simulation of CUT There are Verilog PLI functions developed for producing fault models of a CUT for purpose of fault simulation PLI functions inject faults in good circuit model to create a faulty model of CUT If test data, fault list, and a mechanism for fault injection are available, fault simulation can be implemented in an HDL testbench Testbench needs to instantiate golden and faultable models of circuit, and inject faults and remove them for creating various faulty models Applications of fault simulation Calculation of fault coverage An HDL simulation tool, with a testbench that instantiates a CUT, can calculate fault coverage for a test vector or a test set of CUT Generation of a faulty signature for every one of CUT s faults A database containing tests, faults and their faulty signatures is called a fault dictionary When dealing with an actual faulty CUT, by collecting its signature and comparing resulted signature with ones saved in fault dictionary, CUT s fault can be identified and located Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

14 Fault Simulation Testbench written in Verilog Test Control Test data generation Netlist of gates and flip-flops in Verilog Verilog Simulator Fault Simulation Results Fault Dictionary Fault Coverage Faulty Signature Generation Fault List Test Data Figure 6: Fault simulation using Verilog. Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

15 Test Generation Another application of Verilog PLI for test applications is test generation Netlist is instantiated in testbench Environment injects a fault, generates some random or pseudo random test data, and checks if the test vector detects the injected fault We can find the number of undetected faults that a test vector detects Result is a collection of test vectors (test set) that detect a good number of circuit faults Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

16 Test Generation Testbench written in Verilog/PLI Test Control Netlist of gates and flip-flops in Verilog Verilog Simulator Test Data Generation Test Data Refinement Test Data Evaluation Fault Injection in PLI Fault List Figure 7: Test generation using Verilog. Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

17 Testability Hardware Design Efficient design of hardware that makes a design testable is possible in an HDL environment Using testability measurements and other information provided by simulating a design, we can decide on type and place of testability hardware By applying test generation and fault simulation applications, a proper test set can be found for the new circuit Various testability factors of the new circuit, such as new testability measurements, fault coverage, test time, and even power consumption estimation during test can be obtained Changing configuration of testability hardware is also possible Important parameters of DFT, such as place for inserting test points, length and number of scan chains, and the number of clocks in BIST circuit, can be changed until the best possible configuration is obtained Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

18 Testability Hardware Design Testbench written in Verilog/PLI Test data generation Circuit Under Test in Verilog Verilog Simulator Testability Hardware Evaluation BIST Configuration High-Level Hardware Description Testability Hardware Figure 8: Testability hardware design using Verilog. Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19

19 References Zainalabedin Navabi, Digital System Test and Testable Design: Using HDL Models and Architectures, Springer, Moslem Amiri, Václav Přenosil Digital Systems Testing Fall, / 19