Parallel versus serial execution

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1 Parallel versus serial execution F assign statements are implicitly parallel Ì = means continuous assignment Ì Example assign E = A & D; assign A = B & C; Ì A and E change if B changes F always blocks execute in parallel Ì clock) B C A D E F Procedural block internals not necessarily parallel Ì = is a blocking assignment (sequential) Ì <= is a nonblocking assignment (parallel) Ì Examples of procedures: always, function, etc.

2 @ inside always blocks F can halt execution Ì Says wait for a trigger Ì Can use for simple state machines Á When next state doesn t dep on input clk) begin state = 4 clk) state = 4 clk) state = 4 clk) state = 4 b; 2

3 Assignments F Be careful with always assignments or x) begin if (c) begin value = x; y = value; or x) begin value = x; if (c) begin value = ; y = value; or x) begin if (c) value = ; else if (x) value = ; F Which statements generate a latch? or b) f = a & b & c; 3

4 Assignments F Blocking versus non-blocking reg B, C, D; clk) begin B = A; C = B; D = C; reg B, C, D; clk) begin B <= A; C <= B; D <= C; 4

5 Finite state machines F FSM model Mealy outputs inputs combinational logic next state Moore outputs current state F Implementing FSMs Ì Combinational logic: Use function or always Ì Registers: always triggered off posedge clock 5

6 Example: Moore machine F Reduce s Ì Change the first to zero [] module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter zero =, one =, twos = 2; // states reg out; reg [:] state; // state register reg [:] next_state; // always block needs reg one [] // Implement the state register clk) if (reset) state = zero; //can put in next state logic else state = next_state; twos [] Continued next page 6

7 Moore reduce s (cont d) or state) // combinational logic case (state) zero: begin // last input was a zero out = ; if (in) next_state = one; else next_state = zero; one: begin // we've seen one out = ; if (in) next_state = twos; else next_state = zero; twos: begin // we've seen at least 2 ones out = ; if (in) next_state = twos; else next_state = zero; default: begin // in case we reach a bad state next_state = zero; out = ; case module must include all signals that are input to state and output equations zero [] one [] twos [] 7

8 Another way module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter zero =, one =, twos = 2; // states reg [:] state; // state register assign out = reduce_output(state); zero [] clk) if (reset) state = zero; else state = next_state(in, state); one [] function reduce_output; input [:] state; case (state) zero: reduce_output = ; one: reduce_output = ; twos: reduce_output = ; default: reduce_output = ; case function Continued next page twos [] 8

9 Another way (con t) function [:] next_state; input in; input [:] state; case (state) zero: if (in) next_state = one; else next_state = zero; one: if (in) next_state = twos; else next_state = zero; twos: if (in) next_state = twos; else next_state = zero; default: next_state = zero; case function module zero [] one [] twos [] 9

10 Example: Mealy machine reduce s module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter zero =, one = ; // states reg state; // state register assign out = reduce_output(in, state); / zero / / clk) if (reset) state = zero; else state = next_state(in, state); one / function reduce_output; input in, state; case (state) zero: reduce_output = ; one: if (~in) reduce_output = ; else reduce_output = ; case function Continued next page

11 Mealy machine reduce s (con t) function next_state; input in, state; case (state) zero: if (~in) next_state = zero; else next_state = one; one: if (~in) next_state = zero; else next_state = one; case function module / zero one / / /

12 Mealy machine reduce s again... F Notice the next state is the input... module reduce (clk, reset, in, out); input clk, reset, in; output out; reg state; // state register assign out = state & in; / zero one / / clk) if (reset) state = ; else state = in; module / 2

13 If you use always blocks... F Use at least 2 of them Ì Avoid embedding output logic into state block Á Use an output always Á Use a state always F Not an issue with Mealy machines Ì Must use 2 always with Mealy Á Because output can change at any time 3

14 -always Moore FSM (not recommed!) F Reduce s again module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg [:] state; // state register parameter zero =, one =, twos = 2; zero [] one [] twos [] Continued next page 4

15 clk) case (state) zero: begin out = ; if (in) state = one; else state = zero; one: if (in) begin state = twos; out = ; else begin state = zero; out = ; twos: if (in) begin state = twos; out = ; else begin state = zero; out = ; default: begin state = zero; out = ; case module All outputs are registered Confusing: the output logic is buried in the state logic and compiler might give you an extra register... 5

16 Synchronous Mealy FSMs F Register the output clk) begin state <= f(state, inputs); Mealy_out <= f(state, inputs); 6

17 Parameters customize module instantiation F Can tweak modules for particular applications Ì Example: Variable bit widths module comparator (a, b, c); parameter width = 8; input [width-:] a, b; output c; assign c = (a == b); module... comparator #(32) c32(w, x, p);... comparator #(4) c4(y, z, q);... 7

18 Parameters can choose logic functionality F Example: Choose adder or subtractor define ADD define SUB module addsub (a, b, c); parameter width = 8; parameter op = `ADD; input [width-:] a, b; output [width-:] c; assign c = (op == `ADD)? (a + b) : (a - b); module... addsub #(32,`SUB) c32(x, y, z);... 8

19 Parameters cannot generate logic F Can evaluate constant-valued expressions F Cannot evaluate nonconstant-valued expressions This code won t work module add_or_sub (a, b, op, c); constant-valued parameter width = 8; parameter add = b; input [width-:] a, b; input op; non-constant-valued output [width-:] c; assign c = (op == add)? (a + b) : (a - b); module 9

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