HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b;

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b;"

Transcription

1 HW2 solutions 3.10 Pseuodinstructions What is accomplished Minimum sequence of Mips Move $t5, $t3 $t5=$t3 Add $t5, $t3, $0 Clear $t5 $t5=0 Xor $t5, $t5, $t5 Li $t5, small $t5=small Addi $t5, $0, small Li $t5, big $t5=big lui $t5, big[31:16] Ori $t5, $t5, big[15:0] Lw $t5, big($t3) $t5=mem[$t3+big] Lui $t5, big[31:26] Ori $t5, $t0, big[15:0] Add $t3, $t3, $t5 Lw $t5, 0($t3) Addi $t5, $t3, big $t5=$t3+big Lui $t5, big[31:16] Ori $t5, big[15:0] Addi $t5, $t5, $t3 Beq $t5, small, L If $t5=small, branch to L Addi $at, $0, small Beq $t5, $at, L Beq $t5, big, L If $t5=big, branch to L Lui $at, big[31:16] Ori $at, big[15:0] Beq $at, $t5, L Ble $t5, $t3, L If $t5<=$t3, branch to L Slt $at, $t3, $t5 Beq $at, $0, L Bge $t5, $t3, L If $t5>=$t3, branch to L Slt $at, $t5, $3 Beq $at, $0, L Bgt $t5, $t3, L If $t5>$t3, branch to L Slt $at, $t3, $t5 Bne $at, $0 L 3.25 You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b; 3.30 sbn neg_a, neg_a,.+1 # neg_a = 0; sbn neg_a, a,.+1 # neg_a = -a; sbn c, c,.+1 # c = 0; loop: sbn b, one,.+1 # do { b = b 1; sbn c, neg_a,.+1 # c = c + a; sbn temp, temp,.+1 # temp = 0; sbn temp, b, loop # } while (b > 0);

2 Note (1) This solution does not work if b = 0, because the problem description said to assume that a and b are greater than 0. Perfectionist students are likely to write solutions that do work for b = 0 though, so their answers would be an instruction or too long add $t2, $t3, $t4 slt $t2, $t2, $t You need only alter the full adder for the MSB such that the Set output is the value of the full adder output XORed with the Overflow 4.24 (a * 2^32 + b) * (c * 2^32 + d) = (a * c * 2^64 + a * d * 2^32 + b * c * 2^32 + b * d multu $t5, $t7 # b * d mflo $t3 # product[31:0] = (b * d)[31:0] mfhi $t2 # product[63:32] = (b * d)[64:32] multu $t4, $t7 # a * d mflo $t8 # $t8 = (a * d)[31:0] mfhi $t1 # product[95:64] = (a * d)[63:32] addu $t2, $t2, $t8 # product[63:32] += (a * d)[31:0] sltu $t8, $t2, $t8 # $t8 = carry of 63:32 in last op

3 addu $t1, $t1, $t8 # product[95:64] += carry sltu $t0, $t1, $t8 # product[127:96] = carry in 95:64 multu $t1, $t2 # b * c mflo $t8 # $t8 = (b * c)[31:0] addu $t2, $t2, $t8 # product[63:32] += (b * c)[31:0] sltu $t8, $t2, $t8` # $t8 = carry of 63:32 in last op addu $t1, $t1, $t8 # product[95:64] += carry mfhi $t8 # $t8 = (b * c)[63:32] addu $t1, $t1, $t8 # product[95:64] += (b * c)[63:32] sltu $t8, $t1, $t8 # $t8 = carry of 95:64 in last op addu $t0, $t0, $t8 # product[127:96] += carry multu $t4, $t6 # a * c mflo $t8 # $t8 = (a * c)[31:0] addu $t1, $t1, $t8 # product[95:64] += (a * c)[31:0] sltu $t8, $t1, $t8 # $t8 = carry of 95:64 in last op addu $t0, $t0, $t8 # product[127:96] += carry mfhi $t8 # $t8 = (a * c)[63:32] addu $t0, $t0, $t8 # product[127:96] += (a * c)[63:32] 4.52 Each CSA has a delay of 2T. The iterative CLA-based multiplier takes: 16 layers * CLA delay = 16 * 7T = 112T The CSA multiplier takes: 6 layers * 2T + CLA delay = 6 * 2T + 7T = 19T

4 4.53 (ai+1 ai ai1) == NOP + NOP = NOP == NOP + multiplicand = multiplicand == 2 * multiplicand + (-multiplicand) = multiplicand == 2 * multiplicand + NOP = 2 * multiplicand == -(2 * multiplicand) + NOP = -(2 * multiplicand) == -(2 * multiplicand) + multiplicand = -multiplicand == NOP + -multiplicand = -multiplicand == NOP + NOP = NOP 4.54 See Lecture notes. Basic algorithm is: Take the top 4 bits of the dividend, and subtract off the divisor. Based on the top value of the result, we choose whether the next stage is an add (top bit was 1), or a subtract (top bit was 0). The inverted value of this top bit is also the quotient result. The next stage is simply the lower 3 bits of the subtracted (or added) results, along with the next bit of the dividend. The divisor remains the same.

5 You continue this until you have used up all the bits of the dividend. The remainder is the final sum, unless the top bit is 1, in which case you have to add the divisor to that final sum to fix the remainder. A5.ktext 0x sw $a0, save0 sw $a1, save1 mfc0 $k0, $13 # Move Cause into $k0 mfc0 $k1, $14 # Move EPC into $k1 addiu $v0, $zero, 0x44 slt $v0, $v0, $k0 # Ignore interrupts bgtz $v0, _restore mov $a0, $k0 # Move Cause into $a0 mov $a1, $k1 # EPC into $a1 jal print_excp # Print exception error msg _restore: lw $a0, save0 lw $a1, save1 lw $k0, -4($k1) # $k0 = previous instruction srl $k0, $k0, 26 # $k0 = opcode of prev instr ori $k1, $zero, 2 # opcode of j beq $k0, $k1, _delayslot # ori $k0, $zero, 4 # opcode of beq beq $k0, $k1, _delayslot # and so on for: jr, jal, bne, bltz, bgezal, bczt... _done: mfc0 $k1, $14 # reload EPC into $k1 addiu $k1, $k1, 4 # Do not reexecute fault instr jr $k1 rfe # done in delay-slot of jr _delayslot: mfc0 $k1, $14 # reload EPC into $k1 addiu $k0, $k1, -4 # $k0 = EPC - 4 addiu $k1, $k1, 4 # $k1 = EPC + 4 jr $k0 # poke at branching instr j _check _check: rfe jr $k1 or $zero,$zero,$zero.kdata Save0:.word 0 save1:.word 0 This problem is hard. The basic idea of this solution is to do everything possible in order not to touch the instruction that caused the exception. We need a way to poke the branching instruction, that is, execute the instruction without executing any instructions around it. This procedure works by calling the branching instruction with jr, but putting a j in the delay-slot of the jr, so that we will jump back after executing the branching instruction and not execute its regular delay-slot. If it turns out that the branch is not taken (which may happen with a bne or beq), then we jump back to EPC+4. Note: this

6 solution assumes that j in branch delay slots will NOT executed if branch is taken! Other elegant solutions will be highly appreciated B.6 B.10 A B!A!B!(A+B)!A *!B!(A*B)!A +!B a) F = (!x3 &&!x2 && x1) (!x3 && x2 &&!x1) (x3 &&!x2 &&!x1) b) F = (!x3 && x2 && x1) (x3 &&!x2 && x1) (x3 && x2 &&!x1) c) F = (!x3 &&!x2) (!x3 &&!x1) d) F = (x3 &&!x2) (x3 && x1) B.14 Simply use two muxes: B.21

7 B.22 State Assignments: Left (00), Middle a (01), Right (10), Middle b (11) S1 S0 S1 S Solving the K-Maps for S1 and S0, you get: S1 = XOR (S1, S0) S0 = NOT (S0) The Outputs are associated with the state (where both Middle a, b output Middle) C.1 This looks just like the PLA on page C-20, except that there is now S0 through S9. The logic is the same, it just looks a lot bigger. Each column should also only be connected to one of the state bits.

Chapter loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop

Chapter loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop Chapter 3 3.7 loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop Instructions Format OP rs rt Imm lw $v1, 0($a0) I 35 4 3 0 addi $v0, $v0, 1 I 8

More information

MIPS Instruction Reference

MIPS Instruction Reference Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

More information

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

More information

MIPS Instruction Format

MIPS Instruction Format MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

More information

MIPS Reference Guide

MIPS Reference Guide MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

More information

Tailoring the 32-Bit ALU to MIPS

Tailoring the 32-Bit ALU to MIPS Tailoring the 32-Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance

More information

SPIM Instruction Set

SPIM Instruction Set SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

More information

COMP MIPS instructions 2 Feb. 8, f = g + h i;

COMP MIPS instructions 2 Feb. 8, f = g + h i; Register names (save, temporary, zero) From what I have said up to now, you will have the impression that you are free to use any of the 32 registers ($0,..., $31) in any instruction. This is not so, however.

More information

Computer Architecture. Chapter 3: Arithmetic for Computers

Computer Architecture. Chapter 3: Arithmetic for Computers 182.092 Computer Architecture Chapter 3: Arithmetic for Computers Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, Morgan Kaufmann Publishers and Mary Jane Irwin

More information

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local

More information

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design. Computer Organization - Previously covered ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

More information

ECE Exam I February 19 th, :00 pm 4:25pm

ECE Exam I February 19 th, :00 pm 4:25pm ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

More information

COMP 303 Computer Architecture Lecture 6

COMP 303 Computer Architecture Lecture 6 COMP 303 Computer Architecture Lecture 6 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 = 8 Multiplier x 1001 = 9 1000 0000 0000 1000 Product 01001000 = 72 n bits x n bits =

More information

The MIPS R2000 Instruction Set

The MIPS R2000 Instruction Set The MIPS R2000 Instruction Set Arithmetic and Logical Instructions In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions

More information

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation

More information

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

More information

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right

More information

Chapter 3 Arithmetic for Computers

Chapter 3 Arithmetic for Computers Chapter 3 Arithmetic for Computers 1 Arithmetic Where we've been: Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: Implementing the Architecture operation

More information

Assembly Programming

Assembly Programming Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

More information

Homework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures

Homework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures Homework 3 Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) 1 CSCI 402: Computer Architectures Arithmetic for Computers (2) Fengguang Song Department

More information

Week 10: Assembly Programming

Week 10: Assembly Programming Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +

More information

Compiling Techniques

Compiling Techniques Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically

More information

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers

More information

Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then

More information

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done

More information

MIPS Assembly Programming

MIPS Assembly Programming COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2

More information

CS 4200/5200 Computer Architecture I

CS 4200/5200 Computer Architecture I CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational

More information

Computer Architecture Experiment

Computer Architecture Experiment Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU

More information

Fast Arithmetic. Philipp Koehn. 19 October 2016

Fast Arithmetic. Philipp Koehn. 19 October 2016 Fast Arithmetic Philipp Koehn 19 October 2016 1 arithmetic Addition (Immediate) 2 Load immediately one number (s0 = 2) li $s0, 2 Add 4 ($s1 = $s0 + 4 = 6) addi $s1, $s0, 4 Subtract 3 ($s2 = $s1-3 = 3)

More information

Solutions for Chapter 2 Exercises

Solutions for Chapter 2 Exercises Solutions for Chapter 2 Exercises 1 Solutions for Chapter 2 Exercises 2.2 By lookup using the table in Figure 2.5 on page 62, 7fff fffa hex = 0111 1111 1111 1111 1111 1111 1111 1010 two = 2,147,483,642

More information

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H. Lipasti. University of Wisconsin-Madison. Basics Registers and ALU ops

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H. Lipasti. University of Wisconsin-Madison. Basics Registers and ALU ops ECE/CS 552: Instruction Sets Instructor:Mikko H. Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill. Instructions (354 Review) Instructions are

More information

Forecast. Instructions (354 Review) Basics. Basics. Instruction set architecture (ISA) is its vocabulary. Instructions are the words of a computer

Forecast. Instructions (354 Review) Basics. Basics. Instruction set architecture (ISA) is its vocabulary. Instructions are the words of a computer Instructions (354 Review) Forecast Instructions are the words of a computer Instruction set architecture (ISA) is its vocabulary With a few other things, this defines the interface of computers But implementations

More information

CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION. A bit of history CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

More information

MIPS PROJECT INSTRUCTION SET and FORMAT

MIPS PROJECT INSTRUCTION SET and FORMAT ECE 312: Semester Project MIPS PROJECT INSTRUCTION SET FORMAT This is a description of the required MIPS instruction set, their meanings, syntax, semantics, bit encodings. The syntax given for each instruction

More information

MIPS Instructions: 64-bit Core Subset

MIPS Instructions: 64-bit Core Subset MIPS Instructions: 64-bit Core Subset Spring 2008 General notes: a. R s, R t, and R d specify 64-bit general purpose registers b. F s, F t, and F d specify 64-bit floating point registers c. C d specifies

More information

Review (1/2) IEEE 754 Floating Point Standard: Kahan pack as much in as could get away with. CS61C - Machine Structures

Review (1/2) IEEE 754 Floating Point Standard: Kahan pack as much in as could get away with. CS61C - Machine Structures Review (1/2) CS61C - Machine Structures Lecture 11 - Starting a Program October 4, 2000 David Patterson http://www-inst.eecs.berkeley.edu/~cs61c/ IEEE 754 Floating Point Standard: Kahan pack as much in

More information

CS 61C: Great Ideas in Computer Architecture. Lecture 11: Datapath. Bernhard Boser & Randy Katz

CS 61C: Great Ideas in Computer Architecture. Lecture 11: Datapath. Bernhard Boser & Randy Katz CS 61C: Great Ideas in Computer Architecture Lecture 11: Datapath Bernhard Boser & Randy Katz http://inst.eecs.berkeley.edu/~cs61c Agenda MIPS Datapath add instruction register transfer level circuit timing

More information

CS 61c: Great Ideas in Computer Architecture

CS 61c: Great Ideas in Computer Architecture MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: $s0-$s7,$t0-$t9, $0

More information

ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016

ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Lecture 14: Recap. Today s topics: Recap for mid-term No electronic devices in midterm

Lecture 14: Recap. Today s topics: Recap for mid-term No electronic devices in midterm Lecture 14: Recap Today s topics: Recap for mid-term No electronic devices in midterm 1 Modern Trends Historical contributions to performance: Better processes (faster devices) ~20% Better circuits/pipelines

More information

We will study the MIPS assembly language as an exemplar of the concept.

We will study the MIPS assembly language as an exemplar of the concept. MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and

More information

Digital System Design II

Digital System Design II Digital System Design II 数字系统设计 II Peng Liu ( 刘鹏 ) Dept. of Info. Sci. & Elec. Engg. Zhejiang University liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture 2 Textbook reading MIPS ISA 2.1-2.4

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures $2M 3D camera Lecture 8 MIPS Instruction Representation I Instructor: Miki Lustig 2014-09-17 August 25: The final ISA showdown: Is ARM, x86, or

More information

USING A SIMULATOR. QUICK INTRODUCTION From various sources For cs470

USING A SIMULATOR. QUICK INTRODUCTION From various sources For cs470 USING A SIMULATOR QUICK INTRODUCTION From various sources For cs470 INTRODUCTION MARS INTERFACE SIMULATOR USAGE MIPS ASSEMBLER LANGUAGE PROGRAM EXAMPLE Introduction MARS IDE A simulator for the MIPS processor

More information

Patterson PII. Solutions

Patterson PII. Solutions Patterson-1610874 978-0-12-407726-3 PII 2 Solutions Chapter 2 Solutions S-3 2.1 addi f, h, -5 (note, no subi) add f, f, g 2.2 f = g + h + i 2.3 sub $t0, $s3, $s4 add $t0, $s6, $t0 lw $t1, 16($t0) sw $t1,

More information

EE108B Lecture 3. MIPS Assembly Language II

EE108B Lecture 3. MIPS Assembly Language II EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework

More information

MIPS%Assembly% E155%

MIPS%Assembly% E155% MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary

More information

Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B

Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B Anne Bracy CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. See P&H Chapter: 2.16-2.20, 4.1-4.4,

More information

CS152 Computer Architecture and Engineering. Lecture 1 Introduction & MIPS Review Dave Patterson. www-inst.eecs.berkeley.

CS152 Computer Architecture and Engineering. Lecture 1 Introduction & MIPS Review Dave Patterson. www-inst.eecs.berkeley. CS152 Computer Architecture and Engineering Lecture 1 Introduction & MIPS Review 2003-08-26 Dave Patterson (www.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs152/ CS 152 L01 Introduction &

More information

Lecture 6 Decision + Shift + I/O

Lecture 6 Decision + Shift + I/O Lecture 6 Decision + Shift + I/O Instructions so far MIPS C Program add, sub, addi, multi, div lw $t0,12($s0) sw $t0, 12($s0) beq $s0, $s1, L1 bne $s0, $s1, L1 j L1 (unconditional branch) slt reg1,reg2,reg3

More information

CSE Lecture In Class Example Handout

CSE Lecture In Class Example Handout CSE 30321 Lecture 07-08 In Class Example Handout Part A: J-Type Example: If you look in your book at the syntax for j (an unconditional jump instruction), you see something like: e.g. j addr would seemingly

More information

Arithmetic. Chapter 3 Computer Organization and Design

Arithmetic. Chapter 3 Computer Organization and Design Arithmetic Chapter 3 Computer Organization and Design Addition Addition is similar to decimals 0000 0111 + 0000 0101 = 0000 1100 Subtraction (negate) 0000 0111 + 1111 1011 = 0000 0010 Over(under)flow For

More information

Chapter 6. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 6 <1>

Chapter 6. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 6 <1> Chapter 6 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 6 Chapter 6 :: Topics Introduction Assembly Language Machine Language Programming Addressing

More information

CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14

CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14 CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017 Frame Pointer (1) The stack is also used to store variables that are local to function, but

More information

Control Unit. Simulation. Result

Control Unit. Simulation. Result Control Unit One of the basic modules for a CPU is the control unit. Our task was to design the control unit with the following functions: sw, lw, beq, bne, j, add, sub, and, or, slt, addi. The implementation

More information

CPS 104 Computer Organization and Programming

CPS 104 Computer Organization and Programming CPS 104 Computer Organization and Programming Lecture 9: Integer Arithmetic. Robert Wagner CPS104 IMD.1 RW Fall 2000 Overview of Today s Lecture: Integer Multiplication and Division. Read Appendix B CPS104

More information

CHW 362 : Computer Architecture & Organization

CHW 362 : Computer Architecture & Organization CHW 362 : Computer Architecture & Organization Instructors: Dr Ahmed Shalaby Dr Mona Ali http://bu.edu.eg/staff/ahmedshalaby14# http://www.bu.edu.eg/staff/mona.abdelbaset Assignment What is the size of

More information

CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014

CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 B CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 DUE : March 3, 2014 READ : - Related sections of Chapter 2 - Related sections of Chapter 3 - Related sections of Appendix A - Related sections

More information

Lab 3: Pipelined MIPS Assigned: Wed., 2/13; Due: Fri., 3/1 (Midnight)

Lab 3: Pipelined MIPS Assigned: Wed., 2/13; Due: Fri., 3/1 (Midnight) CMU 18-447 Introduction to Computer Architecture Spring 2013 1/7 Lab 3: Pipelined MIPS Assigned: Wed., 2/13; Due: Fri., 3/1 (Midnight) Instructor: Onur Mutlu TAs: Justin Meza, Yoongu Kim, Jason Lin It

More information

A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3 A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU

More information

Grading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off.

Grading: 3 pts each part. If answer is correct but uses more instructions, 1 pt off. Wrong answer 3pts off. Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 552 Introductions to Computer Architecture Homework #2 (Suggested Solution) 1. (10 points) MIPS and C program translations

More information

Recitation 5: Recitation 5: MIPS Interrupts and Floating Point

Recitation 5: Recitation 5: MIPS Interrupts and Floating Point Float Operations We will write a full program to read in two floats, perform an add, subtract, multiply, and divide, printing out each result Let s attempt in C (using blocking IO) Float Operations We

More information

Review of the Machine Cycle

Review of the Machine Cycle MIPS Branch and Jump Instructions Cptr280 Dr Curtis Nelson Review of the Machine Cycle When a program is executing, its instructions are located in main memory. The address of an instruction is the address

More information

Chapter 6 :: Topics. Chapter 6 :: Architecture

Chapter 6 :: Topics. Chapter 6 :: Architecture Chapter 6 :: Architecture Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Chapter 6 :: Topics Introduction Assembly Language Machine Language Programming Addressing Modes

More information

Administrivia. Midterm Exam - You get to bring. What you don t need to bring. Conflicts? DSP accomodations? Head TA

Administrivia. Midterm Exam - You get to bring. What you don t need to bring. Conflicts? DSP accomodations?  Head TA inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 16 Running a Program (Compiling, Assembling, Linking, Loading) Sr Lecturer SOE Dan Garcia Research shows laptops and tablets in class

More information

Mark Redekopp, All rights reserved. EE 352 Unit 4. Assembly and the MARS Simulator Control Flow (Branch Instructions)

Mark Redekopp, All rights reserved. EE 352 Unit 4. Assembly and the MARS Simulator Control Flow (Branch Instructions) EE 352 Unit 4 Assembly and the MARS Simulator Control Flow (Branch Instructions) Directives Pseudo-instructions ASSEMBLERS Assembler Syntax In MARS and most assemblers each line of the assembly program

More information

LECTURE 10. Pipelining: Advanced ILP

LECTURE 10. Pipelining: Advanced ILP LECTURE 10 Pipelining: Advanced ILP EXCEPTIONS An exception, or interrupt, is an event other than regular transfers of control (branches, jumps, calls, returns) that changes the normal flow of instruction

More information

8*4 + 4 = 36 each int is 4 bytes

8*4 + 4 = 36 each int is 4 bytes CS 61CL (Clancy) Solutions and grading standards for exam 1 Spring 2009 169 students took the exam. The average score was 43.6; the median was 46. Scores ranged from 1 to 59. There were 89 scores between

More information

Review from last time. CS152 Computer Architecture and Engineering Lecture 6. Verilog (finish) Multiply, Divide, Shift

Review from last time. CS152 Computer Architecture and Engineering Lecture 6. Verilog (finish) Multiply, Divide, Shift Review from last time CS152 Computer Architecture and Engineering Lecture 6 Verilog (finish) Multiply, Divide, Shift February 11, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/

More information

ECE Exam I - Solutions February 19 th, :00 pm 4:25pm

ECE Exam I - Solutions February 19 th, :00 pm 4:25pm ECE 3056 Exam I - Solutions February 19 th, 2015 3:00 pm 4:25pm 1. (35 pts) Consider the following block of SPIM code. The text segment starts at 0x00400000 and the data segment starts at 0x10010000..data

More information

Arithmetic for Computers. Hwansoo Han

Arithmetic for Computers. Hwansoo Han Arithmetic for Computers Hwansoo Han Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems The MIPS Instruction Set Martha A. Kim Columbia University Fall 2015 1 / 67 Instruction Set Architectures MIPS The GCD Algorithm MIPS Registers Types of Instructions Computational

More information

Lab 4 Report. Single Cycle Design BAOTUNG C. TRAN EEL4713C

Lab 4 Report. Single Cycle Design BAOTUNG C. TRAN EEL4713C Lab 4 Report Single Cycle Design BAOTUNG C. TRAN EEL4713C Added Hardware : Andi and Ori : For this instruction, I had to add a zero extender into my design. Which therefore required me to add a mux that

More information

Welcome to CS250 VLSI Systems Design

Welcome to CS250 VLSI Systems Design Image Courtesy: Intel Welcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee YUNSUP LEE Email: yunsup@cs.berkeley.edu Please add [CS250] in the subject Will try to get back in a day CS250 Newsgroup Post

More information

Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:

Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#: Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators

More information

Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21

Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...

More information

A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3 A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Announcements! HW2 available later today HW2 due in one week and a half Work alone

More information

A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches

More information

Concocting an Instruction Set

Concocting an Instruction Set Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von

More information

SMIPS Processor Specification

SMIPS Processor Specification SMIPS Processor Specification CS250 VLSI Systems Design September 25, 2009 SMIPS is the version of the MIPS instruction set architecture (ISA) we ll be using for the processors we implement in 6.884. SMIPS

More information

Harnessing FPGAs for Computer Architecture Education

Harnessing FPGAs for Computer Architecture Education Harnessing FPGAs for Computer Architecture Education Mark Holland, James Harris, Scott Hauck Department of Electrical Engineering University of Washington, Seattle, WA 98195, USA mholland@ee.washington.edu,

More information

CSc 256 Final Spring 2011

CSc 256 Final Spring 2011 CSc 256 Final Spring 2011 NAME: Problem1: Convertthedecimalfloatingpointnumber 4.3toa32 bitfloat(inbinary)inieee 754standardrepresentation.Showworkforpartialcredit.10points Hint:IEEE754formatfor32 bitfloatsconsistsofs

More information

Problem maximum score 1 35pts 2 22pts 3 23pts 4 15pts Total 95pts

Problem maximum score 1 35pts 2 22pts 3 23pts 4 15pts Total 95pts University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS61c Summer 2001 Woojin Yu Midterm Exam This is a closed-book exam. No calculators

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 14 Introduction to MIPS Instruction Representation II Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia Are you P2P sharing fans? Two

More information

EE 109 Unit 8 MIPS Instruction Set

EE 109 Unit 8 MIPS Instruction Set 1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system

More information

COMP2611: Computer Organization MIPS function and recursion

COMP2611: Computer Organization MIPS function and recursion COMP2611 Fall2015 COMP2611: Computer Organization MIPS function and recursion Overview 2 You will learn the following in this lab: how to use MIPS functions in a program; the concept of recursion; how

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 14 Introduction to MIPS Instruction Representation II 2004-02-23 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia In the US, who is

More information

CPU Design for Computer Integrated Experiment

CPU Design for Computer Integrated Experiment CPU Design for Computer Integrated Experiment Shan Lu, Guangyao Li, Yijianan Wang CEIE, Tongji University, Shanghai, China Abstract - Considering the necessity and difficulty of designing a CPU for students,

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 17 Instruction Representation III 2010-03-01! Hello to Sherif Kandel listening from Egypt!!!Lecturer SOE Dan Garcia!!!www.cs.berkeley.edu/~ddgarcia

More information

Midterm. CS64 Spring Midterm Exam

Midterm. CS64 Spring Midterm Exam Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every

More information

CS61C Machine Structures. Lecture 10 - MIPS Branch Instructions II. 2/8/2006 John Wawrzynek. (www.cs.berkeley.edu/~johnw)

CS61C Machine Structures. Lecture 10 - MIPS Branch Instructions II. 2/8/2006 John Wawrzynek. (www.cs.berkeley.edu/~johnw) CS61C Machine Structures Lecture 10 - MIPS Branch Instructions II 2/8/2006 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L10 MIPS Branch II (1) Compiling C if into

More information

CS3350B Computer Architecture

CS3350B Computer Architecture CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,

More information

Learning Outcomes. System Calls. System Calls. The System Call Interface: A Brief Overview. System Calls. The Structure of a Computer System

Learning Outcomes. System Calls. System Calls. The System Call Interface: A Brief Overview. System Calls. The Structure of a Computer System Learning Outcomes System Calls Interface and Implementation A high-level understanding of System Call interface Mostly from the user s perspective From textbook (section.6) Understanding of how the application-kernel

More information

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction

More information

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 C functions main() { int i,j,k,m;... i = mult(j,k);... m = mult(i,i);... } What information must compiler/programmer keep

More information

Number Systems and Computer Arithmetic

Number Systems and Computer Arithmetic Number Systems and Computer Arithmetic Counting to four billion two fingers at a time What do all those bits mean now? bits (011011011100010...01) instruction R-format I-format... integer data number text

More information

Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary

Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary Announcements EE108B Lecture MIPS Assembly Language III Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b PA1 available, due on Thursday 2/8 Work on you own (no groups) Homework

More information

Concocting an Instruction Set

Concocting an Instruction Set Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Lab is posted. Do your prelab! Stay tuned for the first problem set. L04 Instruction

More information