HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b;

Size: px
Start display at page:

Download "HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b;"

Transcription

1 HW2 solutions 3.10 Pseuodinstructions What is accomplished Minimum sequence of Mips Move $t5, $t3 $t5=$t3 Add $t5, $t3, $0 Clear $t5 $t5=0 Xor $t5, $t5, $t5 Li $t5, small $t5=small Addi $t5, $0, small Li $t5, big $t5=big lui $t5, big[31:16] Ori $t5, $t5, big[15:0] Lw $t5, big($t3) $t5=mem[$t3+big] Lui $t5, big[31:26] Ori $t5, $t0, big[15:0] Add $t3, $t3, $t5 Lw $t5, 0($t3) Addi $t5, $t3, big $t5=$t3+big Lui $t5, big[31:16] Ori $t5, big[15:0] Addi $t5, $t5, $t3 Beq $t5, small, L If $t5=small, branch to L Addi $at, $0, small Beq $t5, $at, L Beq $t5, big, L If $t5=big, branch to L Lui $at, big[31:16] Ori $at, big[15:0] Beq $at, $t5, L Ble $t5, $t3, L If $t5<=$t3, branch to L Slt $at, $t3, $t5 Beq $at, $0, L Bge $t5, $t3, L If $t5>=$t3, branch to L Slt $at, $t5, $3 Beq $at, $0, L Bgt $t5, $t3, L If $t5>$t3, branch to L Slt $at, $t3, $t5 Bne $at, $0 L 3.25 You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b; 3.30 sbn neg_a, neg_a,.+1 # neg_a = 0; sbn neg_a, a,.+1 # neg_a = -a; sbn c, c,.+1 # c = 0; loop: sbn b, one,.+1 # do { b = b 1; sbn c, neg_a,.+1 # c = c + a; sbn temp, temp,.+1 # temp = 0; sbn temp, b, loop # } while (b > 0);

2 Note (1) This solution does not work if b = 0, because the problem description said to assume that a and b are greater than 0. Perfectionist students are likely to write solutions that do work for b = 0 though, so their answers would be an instruction or too long add $t2, $t3, $t4 slt $t2, $t2, $t You need only alter the full adder for the MSB such that the Set output is the value of the full adder output XORed with the Overflow 4.24 (a * 2^32 + b) * (c * 2^32 + d) = (a * c * 2^64 + a * d * 2^32 + b * c * 2^32 + b * d multu $t5, $t7 # b * d mflo $t3 # product[31:0] = (b * d)[31:0] mfhi $t2 # product[63:32] = (b * d)[64:32] multu $t4, $t7 # a * d mflo $t8 # $t8 = (a * d)[31:0] mfhi $t1 # product[95:64] = (a * d)[63:32] addu $t2, $t2, $t8 # product[63:32] += (a * d)[31:0] sltu $t8, $t2, $t8 # $t8 = carry of 63:32 in last op

3 addu $t1, $t1, $t8 # product[95:64] += carry sltu $t0, $t1, $t8 # product[127:96] = carry in 95:64 multu $t1, $t2 # b * c mflo $t8 # $t8 = (b * c)[31:0] addu $t2, $t2, $t8 # product[63:32] += (b * c)[31:0] sltu $t8, $t2, $t8` # $t8 = carry of 63:32 in last op addu $t1, $t1, $t8 # product[95:64] += carry mfhi $t8 # $t8 = (b * c)[63:32] addu $t1, $t1, $t8 # product[95:64] += (b * c)[63:32] sltu $t8, $t1, $t8 # $t8 = carry of 95:64 in last op addu $t0, $t0, $t8 # product[127:96] += carry multu $t4, $t6 # a * c mflo $t8 # $t8 = (a * c)[31:0] addu $t1, $t1, $t8 # product[95:64] += (a * c)[31:0] sltu $t8, $t1, $t8 # $t8 = carry of 95:64 in last op addu $t0, $t0, $t8 # product[127:96] += carry mfhi $t8 # $t8 = (a * c)[63:32] addu $t0, $t0, $t8 # product[127:96] += (a * c)[63:32] 4.52 Each CSA has a delay of 2T. The iterative CLA-based multiplier takes: 16 layers * CLA delay = 16 * 7T = 112T The CSA multiplier takes: 6 layers * 2T + CLA delay = 6 * 2T + 7T = 19T

4 4.53 (ai+1 ai ai1) == NOP + NOP = NOP == NOP + multiplicand = multiplicand == 2 * multiplicand + (-multiplicand) = multiplicand == 2 * multiplicand + NOP = 2 * multiplicand == -(2 * multiplicand) + NOP = -(2 * multiplicand) == -(2 * multiplicand) + multiplicand = -multiplicand == NOP + -multiplicand = -multiplicand == NOP + NOP = NOP 4.54 See Lecture notes. Basic algorithm is: Take the top 4 bits of the dividend, and subtract off the divisor. Based on the top value of the result, we choose whether the next stage is an add (top bit was 1), or a subtract (top bit was 0). The inverted value of this top bit is also the quotient result. The next stage is simply the lower 3 bits of the subtracted (or added) results, along with the next bit of the dividend. The divisor remains the same.

5 You continue this until you have used up all the bits of the dividend. The remainder is the final sum, unless the top bit is 1, in which case you have to add the divisor to that final sum to fix the remainder. A5.ktext 0x sw $a0, save0 sw $a1, save1 mfc0 $k0, $13 # Move Cause into $k0 mfc0 $k1, $14 # Move EPC into $k1 addiu $v0, $zero, 0x44 slt $v0, $v0, $k0 # Ignore interrupts bgtz $v0, _restore mov $a0, $k0 # Move Cause into $a0 mov $a1, $k1 # EPC into $a1 jal print_excp # Print exception error msg _restore: lw $a0, save0 lw $a1, save1 lw $k0, -4($k1) # $k0 = previous instruction srl $k0, $k0, 26 # $k0 = opcode of prev instr ori $k1, $zero, 2 # opcode of j beq $k0, $k1, _delayslot # ori $k0, $zero, 4 # opcode of beq beq $k0, $k1, _delayslot # and so on for: jr, jal, bne, bltz, bgezal, bczt... _done: mfc0 $k1, $14 # reload EPC into $k1 addiu $k1, $k1, 4 # Do not reexecute fault instr jr $k1 rfe # done in delay-slot of jr _delayslot: mfc0 $k1, $14 # reload EPC into $k1 addiu $k0, $k1, -4 # $k0 = EPC - 4 addiu $k1, $k1, 4 # $k1 = EPC + 4 jr $k0 # poke at branching instr j _check _check: rfe jr $k1 or $zero,$zero,$zero.kdata Save0:.word 0 save1:.word 0 This problem is hard. The basic idea of this solution is to do everything possible in order not to touch the instruction that caused the exception. We need a way to poke the branching instruction, that is, execute the instruction without executing any instructions around it. This procedure works by calling the branching instruction with jr, but putting a j in the delay-slot of the jr, so that we will jump back after executing the branching instruction and not execute its regular delay-slot. If it turns out that the branch is not taken (which may happen with a bne or beq), then we jump back to EPC+4. Note: this

6 solution assumes that j in branch delay slots will NOT executed if branch is taken! Other elegant solutions will be highly appreciated B.6 B.10 A B!A!B!(A+B)!A *!B!(A*B)!A +!B a) F = (!x3 &&!x2 && x1) (!x3 && x2 &&!x1) (x3 &&!x2 &&!x1) b) F = (!x3 && x2 && x1) (x3 &&!x2 && x1) (x3 && x2 &&!x1) c) F = (!x3 &&!x2) (!x3 &&!x1) d) F = (x3 &&!x2) (x3 && x1) B.14 Simply use two muxes: B.21

7 B.22 State Assignments: Left (00), Middle a (01), Right (10), Middle b (11) S1 S0 S1 S Solving the K-Maps for S1 and S0, you get: S1 = XOR (S1, S0) S0 = NOT (S0) The Outputs are associated with the state (where both Middle a, b output Middle) C.1 This looks just like the PLA on page C-20, except that there is now S0 through S9. The logic is the same, it just looks a lot bigger. Each column should also only be connected to one of the state bits.

Chapter loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop

Chapter loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop Chapter 3 3.7 loop: lw $v1, 0($a0) addi $v0, $v0, 1 sw $v1, 0($a1) addi $a0, $a0, 1 addi $a1, $a1, 1 bne $v1, $zero, loop Instructions Format OP rs rt Imm lw $v1, 0($a0) I 35 4 3 0 addi $v0, $v0, 1 I 8

More information

CS152 Computer Architecture and Engineering

CS152 Computer Architecture and Engineering University of California, Berkeley College of Engineering Electrical Engineering and Computer Science, Computer Science Division Fall 2001 CS152 Computer Architecture and Engineering Homework #2 Solutions

More information

F. Appendix 6 MIPS Instruction Reference

F. Appendix 6 MIPS Instruction Reference F. Appendix 6 MIPS Instruction Reference Note: ALL immediate values should be sign extended. Exception: For logical operations immediate values should be zero extended. After extensions, you treat them

More information

MIPS Instruction Reference

MIPS Instruction Reference Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

More information

Flow of Control -- Conditional branch instructions

Flow of Control -- Conditional branch instructions Flow of Control -- Conditional branch instructions You can compare directly Equality or inequality of two registers One register with 0 (>,

More information

Examples of branch instructions

Examples of branch instructions Examples of branch instructions Beq rs,rt,target #go to target if rs = rt Beqz rs, target #go to target if rs = 0 Bne rs,rt,target #go to target if rs!= rt Bltz rs, target #go to target if rs < 0 etc.

More information

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

More information

MIPS Instruction Format

MIPS Instruction Format MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

More information

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction

More information

MIPS Reference Guide

MIPS Reference Guide MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

More information

MIPS Instruction Set

MIPS Instruction Set MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central

More information

Tailoring the 32-Bit ALU to MIPS

Tailoring the 32-Bit ALU to MIPS Tailoring the 32-Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly)

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam One 4 February Your Name (please print clearly) Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

Arithmetic for Computers

Arithmetic for Computers MIPS Arithmetic Instructions Cptr280 Dr Curtis Nelson Arithmetic for Computers Operations on integers Addition and subtraction; Multiplication and division; Dealing with overflow; Signed vs. unsigned numbers.

More information

SPIM Instruction Set

SPIM Instruction Set SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

More information

COMP MIPS instructions 2 Feb. 8, f = g + h i;

COMP MIPS instructions 2 Feb. 8, f = g + h i; Register names (save, temporary, zero) From what I have said up to now, you will have the impression that you are free to use any of the 32 registers ($0,..., $31) in any instruction. This is not so, however.

More information

Lecture 8: Addition, Multiplication & Division

Lecture 8: Addition, Multiplication & Division Lecture 8: Addition, Multiplication & Division Today s topics: Signed/Unsigned Addition Multiplication Division 1 Signed / Unsigned The hardware recognizes two formats: unsigned (corresponding to the C

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.

More information

M2 Instruction Set Architecture

M2 Instruction Set Architecture M2 Instruction Set Architecture Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine

More information

Q1: /30 Q2: /25 Q3: /45. Total: /100

Q1: /30 Q2: /25 Q3: /45. Total: /100 ECE 2035(A) Programming for Hardware/Software Systems Fall 2013 Exam One September 19 th 2013 This is a closed book, closed note texam. Calculators are not permitted. Please work the exam in pencil and

More information

Computer Architecture. The Language of the Machine

Computer Architecture. The Language of the Machine Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers

More information

The MIPS Instruction Set Architecture

The MIPS Instruction Set Architecture The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use

More information

Review: MIPS Organization

Review: MIPS Organization 1 MIPS Arithmetic Review: MIPS Organization Processor Memory src1 addr 5 src2 addr 5 dst addr 5 write data Register File registers ($zero - $ra) bits src1 data src2 data read/write addr 1 1100 2 30 words

More information

Reduced Instruction Set Computer (RISC)

Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying

More information

Computer Architecture. Chapter 3: Arithmetic for Computers

Computer Architecture. Chapter 3: Arithmetic for Computers 182.092 Computer Architecture Chapter 3: Arithmetic for Computers Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, Morgan Kaufmann Publishers and Mary Jane Irwin

More information

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2) Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into

More information

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 19 September 2012 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

Number Systems and Their Representations

Number Systems and Their Representations Number Representations Cptr280 Dr Curtis Nelson Number Systems and Their Representations In this presentation you will learn about: Representation of numbers in computers; Signed vs. unsigned numbers;

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local

More information

MIPS Integer ALU Requirements

MIPS Integer ALU Requirements MIPS Integer ALU Requirements Add, AddU, Sub, SubU, AddI, AddIU: 2 s complement adder/sub with overflow detection. And, Or, Andi, Ori, Xor, Xori, Nor: Logical AND, logical OR, XOR, nor. SLTI, SLTIU (set

More information

NUMBER OPERATIONS. Mahdi Nazm Bojnordi. CS/ECE 3810: Computer Organization. Assistant Professor School of Computing University of Utah

NUMBER OPERATIONS. Mahdi Nazm Bojnordi. CS/ECE 3810: Computer Organization. Assistant Professor School of Computing University of Utah NUMBER OPERATIONS Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 3810: Computer Organization Overview Homework 4 is due tonight Verify your uploaded file before the

More information

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,

More information

ECE Exam I February 19 th, :00 pm 4:25pm

ECE Exam I February 19 th, :00 pm 4:25pm ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

More information

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total

ECE 2035 Programming HW/SW Systems Spring problems, 6 pages Exam Two 11 March Your Name (please print) total Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

COMP 303 Computer Architecture Lecture 6

COMP 303 Computer Architecture Lecture 6 COMP 303 Computer Architecture Lecture 6 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 = 8 Multiplier x 1001 = 9 1000 0000 0000 1000 Product 01001000 = 72 n bits x n bits =

More information

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design. Computer Organization - Previously covered ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

More information

The MIPS R2000 Instruction Set

The MIPS R2000 Instruction Set The MIPS R2000 Instruction Set Arithmetic and Logical Instructions In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions

More information

Integer Multiplication and Division

Integer Multiplication and Division Integer Multiplication and Division COE 301 Computer Organization Prof. Muhamed Mudawar College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals Presentation Outline

More information

MIPS Assembly Language

MIPS Assembly Language MIPS Assembly Language Chapter 15 S. Dandamudi Outline MIPS architecture Registers Addressing modes MIPS instruction set Instruction format Data transfer instructions Arithmetic instructions Logical/shift/rotate/compare

More information

MIPS Assembly Language Programming

MIPS Assembly Language Programming MIPS Assembly Language Programming Bob Britton Chapter 1 The MIPS Architecture My objective in teaching assembly language is to introduce students to the fundamental concepts of contemporary computer architecture.

More information

bits 5..0 the sub-function of opcode 0, 32 for the add instruction

bits 5..0 the sub-function of opcode 0, 32 for the add instruction CS2 Computer Systems note 1a Some MIPS instructions More details on these, and other instructions in the MIPS instruction set, can be found in Chapter 3 of Patterson and Hennessy. A full listing of MIPS

More information

RTL Model of a Two-Stage MIPS Processor

RTL Model of a Two-Stage MIPS Processor RTL Model of a Two-Stage MIPS Processor 6.884 Laboratory February 4, 5 - Version 45 Introduction For the first lab assignment, you are to write an RTL model of a two-stage pipelined MIPS processor using

More information

Chapter 3 Arithmetic for Computers. ELEC 5200/ From P-H slides

Chapter 3 Arithmetic for Computers. ELEC 5200/ From P-H slides Chapter 3 Arithmetic for Computers 1 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation

More information

CSc 256 Midterm 2 Fall 2011

CSc 256 Midterm 2 Fall 2011 CSc 256 Midterm 2 Fall 2011 NAME: 1a) You are given a MIPS branch instruction: x: beq $12, $0, y The address of the label "y" is 0x400468. The memory location at "x" contains: address contents 0x40049c

More information

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation

More information

MIPS Assembly Language. Today s Lecture

MIPS Assembly Language. Today s Lecture MIPS Assembly Language Computer Science 104 Lecture 6 Homework #2 Midterm I Feb 22 (in class closed book) Outline Assembly Programming Reading Chapter 2, Appendix B Today s Lecture 2 Review: A Program

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam One 22 September Your Name (please print clearly) Signed. Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

TSK3000A - Generic Instructions

TSK3000A - Generic Instructions TSK3000A - Generic Instructions Frozen Content Modified by Admin on Sep 13, 2017 Using the core set of assembly language instructions for the TSK3000A as building blocks, a number of generic instructions

More information

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

More information

Computer Science 61C Spring Friedland and Weaver. Instruction Encoding

Computer Science 61C Spring Friedland and Weaver. Instruction Encoding Instruction Encoding 1 Instruction Formats I-format: used for instructions with immediates, lw and sw (since offset counts as an immediate), and branches (beq and bne) since branches are "relative" to

More information

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right

More information

Chapter 3 Arithmetic for Computers

Chapter 3 Arithmetic for Computers Chapter 3 Arithmetic for Computers 1 Arithmetic Where we've been: Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: Implementing the Architecture operation

More information

CS61c MIDTERM EXAM: 3/17/99

CS61c MIDTERM EXAM: 3/17/99 CS61c MIDTERM EXAM: 3/17/99 D. A. Patterson Last name Student ID number First name Login: cs61c- Please circle the last two letters of your login name. a b c d e f g h i j k l m n o p q r s t u v w x y

More information

Kernel Registers 0 1. Global Data Pointer. Stack Pointer. Frame Pointer. Return Address.

Kernel Registers 0 1. Global Data Pointer. Stack Pointer. Frame Pointer. Return Address. The MIPS Register Set The MIPS R2000 CPU has 32 registers. 31 of these are general-purpose registers that can be used in any of the instructions. The last one, denoted register zero, is defined to contain

More information

Computer Architecture. MIPS Instruction Set Architecture

Computer Architecture. MIPS Instruction Set Architecture Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design

More information

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

Integer Arithmetic. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University

Integer Arithmetic. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University Integer Arithmetic Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)

More information

INSTRUCTION SET COMPARISONS

INSTRUCTION SET COMPARISONS INSTRUCTION SET COMPARISONS MIPS SPARC MOTOROLA REGISTERS: INTEGER 32 FIXED WINDOWS 32 FIXED FP SEPARATE SEPARATE SHARED BRANCHES: CONDITION CODES NO YES NO COMPARE & BR. YES NO YES A=B COMP. & BR. YES

More information

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-2 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

More information

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011 CSE 2021: Computer Organization Recap from Last Time load from disk High-Level Program Lecture-3 Code Translation-1 Registers, Arithmetic, logical, jump, and branch instructions MIPS to machine language

More information

Homework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures

Homework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures Homework 3 Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) 1 CSCI 402: Computer Architectures Arithmetic for Computers (2) Fengguang Song Department

More information

5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner. Topic 3: Arithmetic

5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner. Topic 3: Arithmetic 5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner Topic 3: Arithmetic These slides are mostly taken verbatim, or with minor changes, from those

More information

Assembly Programming

Assembly Programming Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

More information

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Computer Organization and Structure. Bing-Yu Chen National Taiwan University Computer Organization and Structure Bing-Yu Chen National Taiwan University Arithmetic for Computers Addition and Subtraction Gate Logic and K-Map Method Constructing a Basic ALU Arithmetic Logic Unit

More information

CSc 256 Midterm 2 Spring 2012

CSc 256 Midterm 2 Spring 2012 CSc 256 Midterm 2 Spring 2012 NAME: 1a) You are given this MIPS assembly language instruction (i.e., pseudo- instruction): ble $12, 0x20004880, there Translate this MIPS instruction to an efficient sequence

More information

CENG3420 L05: Arithmetic and Logic Unit

CENG3420 L05: Arithmetic and Logic Unit CENG3420 L05: Arithmetic and Logic Unit Bei Yu byu@cse.cuhk.edu.hk (Latest update: January 25, 2018) Spring 2018 1 / 53 Overview Overview Addition Multiplication & Division Shift Floating Point Number

More information

CS61C - Machine Structures. Lecture 6 - Instruction Representation. September 15, 2000 David Patterson.

CS61C - Machine Structures. Lecture 6 - Instruction Representation. September 15, 2000 David Patterson. CS61C - Machine Structures Lecture 6 - Instruction Representation September 15, 2000 David Patterson http://www-inst.eecs.berkeley.edu/~cs61c/ 1 Review Instructions: add, addi, sub, lw, sw beq, bne, j

More information

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei

Computer Architecture Instruction Set Architecture part 2. Mehran Rezaei Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter

More information

Review of Last lecture. Review ALU Design. Designing a Multiplier Shifter Design Review. Booth s algorithm. Today s Outline

Review of Last lecture. Review ALU Design. Designing a Multiplier Shifter Design Review. Booth s algorithm. Today s Outline Today s Outline San Jose State University EE176-SJSU Computer Architecture and Organization Lecture 5 HDL, ALU, Shifter, Booth Algorithm Multiplier & Divider Instructor: Christopher H. Pham Review of Last

More information

ECE 30 Introduction to Computer Engineering

ECE 30 Introduction to Computer Engineering ECE 30 Introduction to Computer Engineering Study Problems, Set #3 Spring 2015 Use the MIPS assembly instructions listed below to solve the following problems. arithmetic add add sub subtract addi add

More information

Week 10: Assembly Programming

Week 10: Assembly Programming Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +

More information

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible

More information

ECE 15B Computer Organization Spring 2010

ECE 15B Computer Organization Spring 2010 ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 7: Procedures I Partially adapted from Computer Organization and Design, 4 th edition, Patterson and Hennessy, and classes taught by and

More information

CMPE324 Computer Architecture Lecture 2

CMPE324 Computer Architecture Lecture 2 CMPE324 Computer Architecture Lecture 2.1 What is Computer Architecture? Software Hardware Application (Netscape) Operating System Compiler (Unix; Assembler Windows 9x) Processor Memory Datapath & Control

More information

Compiling Techniques

Compiling Techniques Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically

More information

Programming the processor

Programming the processor CSC258 Week 9 Logistics This week: Lab 7 is the last Logisim DE2 lab. Next week: Lab 8 will be assembly. For assembly labs you can work individually or in pairs. No matter how you do it, the important

More information

Exam in Computer Engineering

Exam in Computer Engineering Exam in Computer Engineering Kurskod D0013E/SMD137/SMD082/SMD066 Tentamensdatum 2010-10-29 Skrivtid 14.00-18.00 Maximalt resultat 50 poäng Godkänt resultat 25 poäng Jourhavande lärare Andrey Kruglyak Tel

More information

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture ECE468 Computer Organization & Architecture MIPS Instruction Set Architecture ECE468 Lec4.1 MIPS R2000 / R3000 Registers 32-bit machine --> Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0 = 0) 32

More information

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix

More information

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done

More information

COMPUTER ORGANIZATION AND DESIGN

COMPUTER ORGANIZATION AND DESIGN COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication

More information

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 21 October 2016 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

CSc 256 Midterm (green) Fall 2018

CSc 256 Midterm (green) Fall 2018 CSc 256 Midterm (green) Fall 2018 NAME: Problem 1 (5 points): Suppose we are tracing a C/C++ program using a debugger such as gdb. The code showing all function calls looks like this: main() { bat(5);

More information

Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then

More information

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

CENG 3420 Lecture 05: Arithmetic and Logic Unit

CENG 3420 Lecture 05: Arithmetic and Logic Unit CENG 3420 Lecture 05: Arithmetic and Logic Unit Bei Yu byu@cse.cuhk.edu.hk CENG3420 L05.1 Spring 2017 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number

More information

UCB CS61C : Machine Structures

UCB CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 13 Running a Program (Compiling, Assembling, Linking, Loading) Instructor Paul Pearce 2010-07-13 Ok. It won t actually explode. But

More information

Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck!

Question 0. Do not turn this page until you have received the signal to start. (Please fill out the identification section above) Good Luck! CSC B58 Winter 2017 Final Examination Duration 2 hours and 50 minutes Aids allowed: none Last Name: Student Number: UTORid: First Name: Question 0. [1 mark] Read and follow all instructions on this page,

More information

MIPS Assembly Programming

MIPS Assembly Programming COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2

More information

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed.

ECE 2035 Programming HW/SW Systems Fall problems, 6 pages Exam Two 23 October Your Name (please print clearly) Signed. Your Name (please print clearly) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions

More information

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: The MIPS ISA (P&H ) Consulting hours. Milestone #1 (due 1/26)

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: The MIPS ISA (P&H ) Consulting hours. Milestone #1 (due 1/26) Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: The MIPS ISA (P&H 2.1-2.14) 1 Announcements Consulting hours Milestone #1 (due 1/26) Milestone #2 (due 2/2) 2 1 Review: Integer Operations Internal

More information

CS 4200/5200 Computer Architecture I

CS 4200/5200 Computer Architecture I CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational

More information

CENG 3420 Lecture 06: Datapath

CENG 3420 Lecture 06: Datapath CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference

More information

Solutions for Chapter 2 Exercises

Solutions for Chapter 2 Exercises Solutions for Chapter 2 Exercises 1 Solutions for Chapter 2 Exercises 2.2 By lookup using the table in Figure 2.5 on page 62, 7fff fffa hex = 0111 1111 1111 1111 1111 1111 1111 1010 two = 2,147,483,642

More information

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H. Lipasti. University of Wisconsin-Madison. Basics Registers and ALU ops

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H. Lipasti. University of Wisconsin-Madison. Basics Registers and ALU ops ECE/CS 552: Instruction Sets Instructor:Mikko H. Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill. Instructions (354 Review) Instructions are

More information

Project Part A: Single Cycle Processor

Project Part A: Single Cycle Processor Curtis Mayberry Andrew Kies Mark Monat Iowa State University CprE 381 Professor Joseph Zambreno Project Part A: Single Cycle Processor Introduction The second part in the three part MIPS Processor design

More information

Adventures in Assembly Land

Adventures in Assembly Land Adventures in Assembly Land What is an Assembler ASM Directives ASM Syntax Intro to SPIM Simple examples L6 Simulator 1 A Simple Programming Task Add the numbers 0 to 4 10 = 0 + 1 + 2 + 3 + 4 In C : int

More information