Chapter 10 Computer Design Basics

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1 Logic and Computer Design Fundamentals Chapter 10 Computer Design Basics Part 2 A Simple Computer Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode)

2 Overview Part 1 Datapaths Introduction Datapath Example Arithmetic Logic Unit (ALU) Shifter Datapath Representation and Control Word Part 2 A Simple Computer Instruction Set Architecture (ISA) Single-Cycle Hardwired Control PC Function Instruction Decoder Example Instruction Execution Part 3 Multiple Cycle Hardwired Control Single Cycle Computer Issues Sequential Control Design Chapter 10 Part 2 2

3 Instruction Set Architecture (ISA) for Simple Computer (SC) A programmable system uses a sequence of instructions to control its operation An typical instruction specifies: Operation to be performed Operands to use, and Where to place the result, or Which instruction to execute next Instructions are stored in RAM or ROM as a program The addresses for instructions in a computer are provided by a program counter (PC) that can Count up Load a new address based on an instruction and, optionally, status information Chapter 10 Part 2 3

4 Instruction Set Architecture (ISA) (continued) The PC and associated control logic are part of the Control Unit Executing an instruction - activating the necessary sequence of operations specified by the instruction Execution is controlled by the control unit and performed: In the datapath In the control unit In external hardware such as memory or input/output Chapter 10 Part 2 4

5 ISA: Storage Resources The storage resources are "visible" to the programmer at the lowest software level (typically, machine or assembly language) Storage resources for the SC => Separate instruction and data memories imply "Harvard architecture" Done to permit use of single clock cycle per instruction implementation Due to use of "cache" in modern computer architectures, is a fairly realistic model Instruction memory 2 15 x 16 Data memory 2 15 x16 Program counter (PC) Register file 8 x 16 Chapter 10 Part 2 5

6 ISA: Instruction Format A instruction consists of a bit vector The fields of an instruction are subvectors representing specific functions and having specific binary codes defined The format of an instruction defines the subvectors and their function An ISA usually contains multiple formats The SC ISA contains the three formats presented on the next slide Chapter 10 Part 2 6

7 ISA: Instruction Format Opcode Destination register (DR) (a) Register (c) Jump and Branch Source register A (SA) The three formats are: Register, Immediate, and Jump and Branch All formats contain an Opcode field in bits 9 through 15. The Opcode specifies the operation to be performed Source register B (SB) Opcode Destination register (DR) (b) Immediate Source register A (SA) Operand (OP) Opcode Address (AD) (Left) Source register A (SA) Address (AD) (Right) More details on each format are provided on the next three slides Chapter 10 Part 2 7

8 ISA: Instruction Format (continued) Opcode Destination register (DR) Source register A (SA) Source register B (SB) This format supports instructions represented by: R1 R2 + R3 R1 sl R2 (a) Register There are three 3-bit register fields: DR - specifies destination register (R1 in the examples) SA - specifies the A source register (R2 in the first example) SB - specifies the B source register (R3 in the first example and R2 in the second example) Why is R2 in the second example SB instead of SA? The source for the shifter in our datapath to be used in Chapter 10 Part 2 8

9 ISA: Instruction Format (continued) Opcode Destination register (DR) Source register A (SA) Operand (OP) (b) Immediate This format supports instructions described by: R1 R2 + 3 The B Source Register field is replaced by an Operand field OP which specifies a constant. The Operand: 3-bit constant Values from 0 to 7 The constant: Zero-fill (on the left of) the Operand to form 16-bit constant 16-bit representation for values 0 through 7 Chapter 10 Part 2 9

10 ISA: Instruction Format (continued) Opcode Address (AD) (Left) Source register A (SA) Address (AD) (Right) (c) Jump and Branch This instruction supports changes in the sequence of instruction execution by adding an extended, 6-bit, signed 2s-complement address offset to the PC value The 6-bit Address (AD) field replaces the DR and SB fields Example: Suppose that a jump is specified by the Opcode and the PC contains 45 ( ) and Address contains 12 (110100). Then the new PC value will be: ( ) = (45 + ( 12) = 33) The SA field is retained to permit jumps and branches on N or Z based on the contents of Source register A Chapter 10 Part 2 10

11 ISA: Instruction Specifications The specifications provide: The name of the instruction The instruction's opcode A shorthand name for the opcode called a mnemonic A specification for the instruction format A register transfer description of the instruction, and A listing of the status bits that are meaningful during an instruction's execution (not used in the architectures defined in this chapter) Chapter 10 Part 2 11

12 ISA: Instruction Specifications (continued) Instruction Specifications for the SimpleComputer - Part 1 Instruction Opcode Mnemonic Format Description St atus Bits Move A MOVA RD,RA R[DR] R[SA ] N, Z Increment INC RD,RA R[DR] R[SA] + 1 N, Z Add ADD R D,RA,RB R[DR] R[SA ] + R[ SB] N, Z Subtract SUB RD,RA,RB R[DR] R[SA ] R[SB] N, Z Decrement DEC RD,RA R[DR] R[SA ] 1 N, Z AND AND RD,RA,RB R[DR] R[SA ] R[SB ] N, Z OR OR RD,RA,RB R[DR] R[SA] R[SB] N, Z Exclusive OR XOR RD,RA,RB R[DR] R[SA] R[SB] N, Z NO T NO T R D,RA R[DR] R[SA ] N, Z Chapter 10 Part 2 12

13 ISA: Instruction Specifications (continued) Instruction Specifications for the Simple Computer - Part 2 Instr uction Opcode Mnemonic Format Description St atus Bits Move B MOVB RD,RB R[DR] R[SB] Shift Right SHR RD,RB R[DR] sr R[SB] Shift Left SHL RD,RB R[DR] sl R[SB] Load Immediate LDI RD, OP R[DR] zf OP Add Immediate ADI RD,RA,OP R[DR] R[SA] + zf OP Load LD RD,RA R[DR] M[SA] Store ST RA,RB M[SA] R[SB] Branch on Zero BRZ RA,AD if (R[SA] = 0) PC PC + se AD Branch on Negative BRN RA,AD if (R[SA] < 0) PC PC + se AD Jump JMP RA PC R[SA ] Chapter 10 Part 2 13

14 ISA:Example Instructions and Data in Memory Memory Repr esentation of Instructions and Data Deciimal Address Memory Contents Decimal Opcode Other Fields Operation (Subtract) DR:1, SA:2, SB:3 R1 R2 R (Store ) SA:4, SB:5 M[R4] R (Add Immediate) DR: 2, SA:7, OP:3 R2 R (Branch on Zero) AD: 44, SA:6 If R6 = 0, PC PC Data = 192. After execution of instruction in 35, Data = 80. Chapter 10 Part 2 14

15 Single-Cycle Hardwired Control Based on the ISA defined, design a computer architecture to support the ISA The architecture is to fetch and execute each instruction in a single clock cycle The datapath from Figure will be used The control unit will be defined as a part of the design The block diagram is shown on the next slide Chapter 10 Part 2 15

16 V CN Z Branch Control PC IR(8:6) IR(2:0) Extend J L P B B C D A B A A A Address Instruction memory Instruction IR(2:0) Instruction decoder M B F M R M J S D W W L P B B C CONTROL Zero fill RW DA AA Constant in FS V C N Z Bus A D Register file A B A 1 0 MUX B Bus B Function unit F B BA MB Address out Data out MW Data in Address Data memory Data out Data in MD Bus D 01 MUX D DATAPATH Chapter 10 Part 2 16

17 The Control Unit The Data Memory has been attached to the Address Out and Data Out and Data In lines of the Datapath. The MW input to the Data Memory is the Memory Write signal from the Control Unit. For convenience, the Instruction Memory, which is not usually a part of the Control Unit is shown within it. The Instruction Memory address input is provided by the PC and its instruction output feeds the Instruction Decoder. Zero-filled IR(2:0) becomes Constant In Extended IR(8:6) IR(2:0) and Bus A are address inputs to the PC. The PC is controlled by Branch Control logic Chapter 10 Part 2 17

18 PC Function PC function is based on instruction specifications involving jumps and branches taken from Slide 13: Branchon Zero BRZ if (R[SA] =0) PC PC+ se AD Branch on Negative BRN if (R[SA] <0) PC PC+ se AD Jump JMP PC R[SA] In addition to the above register transfers, the PC must also implement: PC PC + 1 The first two transfers above require addition to the PC of: Address Offset = Extended IR(8:6) IR(2:0) The third transfer requires that the PC be loaded with: Jump Address = Bus A = R[SA] The counting function of the PC requires addition to the PC of 1 Chapter 10 Part 2 18

19 PC Function (continued) Branch Control determines the PC transfers based on five of its inputs defined as follows: N,Z negative and zero status bits PL load enable for the PC JB Jump/Branch select: If JB = 1, Jump, else Branch BC Branch Condition select: If BC = 1, branch for N = 1, else branch for Z = 1. The above is summarize by the following table: PC Operation PL JB BC Count Up 0 X X Jump 1 1 X Branch on Negative (else Count Up) Branch on Zero (else Count Up) Sufficient information is provided here to design the PC Chapter 10 Part 2 19

20 Instruction Decoder The combinational instruction decoder converts the instruction into the signals necessary to control all parts of the computer during the single cycle execution The input is the 16-bit Instruction The outputs are control signals: Register file addresses DA, AA, and BA, Function Unit Select FS Multiplexer Select Controls MB and MD, Register file and Data Memory Write Controls RW and MW, and PC Controls PL, JB, and BC The register file outputs are simply pass-through signals: DA = DR, AA = SA, and BA = SB Determination of the remaining signals is more complex. Chapter 10 Part 2 20

21 Instruction Decoder (continued) The remaining control signals do not depend on the addresses, so must be a function of IR(13:9) Formulation requires examining relationships between the outputs and the opcodes given in Slides 12 and 13. Observe that for other than branches and jumps, FS = IR(12:9) This implies that the other control signals should depend as much as possible on IR(15:13) (which actually were assigned with decoding in mind!) To make some sense of this, we divide instructions into types as shown in the table on the next page Chapter 10 Part 2 21

22 Instruction Decoder (continued) Truth Table for Instruction Decoder Logic Instruction Bits Control Wo rd Bits Instruction Function Type MB MD RW MW PL JB BC Function unit operations using registers X X X Memory read X X X Memory write X 0 X X X Function unit operations using register and constant X X X Conditional branch on zero (Z) X X Conditional branch on negative (N) X X Unconditional Jump X X X X Chapter 10 Part 2 22

23 Instruction Decoder (continued) The types are based on the blocks controlled and the seven signals to be generated; types can be divided into two groups: Datapath and Memory Control (First 4 types) PC Control (Last 3 types) In Datapath and Memory Control blocks controlled are considered: Mux B (1st and 4th types) Memory and Mux D (2nd and 3rd types) By assigning codes with no or only one 1 for these, implementation of MB, MD, RW and MW are simplified. In Control Unit more of a bit setting approach was used: Bit 15 = Bit 14 = 1 were assigned to generate PL Bit 13 values were assigned to generate JB. Bit 9 was use as BC which contradicts FS = 0000 needed for branches. To force FS(6) to 0 for branches, Bit 9 into FS(6) is disabled by PL. Also, useful bit correlations between values in the two groups were exploited in assigning the codes. Chapter 10 Part 2 23

24 Instruction Decoder (continued) The end result by use of the types, careful assignment of codes, and use of don't cares, yields very simple logic: Instruction This completes the Opcode DR SA SB design of most of the essential parts of the single-cycle simple computer DA AA BA MB FS MD Control word RW MW PL JB BC Chapter 10 Part 2 24

25 Example Instruction Execution Six Instructions for the Single-Cycle Comp uter Operation code Symbol ic name Format Description Function MB MD RW MW PL JB BC ADI Immediate Add immediate R[ DR] R[ SA] + zf I(2:0) operand LD Register Load memory R [ DR ] M [ R [ SA] ] content into register ST Register Store register M [ R [ SA] ] R[ SB] content in memory SL Register Shift left R[ DR] sl R [ SB] NOT Register Complement register R [ DR] R[ SA] BRZ Jump/Branch If R [SA] = 0, branch If R[SA] = 0, to PC + se AD PC PC + se AD, If R[S A] 0, PC PC + 1 Decoding, control inputs and paths shown for ADI, RD and BRZ on next 6 slides Chapter 10 Part 2 25

26 Decoding for ADI Instruction Opcode DR SA SB DA AA BA 10 MB 9 6 FS 5 MD RW MW PL 1 JB 0 BC Control word Chapter 10 Part 2 26

27 V CN Z Branch Control PC IR(8:6) IR(2:0) Extend Control Inputs and Paths for ADI J L P B B C 0 00 Increment PC D A B A A A Address Instruction memory Instruction Instruction decoder M B Zero fill IR(2:0) F M R M J S D W W L P B B C 0 CONTROL RW DA AA Constant in FS V C N Z Bus A D Register file A B A 1 0 MUX B Bus B + Function unit F B BA MB 1 Address out Data out MW Data in Address Data in 0 Data memory Data out No Write 0 MD Bus D 01 MUX D DATAPATH Chapter 10 Part 2 27

28 Decoding for LD Instruction Opcode DR SA SB DA AA BA 10 MB 9 6 FS 5 MD RW MW PL 1 JB 0 BC Control word Chapter 10 Part 2 28

29 V CN Z Branch Control PC IR(8:6) IR(2:0) Extend Control Inputs and Paths for LD J L P B B C 0 10 Increment PC D A B A A A Address Instruction memory Instruction Instruction decoder M B Zero fill IR(2:0) F M R M J S D W W L P B B C 1 CONTROL RW DA AA Constant in FS V C N Z Bus A D Register file A B A 1 0 MUX B Bus B Function unit F B BA MB 0 Address out Data out MW Data in Address Data in 0 Data memory Data out No Write 1 MD Bus D 01 MUX D DATAPATH Chapter 10 Part 2 29

30 Decoding for BRZ Instruction Opcode DR SA SB DA AA BA 10 MB 9 6 FS 5 MD RW MW PL 1 JB 0 BC Control word Chapter 10 Part 2 30

31 V CN Z Branch Control J L P B B C Branch on Z D A B A A A M B PC Address Instruction memory Instruction Instruction decoder Zero fill IR(2:0) F M R M J S D W W L P B B C 0 CONTROL IR(8:6) IR(2:0) Extend 0 RW DA AA Constant in FS V C N Z Control Inputs and Paths for BRZ Bus A No Write D Register file A B A 1 0 MUX B Bus B Function unit F B BA MB 1 Address out 0 Data out MW Data in Address Data memory Data out No Write Data in 0 MD Bus D 01 MUX D DATAPATH Chapter 10 Part 2 31

32 Terms of Use 2004 by Pearson Education,Inc. All rights reserved. The following terms of use apply in addition to the standard Pearson Education Legal Notice. Permission is given to incorporate these materials into classroom presentations and handouts only to instructors adopting Logic and Computer Design Fundamentals as the course text. Permission is granted to the instructors adopting the book to post these materials on a protected website or protected ftp site in original or modified form. All other website or ftp postings, including those offering the materials for a fee, are prohibited. You may not remove or in any way alter this Terms of Use notice or any trademark, copyright, or other proprietary notice, including the copyright watermark on each slide. Return to Title Page Chapter 10 Part 2 32

Chapter 9 Computer Design Basics

Chapter 9 Computer Design Basics Logic and Computer Design Fundamentals Chapter 9 Computer Design asics Part 2 A Simple Computer Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview