Xuan Guo. Lecture XIV: Review of Chapter 3 & 4. CSC 3210 Computer Organization and Programming Georgia State University. March 5, 2015.

Transcription

1 CSC 3210 Computer Organization and Programming Georgia State University March 5, 2015

2 This lecture Plan for the lecture: Binary Hardware Device Converting from Decimal to other number system Converting from any number system to Decimal Bitwise logical operation Synthetic Instructions Flags Half and Full Adders & Modulus Arithmetic Addition Two s Complement Number Subtraction Shift Unsigned Arithmetic Four condition codes Signed and Unsigned Number Branching Conditions Extended Precision Arithmetic

3 Binary A computer is a bistable device A bistable device: Easy to design and build Has 2 states: 0 and 1 One Binary digit (bit) represents 2 possible states (0, 1)

4 A subscript indicates the number s base E.g. is 100 decimal or binary? We don t know! But = is clear It is difficult for a human to work with long strings of 0 s and 1 s Octal: base 8 Hexadecimal: base 16

5 Binary to Hexadecimal =? in hex Group into 4 bits, from the right: 0101, 0110, 1011, Now translate each (see previous table): => 5, => 6, => b, => 3 So this is 56b3 16 What if there are not enough bits? Pad with 0 s on the left

6 Hexadecimal to Binary f0e5 16 =? in binary Translate each into a group of 4 bits: f 16 => , 0 16 => , e 16 => , 5 16 => So this is

7 Decimal to Any Number Base Take the decimal number, and divide by the new number base Keep track of the quotient and remainder Repeat until quotient = 0 Read number from the bottom to the top

8 Decimal to Binary Binary is base 2 Example: convert 35 (decimal) to binary Quotient Remainder 35 / 2 = / 2 = / 2 = / 2 = / 2 = / 2 = 0 1 So =

9 Any Number Base to Decimal From right to left, multiply the digit of the number-to-convert by its base position Sum all results

10 Binary to Decimal Binary is base 2 Example: convert (binary) to decimal = 1x x x x x2 0 = 1x16 + 0x8 + 1x4 + 1x2 + 0x1 = = 22 So = 22 10

11 In C program and Assembly language Hexadecimal designated by a leading 0x Octal designated by a leading 0 Example mov 0xa, %l0 mov 012, %l1 mov 10, %l2

12 Bitwise Logical Operations There are several binary operations: NOT AND OR XOR NAND NOR

13 SPARC Instruction Format These commands are in the form: command reg rs1, reg_or_imm, reg rd command can be any of the following: and, andn, xor, or, xnor, orn andcc, andncc, xorcc, orcc, xnorcc, orncc the cc means set condition codes andn means a and (not b) orn means a or (not b) not reg rs1, reg rd not reg rd recognized as xnor reg rs1, %g0, reg rd xnor reg rd, %g0, reg rd

14 A Few More Logic Examples (Bonus) In all the examples below, these registers have the following initial values: %l0 = 0x %l1 = 0x9abcdef0 What are the values for %l1 after the instruction? and %l0, %l1, %l1 xor %l0, %l1, %l or %l0, %l1, %l1 9abcdef8 not %l0, %l1 edcba987

15 A Few More Logic Examples (Bonus) %l0 = 0x (0001,0010,0011,0100,0101,0110,0111,1000) 2 %l1 = 0x9abcdef0 (1001,1010,1011,1100,1101,1110,1111,0000) 2 What are the values for %l1 after the instruction? and %l0, %l1, %l1 xor %l0, %l1, %l1 0x = (0001,0010,0011,0100,0101,0110,0111,0000) = (1000,1000,1000,1000,1000,1000,1000,1000) 2 or %l0, %l1, %l1 0x9abcdef8 = (1001,1010,1011,1100,1101,1110,1111,1000) 2 not %l0, %l1 0xedcba987 = (1110,1101,1100,1011,1010,1001,1000,0111) 2

16 Synthetic Instructions The cmp command is a synthetic one. It is a macro that uses %g0. cmp reg rs1, reg_or_imm command will be expanded to: subcc reg rs1, reg_or_imm, %g0 the tst command compares a register to 0: tst reg rs1 which the assembler turns into: orcc reg rs1, %g0, %g0 Since %g0 ignores any updates, only the condition codes are affected.

17 Flags & Testing Flags A word may contain 32 flags. Common flag operations and mnemonics set: bset ( done with or ) clear: bclr ( done with andn ) toggle: btog ( done with xor ) bset/bclr/btog reg_or_imm, reg rd This command will see if one or more flags is set btst reg_or_imm, reg rs1 it expands to: andcc reg rs1, reg_or_imm, %g0 example: test if flag 0x02 is set btst 0x02, %a_r be clear nop set: clear:

18 Binary Sums and Carries a b Sum a b Carry XOR AND

19 Half Adder / Full Adder A half adder For adding 2 bits Gives carry out and sum 1 AND and 1 XOR gate A full adder For adding 2 bits plus a carry in Gives carry out and sum 2 ANDs, 2 XORs, and 1 OR

20 Modulus Arithmetic It considers only numbers in the range 0 <= n <=M, where M is the modulus. SPARC has 32-bit registers, M = 2 32 Each register can store an integer number between 0 and 2 n -1 where n=32 for SPARC if you have a value of 2 n -1 in a register, and you add 1 to this, the register will then hold a value of 0

21 Complement Arithmetic r n -1-b+1 is called the radix complement ten s complement if r=10 two s complement if r=2 r n -1-b is called the diminished radix complement nine s complement if r=10 one s complement if r=2 Any number where the most significant digit >= (r/2) is considered negative means 128 when r=2, n=8 84 means 16 when r=10, n=2

22 Two s Complement In binary, finding the one s complement and the two s complement are easy One s complement: Replace every 0 with a 1, and replace every 1 with a 0 Two s complement: Find the one s complement, and add 1

23 Two s Complement Example What is 16 (decimal) in binary (r=2)? We ll assume n=8 16 = in binary one s complement add two s complement

24 Addition and Subtraction The two s complement system is an interpretation of numbers in registers; the hardware always performs binary addition. To subtract, find the 2 s complement of the 2 nd operand, and add There is no need for a hardware subtractor

25 Shift Instructions A registers contents can be shifted left shift is like multiplying by 2 right shift is like dividing by 2 Shift right logical (srl) 0 Shift right arithmetic (sra) Shift left logical (sll) 0 Shift left arithmetic is not provided, it would be the same as shift left logical

26 Shift Instructions Shift right logical (srl) srl reg rs1, reg_or_imm, reg rd Shift right arithmetic (sra) sra reg rs1, reg_or_imm, reg rd Shift left logical (sll) sll reg rs1, reg_or_imm, reg rd The number of shifts is the low 5 bits of the reg_or_imm, so largest shift is 31

27 Branching Conditions Branching is based on the following flags: N (negative) the most significant bit of the result not used with unsigned numbers V (overflow) when result is too big for the register Z (zero) set when all bits of the result are 0 C (carry) set when an addition has carry out, or when subtraction does not have carry out

28 Signed Branches Assembler Signed Arithmetic Mnemonic Branches Condition Codes bl branch on less (N xor V) = 1 ble branch on less or equal Z or (N xor V) = 1 be branch on equal Z = 1 bne branch on not equal Z = 0 bge branch on greater or equal (N xor V) = 0 bg branch on greater Z or (N xor V) = 0

29 Unsigned Branches The carry flag (C) can be used instead of the overflow flag (V) Assembler Unsigned Arithmetic Mnemonic Branches Condition Codes blu branch on less C = 1 bleu branch on less or equal Z or C = 1 be branch on equal Z = 1 (same as signed branch) bne branch on not equal Z = 0 (same as signed branch) bgeu branch on greater or equal C = 0 bgu branch on greater Z = 0 and C = 0

30 Condition Code Branches Assembler Condition Code Mnemonic Branches Condition Codes bneg branch on negative N = 1 bpos branch on positive N = 0 bz branch on zero set Z = 1 (same as be) bnz branch on zero not set Z = 0 (same as bne) bvs branch on overflow set V = 0 bvc branch on overflow clear V = 1 bcs branch on carry set C = 1 (same as blu) bcc branch on carry clear C = 0 (same as bgeu)

31 Numeric Labels The assembler allows single-digit labels to appear many times in a single source file. [page 137] 1: addcc %lo_r, %lo_r, %lo_r bcc 1f! find label 1 forward add %hi_r, %hi_r, %hi_r bset 1, %hi_r The letter b or f must be appended to the digit, for backward or forward direction. The closest label in that direction will be the branch target, if the branch is taken. These are good for labels used in control structures.

32 Extended Precision What if we need to work with data that are more than 32 bits wide? We can use extended precision instructions, with the carry addx reg rs1, reg_or_imm, reg rd addxcc reg rs1, reg_or_imm, reg rd these mean: reg rd = reg rs1 + reg_or_imm + C

33 Extended Precision (Sub) We can use extended precision instructions, with the carry subx reg rs1, reg_or_imm, reg rd subxcc reg rs1, reg_or_imm, reg rd these mean: reg rd = reg rs1 - reg_or_imm - C Data larger than 32 bits must be stored in 2 (or more) registers. That is, add (or sub) the low part first, then use the extended precision addx (or subx) for the high part. This is just like doing arithmetic on paper, where we work with one digit at a time.

34 Extended Precision example Given a number A spans over registers %l1 to %l2 and a number B spans over registers %o1 to %o2. Write an assembly code segment to perform A = A - B [A = %l1%l2, B = %o1%o2] ABCDEFABCDEFABCD - BCDEFBCDEFBCDEFB = EEEEF3DDDE32CCD2 subcc %l2, %o2, %l2! sub bits 0 to 31 subx %l1, %o1, %l1! sub bits 32 to 63 and C