Exceptions, MIPS-Style

Transcription

1 Exceptions, MIPS-Style Reminder: MIPS CPU deals with exceptions. Interrupts are just a special case of exceptions. The MIPS Architecture has no interrupt-vector table! All exceptions trigger a jump to the same location, demultiplexing happens in the exception hler, after looking up the reason for the exception in the CAUSE register. exception exception hler specific service routine Exception Hling MIPS-Style (I): Data Structures /* /* DATA STRUCTURES /* typedef enum {Int = 0, Mod = 1, TLBL = 2, TLBS = 3, AdEL = 4, AdES = 5, IBE = 6, DBE = 7, Syscall = 8, Bp = 9, RI = 10, CpU = 11, Ov = 12, TRAP = 13, VCEI = 14, FPE = 15, C2E = 16, Watch = 23, VCED = 31 EXCEPTION_CODE; typedef unsigned int reg_t; typedef struct xcptcontext { /* This is the exception context frame that is passed to the exception hlers. It gets filled in by the low-level exception hler in "machine.s". An assembler version of this structure can be found at the bottom of "machine.h". reg_t ; /* Status Register reg_t cr; /* Cause Register reg_t epc; /* PC at time of exception. reg_t vaddr; reg_t regs[32]; /* Copy of all general purpose registers reg_t mdlo; /* HI/LO registers (used for memory management) reg_t mdhi; reg_t count; /* Timer registers reg_t compare; struct xcptcontext * prev; /* To link exceptions. (unused for now) unsigned xcss; /* Priority css of this exception. (unused for now). EXCEPTION_CONTEXT; 1

2 Exception Hling MIPS-Style (II): Set-up Frame LEAF().set noreorder.set noat /* Note: exceptions do not save k0 k1. * on entry, k1 = exception css. /* save exception css in memory k0, css sw k1, 0(k0) # had better not trap! move k0, zero # now boot exception will abort. /* allocate excepti frame (on 8-byte boundary) subu k1, sp, XCP_SIZE l k1, 3 /* shift right/left -> alligned on boundary sll k1, 3 Exception Hling MIPS-Style (III): Save Registers /* AT, XCP_AT(k1) v0, XCP_V0(k1) v1, XCP_V1(k1) a0, XCP_A0(k1) a1, XCP_A1(k1) a2, XCP_A2(k1) a3, XCP_A3(k1) sp, XCP_SP(k1) ra, XCP_RA(k1) /* get coprocessor 0 exception state mfc0 a0, CPU0_CR mfc0 a1, CPU0_SR mfc0 a2, CPU0_VADDR mfc0 a3, CPU0_EPC /* we can safely use AT now.set at /* switch to using sp to point at exception frame move sp, k1 /* we skip saving of watchpoint registers /* stash exception css lw v0, css /* nothing sensible to store for k0/k1, store zero zero, XCP_K0(sp) zero, XCP_K1(sp) 2

3 Exception Hling MIPS-Style (IV): Save More Registers /* we have finished with the uninterruptible code. * (using k0/k1, saving exception state), so * we can permit nested exceptions ; however, we cannot * permit device interrupts until the interrupt hler * does its prioritization sets SR_IMASK. k0, # restore rom boot exception hook v0, a1, ~(SR_IMASK SR_EXL SR_KSU_MASK) mtc0 v0, CPU0_SR.set reorder /* we are now interruptible: dump all remaining state * into the excepti frame. /* coprocessor exception state a0, XCP_CR(sp) a1, XCP_SR(sp) a2, XCP_VADDR(sp) a3, XCP_EPC(sp) /* timer data mfc0 a0, CPU0_COUNT mfc0 a1, CPU0_COMPARE a0, XCP_COUNT(sp) a1, XCP_COMPARE(sp) /* mdhi mdlo mfhi v0 mflo v1 v0, XCP_MDHI(sp) v1, XCP_MDLO(sp) Exception Hling MIPS-Style (V) /* Save all the other general registers. * We save zero, s0-s7 s8 as well, as instruction emutors (e.g. FP * operations) debuggers rely on all registers stored together in * well-defined structure. zero, XCP_ZERO(sp) t0, XCP_T0(sp) t7, XCP_T7(sp) s0, XCP_S0(sp) s7, XCP_S7(sp) t8, XCP_T8(sp) t9, XCP_T9(sp) gp, XCP_GP(sp) s8, XCP_S8(sp) /* I don't know what the following does. [rb] /* load our _gp pointer gp, _gp 3

4 Exception Hling MIPS-Style (VI) /* call the C exception hler move a0, sp # arg1 = &xcp subu sp, 16 # (arg save area) move ra, zero # fake return address b _xcptcall /* This strange call to _xcptcall with zero return address is to * help exception-aware debuggers to trace back over the exception event. * We are basically interposing a bogus stackframe (with a zero return * address) between the C exception hler the actual machine * exception. xcptrest:.set noat add AT, sp, 16 /* at points to exception frame LEAF(_xcptcall) /* on entry: a0 == &xcp subu sp, 24 ra, 16(sp) /* punt out to _xcpt_deliver jal _xcpt_deliver ra, 16(sp) addu sp, 24 beqz ra, xcptrest j ra END(_xcptcall) /* This function gets called by the low-level exception hler. ::dispatch(_xcp); /* end of _xcpt_deliver Exception Hling MIPS-Style (VII): Restore Registers xcptrestother: /* restore all state /* restore most general registers t0, XCP_T0(AT) t7, XCP_T7(AT) s0, XCP_S0(AT) s7, XCP_S7(AT) t8, XCP_T8(AT) t9, XCP_T9(AT) gp, XCP_GP(AT) s8, XCP_S8(AT) /* mdhi mdlo v0, XCP_MDHI(AT) v1, XCP_MDLO(AT) mthi v0 mtlo v1 /* remaining general registers a0, XCP_A0(AT) a1, XCP_A1(AT) a2, XCP_A2(AT) a3, XCP_A3(AT) ra, XCP_RA(AT) /* restore the exception-time status register, which has the * side effect of disabling interrupts..set noreorder v0, XCP_SR(AT) 4

5 Exception Hling MIPS-Style (VIII): Return /* in the following we do some magic address pipeline effects when updating the control register. #clear SR_IMASK before setting SR_EXL (nasty window) li v1, ~(SR_IMASK SR_EXL) v1, v0 mtc0 v1, CPU0_SR or v0, SR_EXL v1, XCP_V1(AT) mtc0 v0, CPU0_SR v0, XCP_V0(AT) sp, XCP_SP(AT) /* we are not uninterruptible can use k1 safely k1, XCP_EPC(AT) AT, XCP_AT(AT) mtc0 k1, CPU0_EPC eret.set reorder.set at END() Initialize MIPS Low-Level Exception Hler /* Macro to copy exception hler to unchached low memory #define XCPTCOPY(offs, start, end) \ li t0, KSEG1_BASE+offs ; \ t1, start ; \ t2, end ; \ 1: lw t3, 0(t1) ; \ addu t1, 4 ; \ sw t3, 0(t0) ; \ addu t0, 4 ; \ bne t1, t2, 1b LEAF(_xcptlow_init) /* disable all interrupts mfc0 t4, CPU0_SR t4, ~SR_IE mtc0 t4, CPU0_SR _xcptlowstart: j _xcptlowend:.text.set noat.set noreorder.set reorder.set at k1, k1 XCPTCOPY(0x180, _xcptlowstart, _xcptlowend) lw beqz t0, _ram_based t0, 1f /* using RAM-based hlers, so switch off boot exceptions t4, ~SR_BEV mtc0 t4, CPU0_SR 1: k0, j ra END(_xcptlow_init) 5

6 High-Level Exception Hling /* This function gets called by the low-level exception hler. ::dispatch(_xcp); /* end of _xcpt_deliver Default Memory InterruptDispatcher Default Clock High-Level Exception Hling /* This function gets called by the low-level exception hler. ::dispatch(_xcp); /* end of _xcpt_deliver int ::dispatch(exception_context * _xcp) { /* -- RETRIEVE EXCEPTION CODE int xcp_code; xcp_code = (_xcp->cr & CR_EXCCODE) >> 2; Default Console::putstr("EXCEPTION DISPATCHER: xcp_code = "); Console::putint((int)xcp_code); Console::putstr("\n"); Memory assert(xcp_code >= InterruptDispatcher 0 && xcp_code < EXCEPTION_TABLE_SIZE); /* -- HAS A HANDLER BEEN REGISTERED FOR THIS CODE? * hler = hler_table[xcp_code]; /* -- IF SO, CALL THE HANDLER; OTHERWISE, CALL DEFAULT HANDLER. if (hler) { hler->hle_exception(_xcp); else { Default Clock /* --- NO DEFAULT HANDLER HAS BEEN REGISTERED. SIMPLY RETURN AN ERROR. Console::putstr("NO DEFAULT EXCEPTION HANDLER REGISTERED\n"); return -1; 6

7 High-Level Exception Hling int InterruptDispatcher::hle_exception(EXCEPTION_CONTEXT * _xcp) { /* This function gets called by the low-level exception hler. /* -- THE EXCEPTION IS IN RESPONSE TO AN INTERRUPT. ::dispatch(_xcp); /* --- DETERMINE THE PENDING INTERRUPTS /* end of _xcpt_deliver int interrupt_no = (_xcp->cr & CR_IP) >> 8; Console::putstr("InterruptDispatcher::hle_exception : interrupt_stat = "); Console::putint(interrupt_no); Console::putstr("\n"); /* --- DISPATCH THE INTERRUPT WITH THE HIGHEST NUMBER for (int i = 7 + MAX_INTERRUPTS; i > 7; i--) { if (_xcp->cr & (1 << i)) { Console::putstr("Interrupt No "); Console::putint(i-8); Console::putstr(" set.\n"); * interrupt_hler = interrupt_dispatch_table[i-8]; Default if (interrupt_hler) Memory { InterruptDispatcher Console::putstr("calling IDT->hle\n"); interrupt_hler->hle_exception(_xcp); else { if (default_interrupt_hler) { default_interrupt_hler->hle_exception(_xcp); else { /* ---- THERE IS NO HANDLER FOR THIS Default INTERRUPT Console::putstr("UNCAUGHT INTERRUPT\n"); /* InterruptDispatcher::hle_exception Clock 7