Introduction to VHDL

Size: px

Start display at page:

Download "Introduction to VHDL"

Winfred Milo Robinson
6 years ago
Views:

1 Introduction to VHDL

2 Agenda Introduce VHDL Basic VHDL constructs Implementing circuit functions Logic, Muxes Clocked Circuits Counters, Shifters State Machines FPGA design and implementation issues FPGA resource utilization Implementation constraints 2

3 Section 1 Introduction What is VHDL? VHDL Design Flow Basic VHDL constructs Entity/ Architecture Logical operators Using Tools to synthesize VHDL 3

4 Introducing VHDL VHDL was designed ed under the VHSIC program by the Department of Defense VHDL acronym stands for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language 4

5 What is VHDL? VHDL is a language used to describe systems s It can be used to design and simulate digital circuits VHDL was adopted by IEEE in 1987 as a standard IEEE Most Common version VHDL 93 Most recent version VHDL 2008 STD_LOGIC Libraries are covered by IEEE 1164 Simulation enhancements covered in VITAL 5

6 Why VHDL? Capable of more complex designs s than schematics cs Not bound to a vendor Supports design abstraction It is a standard Supports design reuse The DOD requires it 6

7 Synthesis vs. Simulation Simulatable VHDL Synthesizable 7

8 VHDL Design Flow Specify Design Write VHDL Code Simulate VHDL Synthesize Design Implement design Feed Back to any up stream point. Verify Timing Done 8

9 Building Blocks The Entity / Architecture e pair The basis of all VHDL designs Entities can have more then one Architecture Architectures can have only one entity Entities define the interface (i.e. I/Os) for the design Architectures define the function of the design 9

10 The Entity Details entity entity_name is generic (generic_list); port (port_list); end entity_ name; 10

11 The Entity Details D Q clk DFLOP = entity DFLOP is Port ( D : in std_ logic; clk : in std_logic; Q : out std_logic ); end DFLOP; (Port_names : MODE type); MODE types: in, out, inout or buffer 11

12 The Architecture Details architecture architecture_name of entity_name is declaration section begin concurrent statements end architecture_name; Declaration section Signals, constants and components local to the architecture can be declared here Concurrent statements t t Where the circuit is defined 12

13 Logical Operators VHDL predefines the logic operators NOT HIGHER PRECEDENCE AND NAND There is no implied precedence OR for these operators. If there are NOR two or more different operators in an equation, the order of XOR precedence is from left to right XNOR Note: XNOR supported in standard

14 Comments -- (Double minus sign) is the comment mark All text after the -- on the same line is taken as a comment Comments only work on a single line There is no block comment in VHDL 93 (Availible in 2008 /* */ 14

15 Example Entity/Architecture -- Example of two input AND gate library IEEE; use IEEE.std_logic_1164.all; entity and2vhdl is port ( In_ a : in std_ logic; In_b : in std_logic; Out_c : out std_logic ); end and2vhdl; architecture Behavioral of and2vhdl is begin Out_c <= In_a and In_b; -- Note <= in this context is the -- Signal assignment operator end Behavioral; 15

16 Lab WorkShop

17 Section 2 Data Types & Statements Data types Predefined types, additional types & Arrays Concurrent and sequential statements Relational operators More VHDL constructs Process IF WHEN CASE SELECT Lab 2 - Implementing a Multiplexer 17

18 Data Types DATA types: An ordered set of possible values define a particular type Example: Type character is the ISO character set VHDL is a strongly typed language All variables must be assigned a type Type conversion functions are supplied in add on functions but are not part of the core of VHDL 18

19 Predefined Types Boolean FALSE, TRUE Bit ( 0, 1 ) bit_vector( vector( ) --Notice Double quotes for the group Integers: range -(2^31-1) to 2^31-1 Floating real: -1.E38 to 1.0E38 Time Character String Enumerated (User defined) Records, file & access types (Used in Simulation only) 19

20 Std_logic & std_ulogic Not part of 1076 Part of 1164 library Std_logic is a resolved type Std_logic is a subtype of std_ulogic Std_ulogic Values: TYPE std_ulogic IS ('U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); Note case is important, upper case for U,X,Z,W,L,H 20

21 Resolution of Multiple Drivers Z Output=? 1 In the case of STD_ULOGIC the output of this circuit is undefined A method of resolving multiple drivers is needed 21

22 Std_logic Resolution Function Unlike std_ulogic, std_logic can resolve multiple drivers on a signal resolution function CONSTANT resolution_table : stdlogic_table := ( U X 0 1 Z W L H ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- U ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- X ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- 0 ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- 1 ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- Z ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- W ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- L ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- H ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- - ); 22

23 Standard Logic Vectors STD_LOGIC_VETOR de facto standard from Synopsis std_ logic _ vector & std_ ulogic _ vector A collection of std_logic or std_ulogic Defined in the packages STD_LOGIC_ARITH with either STD_LOGIC_UNSIGNED or STD_LOGIC_SIGNED. Ordered set of signals library IEEE; use IEEE.std_logic_1164.all; use IEEE. entity busses is port ( In_bus1, In_bus2 : in std_logic_vector t (7 downto 0); In_bus3 : in std_logic_vector (0 to 7); Out_bus : out std_logic_vector (7 downto 0) ); end busses; 23

24 Vector Properties Vectors are filled from left to right, always Indexes are assigned ascending or descending depending on the key word to or downto In_bus1, In_bus2 : in std_logic_vector (7 downto 0); In_bus3 : in std_logic_vector (0 to 7); Out_bus : out std_logic_vector (7 downto 0) In_bus1 <= ; -- IN_BUS1(7)= 1, IN_BUS1(0) = 0 In_bus2(3) < = 1 ; -- IN_BUS2 = (U,U,U,U,1,U,U,U,) In_bus2(6 downto 4) < = 101 ; -- IN_BUS2 = (U101UUUU) (U,1,0,1,U,U,U,U,) In_bus3 <= ; -- IN_BUS3(7)= 0, IN_BUS3(0) = 1 24

25 Array Ordering Bus1 : std_logic_vector ( 3 downto 0); Bus2 : std_logic_vector ( 0 to 3); Bus1 <= Bus2; Bus1(3) Bus1(2) Bus1(1) Bus1(0) Bus2(0) Bus2(1) Bus2(2) Bus2(3) 25

26 Aggregates signal X_bus, Y_bus, Z_bus : std_logic_vector (3 downto 0); signal Byte_bus : std_logic_vector (7 downto 0); Aggregates: Special array operation can be used to fill a std_logic_vector in sections Byte_bus <= ( 7 => 1, 6 downto 4 => 0, others => 1 ); -- Byte_bus = Others refers to all the values of the array not yet mentioned Aggregates can be used to set all members of a std_logic vector to a particular value without knowing the width of the std_ logic _ vector Z_bus <= (others=> 0 ); 26

27 Concatenation Concatenation (&) is used to gather pieces of an array to construct a bigger array signal x_bus, y_bus, z_bus : std_logic_vector (3 downto 0); signal byte_bus : std_logic_vector (7 downto 0); signal a,b,c,d : std_logic; Building a larger std_ logic _ vector from small vectors Byte_bus <= x_bus & y_bus; -- Concatenation operator & Building a std_logic_vector t from std_logic z_bus <= a&c&b&d; Note: the total width of the right hand side must be equal to the width of the left hand side 27

28 Concurrent Statements Exist inside the Architechture e Concurrent statements are Order independent!!! 28

29 Concurrent Statement Example A B C D X Y Z Z<=X or Y; X<=A and B; Y<=C and D; = Y<=C and D; X<=A and B; Z<=X or Y; 29

30 Relational Operators Used for comparison = Equals /= Not equal < Ordering, less than <= Ordering, less than or equal > Ordering, greater than >= Ordering, greater than or equals 30

31 Process and Sequential Statements Processes exist inside the Architecture Processes have local variables Processes contain Sequential Statements Processes have a sensitivity list or an optional wait statement Processes execute only when a signal in the sensitivity list changes Processes can be used to make clocked circuits 31

32 The Process Framework Lbl Label:-- optional label l process (optional sensitivity list) -- local lprocess declarations begin -- sequential statements t t -- optional wait statements end process; Processes must have a sensitivity list or a wait statement, but never both 32

33 If Statements Can have aeoeapp overlapping gcod conditions os Imply priority, first true condition is always taken Can have incomplete condition lists Useful to control signal assignments 33

34 Sequential If Statement Used inside the Process Can be used to control variable and signal assignments Has optional elsif structure 34

35 The If Framework Sequential Version if <condition> then sequential _ statements elsif <condition> then sequential_statements else sequential_statements end dif; 35

36 Example Multiplexer MUX_IN1 MUX_IN2 MUX_IN3 MUX_IN4 MUX_OUT SEL(1:0) 36

37 Sequential If Example library IEEE; use IEEE.std_logic_1164.all; entity MUX is port ( MUX_IN1, MUX_IN2, MUX_IN3, MUX_IN4 : in std_logic; SEL : in std_logic_vector (1 downto 0); MUX_OUT : out std_logic); end MUX; architecture IF_MUX_arch of MUX is begin process (SEL, MUX_IN1, MUX_IN2, MUX_IN3, MUX_IN4) begin if SEL = "00" then MUX_OUT <= MUX_IN1; elsif SEL = "01" then MUX_OUT <= MUX_IN2; elsif SEL = "10" then MUX_OUT <= MUX_IN3; else MUX_OUT <= MUX_IN4; end if; end process; end IF_MUX_arch; 37

38 What Goes Into the Sensitivity List If a change on an input signal causes an IMMEDIATE change in any signal that is assigned in that process then it should be in the sensitivity list If there is no IMMEDIATE change in a signal assigned in the process based on the change of a particular input signal, then that input signal should NOT be in the sensitivity list 38

39 When Statement The concurrent version of the IF statement LABEL1: -- optional label SIG_NAME <= <expression> when <condition> else <expression> when <condition> else <expression>; 39

40 When Example library IEEE; use IEEE.std_logic_1164.all; entity MUX is port ( MUX_IN1,MUX_IN2 IN2 : in std_logic; dl MUX_IN3,MUX_IN4 : in std_logic; SEL : in std_logic_vector(1 downto 0); MUX_OUT : out std_logic ); end MUX; architecture WHEN_MUX_arch of MUX is begin MUX_OUT <= MUX_IN1 when SEL="00" else MUX_IN2 when SEL="01" else MUX_IN3 when SEL="10" else MUX _ IN4; end WHEN_MUX_arch; 40

41 The Case Statement Used to control o signal assignments s No priority implied Control expression must cover all possible signal assignments No conditions may overlap 41

42 Sequential Case Statement Must be inside a process case <expression> is when <choices> hi => <statements> when <choices> => <statements> when others => <statements> end case; 42

43 Case Example architecture CASE_MUX_arch of MUX is begin process (MUX_IN1, MUX_IN2, MUX_IN3, MUX_IN4, SEL) begin case sel is when "00" => MUX_OUT <= MUX_IN1; when "01" => MUX_ OUT <= MUX_ IN2; when "10" => MUX_OUT <= MUX_IN3; when others => MUX_OUT <= MUX_IN4; end case; end process; end dcase _ MUX _ arch; c; 43

44 Select the Concurrent Case Statement LABEL1: -- optional label with <choice_expression> expression> select SIG_NAME <= <expression> when <choices>, <expression> when <choices>, <expression> when others; 44

45 Select Example library IEEE; use IEEE.std_logic_1164.all; entity MUX is port ( MUX _ IN1,MUX _ IN2 : in std sd_ logic; MUX_IN3,MUX_IN4 : in std_logic; SEL : in std_logic_vector(1 downto 0); MUX_ OUT : out std_ logic ); end MUX; architecture SEL_MUX_arch of MUX is begin with SEL select MUX_OUT <= MUX_IN1 when "00", MUX_IN2 when "01", MUX_IN3 when "10", MUX_IN4 when others; end SEL_MUX_arch; 45

46 Importance of the Process Sensitivity process(s,a) begin if S= 1 then OUTS<=A; else OUTS<=not A; end if; end process; process(s) begin if S= 1 then OUTS<=A; else OUTS<=not A; end if; end process; The second process must remember the last value of A based on a change in S. Assuming the synthesis tool accepts it, the Synthesizer will infer a latch. 46

47 Thank You & Happy Coding

310/ ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006

310/ ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006 310/1780-10 ICTP-INFN Advanced Tranining Course on FPGA and VHDL for Hardware Simulation and Synthesis 27 November - 22 December 2006 VHDL & FPGA - Session 2 Nizar ABDALLH ACTEL Corp. 2061 Stierlin Court