Chapter 2 Lecture 1 Computer Systems Organization
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1 Chapter 2 Lecture 1 Computer Systems Organization This chapter provides an introduction to the components Processors: Primary Memory: Secondary Memory: Input/Output: Busses The Central Processing Unit (CPU), instruction execution, RISC and CISC, Instruction-level and Processor-level Parallelism Bits, Bytes, Address, ECC, caches, etc. Memory Hierarchy, Hard Disks, Floppy, RAID, CD, DVD Buses, Terminals, Printers, Modems, ASCII Interconnecting computer components requires wires. When multiple devices share the same wires, we have the concept of a bus. Busses an interconnections occur at all levels of a machine and are critical for computer operation. A simple block diagram is 1 of 21 ECE 3570
2 A bus oriented Personal Computer (1980 s) Architecture. A single bus architecture with various input/output (I/O) components. Processors: Primary Memory: Secondary Memory: Input/Output: CPU (8088 or generation?) Memory, ICs Hard Disks, Floppy, Terminal, Keyboard 2 of 21 ECE 3570
3 2.1 Processors What is inside the CPU? V. Heuring and H. Jordan, Computer Design and Architecture, Addison Wesley Longman, Menlo Park, CA ISBN: X. PC: IR: ALU: Register File: Internal Busses: External Interfaces: Program Counter holds the address of the instruction Instruction Register holds the instruction Arithmetic Logic Unit executes operations on operands Operand storage for high speed (available now) memory Move instructions and data within the processor Access to external instructions, memory, and peripherals When performing processor design, there is significant focus placed on the Data Path design. 3 of 21 ECE 3570
4 A significant factor on processor speed or execution rate is the data path and a data path cycle. Instruction Execution There are many short-hand ways to define the execution of an instruction: Fetch-Decode-Execute Fetch: Decode: Execute: [Write-Back: Fetch the instruction for execution Decode the instruction and prepare for execution Access the operands required for execution Execute the instruction and store the results Store the result of the execution] 4 of 21 ECE 3570
5 An alternate sequence can be defined as (used later to define pipeling) Instruction Execution in detail: 1) Fetch the instruction from memory into the instruction register 2) Change the program counter to point to the next instruction 3) Determine the type of instruction that was fetched 4) If the instruction requires operands from memory, determine the location 5) Fetch the operands from memory, if required 6) Execute the instruction 7) Store the result. (If in memory, determine the location and store) Repeat: How are the 7 steps accomplished using the SRC core V. Heuring and H. Jordan, Computer Design and Architecture, Addison Wesley Longman, Menlo Park, CA ISBN: X. 5 of 21 ECE 3570
6 Von Neumann based Instruction Unit and/or Control Unit Program Counter Memory Unit Instruction Register Input/Output Unit Execution Unit Instruction Execution in detail: (F-Fetch, D-Decode, E-Execute, WB-writeback) 1.F) Fetch the instruction from memory into the instruction register 2.F) Change the program counter to point to the next instruction 3.F/D) Determine the type of instruction that was fetched 4.D) If the instruction requires operands from memory or I/O, determine the location 5.D) Fetch the operands from memory, if required 6.E) Execute the instruction 7.WB) Store the result. (If in memory or I/O, determine the location and store) 6 of 21 ECE 3570
7 Harvard Architecture Base Instruction Unit and/or Control Unit Program Counter Instruction Memory Unit Instruction Register Data Memory Unit Execution Unit Input/Output Unit Instruction Execution in detail: (F-Fetch, D-Decode, E-Execute, WB-writeback) 1.F) Fetch the instruction from memory into the instruction register 2.F) Change the program counter to point to the next instruction 3.F/D) Determine the type of instruction that was fetched 4.D) If the instruction requires operands from memory or I/O, determine the location 5.D) Fetch the operands from memory, if required 6.E) Execute the instruction 7.WB) Store the result. (If in memory or I/O, determine the location and store) Which one is faster? 7 of 21 ECE 3570
8 Virtual Machine Instruction Execution Using an instruction interpreter (written in JAVA) public class Interp { static int PC; // program counter holds address of next instr static int AC; // the accumulator, a register for doing arithmetic static int instr; // a holding register for the current instruction static int instr_type; // the instruction type (opcode) static int data_loc; // the address of the data, or -1 if none static int data; // holds the current operand static boolean run_bit = true; // a bit that can be turned off to halt the machine public static void interpret(int memory[ ], int starting_address) { // This procedure interprets programs for a simple machine with instructions having // one memory operand. The machine has a register AC (accumulator), used for // arithmetic. The ADD instruction adds am integer in memory to the AC, for example // The interpreter keeps running until run bit is turned off by the HALT instruction. // The state of a process running on this machine consists of the memory, the // program counter, the run bit, and the AC. The input parameters consist of // of the memory image and the starting address. } PC = starting_address; while (run_bit) { instr = memory[pc]; // fetch next instruction into instr (1) PC = PC + 1; // increment program counter (2) instr_type = get_instr_type(instr); // determine instruction type (3) data_loc = find_data(instr, instr_type); // locate data (-1 if none) (4) if (data_loc >= 0) // if data_loc is -1, there is no operand (5) data = memory[data_loc]; // fetch the data execute(instr_type, data); //execute instruction (6,7) } } private static int get_instr_type(int addr) {... } private static int find_data(int instr, int type) {... } private static void execute(int type, int data){... } 8 of 21 ECE 3570
9 The inclusion of an interpreter (hardware or software) can allow for Complex Instructions tailor instructions to application tailor for a programmer s request direct implementation of high-level language structures Interpreted Instruction/Language advantages 1) The ability to fix incorrectly implemented instructions in-the-field, or compensate for hardware design deficiencies or omissions. 2) The opportunity to add new instructions at minimal cost, even after machines have been delivered (upgrading or updating system performance) 3) Structured design that permits efficient development, testing, and documentation of complex instructions. (Note: can be done on a software virtual machine while hardware is being designed or built. A process referred to as emulation.) 4) Easily supports backward compatibility for software Interpreted Instruction/Language disadvantage 1) Speed in cycles-per-(high-level)-instruction (CPI) 2) non-standard instructions are likely 9 of 21 ECE 3570
10 A control unit can be used to support hardware/software interpretation V. Heuring and H. Jordan, Computer Design and Architecture, Addison Wesley Longman, Menlo Park, CA ISBN: X. Microinstructions: ROM Based: Decode: The lower level instructions into which a higher level instruction is interpreted Instruction Interpreted into a sequence of micro-instructions that uses a micro-program counter to execute Decode the instruction and prepare for execution Access the operands required for execution 10 of 21 ECE 3570
11 This concept leads to CISC, the Complex Instruction Set Computer Execution time defined by the number of microinstructions executed, not the macroinstructions There is a high clock cycles-per-instruction (CPI) count Large instructions (number of bits) may be required to define Complex Instruction data locations or operations Does not allow control unit to immediately prepare for the next instructions (Clock) Cycles per Instruction (the inverse of instructions per cycle) Easy instructions register to register moves, increments, etc. Complex Instructions addition of indexed memory operands stored to indexed memory (more complex memory address decoding), multiplication, division, square root, extended precision arithmetic, etc. When programmers are expensive, it is cheaper to do it in hardware (control units). When hardware design or designers are expensive, more primitive instructions are desirable. 11 of 21 ECE 3570
12 CISC: Complex Instruction Set Computer Origin: Addressing: Instructions: CPI: Initial Instructions Set and Computer Architecture Hardware designed to facilitate software languages and programming Many modes built in to assembly language Complex, defined based on software and/or application requests Cycles per instruction increasing with instruction complexity Classic CISC Processors Motorola Intel 8088, 8086, Early CISC got out of hand. How to get more accomplished faster one way is to reduce CPI < 10 % of instructions executed 90 % of the time. results in wasted hardware and large size The architectural fix to early CISC To Reduce the CPI, the instructions had to get easier and faster. Maximize the rate at which instructions are issued (CPI=1 goal) Instructions should be easily decoded (fewer, simpler instructions) Memory Accesses are slow and a major processor speed impediment Add more registers for fewer memory accesses Force use of registers by limiting memory accesses to load and store These and other concepts resulted in a Reduced Instruction Set Computer (RISC) But Note: One CISC instruction necessarily results in multiple RISC instructions. 12 of 21 ECE 3570
13 RISC: Reduced Instruction Set Computer Origin: Addressing: 1980 Berkeley: David Patterson and Carlo Sequin 1981 Stanford: John Hennessy Load/Store Instructions: Fixed length (typically word length), minimal formats CPI: Cycles per instruction increasing with instruction complexity Greatly simplified control units! IR PLA control signals RISC Design Principles 1. All Instructions are directly executed by hardware 2. Maximize the rate at which instructions are issued 3. Instructions should be easily decoded 4. Only load and store instructions should reference memory 5. Provide plenty of registers 13 of 21 ECE 3570
14 If RISC was so great, why did CISC still exist? Backward Compatibility: CISC embraced, RISC ignored. Now done by Inst. Units using interpreted RISC-like microinstructions RISC and CISC have traded good ideas, each advancing to modern processors CISC instructions sets with RISC micro-operation execution cores The drive to make processors faster continued. what came next? CISC maturing: Reduce the CPI related to the fetch and decode processes. Instruction prefetching and pre-execution decoding (reduce time in Fetch-Decode stages) Instruction Cache (Harvard Architecture advantage) Instruction-Level-Parallelism fetch while decoding, execute while decoding, etc. RISC maturing: Instruction Cache Instruction-Level-Parallelism fetch while decoding, execute while decoding, etc. CISC: A special ALU for computing address locations parallel processing! This concept has lead to super-scalar processors. 14 of 21 ECE 3570
15 The drive to reduce execution time and speed up the processors Instruction Level Parallelism ILP (pipelining) Processor Level Parallelism PLP (parallel processing) CISC needed instruction prefetching, but RISC allowed full instruction execution pipelining 15 of 21 ECE 3570
16 Pipelined Processors Instruction Fetch Decode Execute Write Back Instruction Execution Cycle Based Scalar Processor Execution F F D E E WB F D D E WB WB CISC Cycle Based Pipelined Scalar Processor Execution RISC Cycle Based Pipelined Scalar Processor Execution A concern of pipelines.. bracnching (1) stalls pipelines and/or (2) flushes pipelines 16 of 21 ECE 3570
17 Branching in RISC Cycle Based Pipelined Scalar Processor Execution Branching can require processors to stall and/or pipelines to be flushed 17 of 21 ECE 3570
18 Processing rate considerations Clock Rate: Processor Latency: Processor Bandwidth Cycles per Instruction The frequency of the processor clock (Hz or 1/sec.) How long it takes to execute an instruction (sec.) Average of all CISC instructions RISC instruction clock cycle times pipeline stages How many instructions per second can the processor perform (MIPS) The rate at which instructions are issued! (inst./sec.) The average number of clocks required for an instruction MIPS (inst/sec) = Freq (cycles/sec) / CPI (cycles/inst) While RISC embraced pipelining The maximum clock rate was limited by the ALU latency CISC recognized that multiple execution units speed up processing delays. Multiplies take longer than adds Therefore have separate multiply and add/subtract execution units 18 of 21 ECE 3570
19 Pentium Processor pipelined, two-issue superscalar U-pipeline V-pipeline Execute all Pentium instructions Execute simple Pentium instructions when there are no conflicts Complex rules defined when both pipes could be used simultaneously. Compilers were written to take advantage of the instruction pairing. Expanding this to a higher order causes headaches in the Instruction and Decode Units. 19 of 21 ECE 3570
20 Superscalar Processors SuperScalar Instruction Execution, Pentium II Concept F D FP WB ALU L/S WB WB F D ALU ALU WB WB F D FP ALU WB L/S WB F D ALU L/S WB WB WB Simplistic Cycle Based Pipelined SuperScalar Processor Execution 20 of 21 ECE 3570
21 Processor Level Parallelism PLP Parallel Processing Architectures (more coming in Chap. 8) Parallel Vector Processors (PVP) Symmetric Multiprocessor (SMP) Massively Parallel Processor (MPP) Distributed Shared Memory Processor (DSM) Cluster of Workstations (COW) Primary Distinctions (1) Shared Variable/Memory vs. Message Passing (no shared memory) (2) Configuration of the Processing Nodes Multiprocessor vs. Multicomputer PU PU PU PU CPU CPU CPU RAM RAM RAM Bus or Switch Net I/F Net I/F Net I/F Memory Memory Memory Communication Network Multi-processor Multiple CPUs share memory (variables) Bus or switch routes connections, processor to processor or processor to memory PVP or SMP Multi-computer Multiple Compute Nodes communicate using message passing Network may be any configuration, including Ethernet or Internet MPP or COW 21 of 21 ECE 3570
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