CS 31: Intro to Systems ISAs and Assembly. Martin Gagné Swarthmore College February 7, 2017

Transcription

1 CS 31: Intro to Systems ISAs and Assembly Martin Gagné Swarthmore College February 7, 2017

2 ANNOUNCEMENT All labs will meet in SCI 252 (the robot lab) tomorrow.

3 Overview How to directly interact with hardware Instruction set architecture (ISA) Interface between programmer and CPU Established instruction format (assembly lang) Assembly programming (IA-32)

4 Abstraction User / Programmer Wants low complexity Applications Specific functionality Software library Reusable functionality Operating system Manage resources Complex devices Compute & I/O

5 Abstraction Applications Specific functionality This week: Machine Interface Operating system Manage resources Complex devices Compute & I/O Last week: Circuits, Hardware Implementation

6 Compilation Steps (.c to a.out) text C program (p1.c) Usually compile to a.out in a single step: gcc m32 p1.c -m32 tells gcc to compile for 32-bit Intel machines Compiler (gcc m32) Reality is more complex: there are intermediate steps! executable binary Executable code (a.out)

7 Compilation Steps (.c to a.out) CS75 text C program (p1.c) Compiler (gcc m32 -S) You can see the results of intermediate compilation steps using different gcc flags text Assembly program (p1.s) executable binary Executable code (a.out)

8 Assembly Code Human-readable form of CPU instructions Almost a 1-to-1 mapping to Machine Code Hides some details: Registers have names rather than numbers Instructions have names rather than variable-size codes We re going to use IA32 (x86) assembly CS lab machines are 64 bit version of this ISA, but they can also run the 32-bit version (IA32) Can compile C to IA32 assembly on our system: gcc m32 -S code.c # open code.s in vim to view

9 Compilation Steps (.c to a.out) text C program (p1.c) Compiler (gcc m32 -S) You can see the results of intermediate compilation steps using different gcc flags text Assembly program (p1.s) binary executable binary Assembler (gcc -c (or as)) Object code (p1.o) Linker (gcc (or ld)) Executable code (a.out) Other object files (p2.o, p3.o, ) Library obj. code (libc.a)

10 Object / Executable / Machine Code Assembly push %ebp mov %esp, %ebp sub $16, %esp movl $10, -8(%ebp) movl $20, -4(%ebp) movl -4(%ebp), %eax addl %eax, -8(%ebp) movl -8(%ebp), %eax leave int main() { Machine Code (Hexadecimal) 55 int a = 10; 89 E5 83 EC int b 10= 20; C7 45 F8 0A C7 45 a = FC a + 14 b; B 45 FC F8 B8 45 return F a; }

11 Compilation Steps (.c to a.out) text C program (p1.c) High-level language text Compiler (gcc m32 -S) Assembly program (p1.s) Interface for speaking to CPU binary executable binary Assembler (gcc -c (or as)) Object code (p1.o) Linker (gcc (or ld)) Executable code (a.out) CPU-specific format (011010) Other object files (p2.o, p3.o, ) Library obj. code (libc.a)

12 Instruction Set Architecture (ISA) ISA (or simply architecture): Interface between lowest software level and the hardware. Defines specification of the language for controlling CPU state: Provides a set of instructions Makes CPU registers available Allows access to main memory Exports control flow (change what executes next)

13 Instruction Set Architecture (ISA) The agreed-upon interface between all software that runs on the machine and the hardware that executes it. Application / Program Compiler CPU / Processor Operating System I/O system Instruction Set Architecture Digital Circuits Logic Gates

14 ISA Examples Intel IA-32 (80x86) ARM MIPS PowerPC IBM Cell Motorola 68k Intel IA-64 (Itanium) VAX SPARC Alpha IBM 360 How many of these have you used?

15 ISA Characteristics High-level language Hardware Implementation ISA Above ISA: High-level language (C, Python, ) Hides ISA from users Allows a program to run on any machine (after translation by human and/or compiler) Below ISA: Hardware implementing ISA can change (faster, smaller, ) ISA is like a CPU family

16 Instruction Translation sum.c (High-level C) int sum(int x, int y) { int res; res = x+y; return res; } sum.s (Assembly) sum: pushl %ebp movl %esp,%ebp subl $24, %esp movl -12(%ebp),%eax addl -8(%ebp),%eax movl %eax, -12(%ebp) leave ret sum.s from sum.c: gcc m32 S sum.c Instructions to set up the stack frame and get argument values An add instruction to compute sum Instructions to return from function

17 ISA Design Questions sum.c (High-level C) int sum(int x, int y) { int res; res = x+y; return res; } sum.s (Assembly) sum: pushl %ebp movl %esp,%ebp subl $24, %esp movl -12(%ebp),%eax addl -8(%ebp),%eax movl %eax, -12(%ebp) leave ret sum.s from sum.c: gcc m32 S sum.c What should these instructions do? What is/isn t allowed by hardware? How complex should they be? Example: supporting multiplication.

18 C statement: A = A*B Simple instructions: LOAD A, eax LOAD B, ebx PROD eax, ebx STORE ebx, A Powerful instructions: MULT B, A Translation: Load the values A and B from memory into registers, compute the product, store the result in memory where A was.

19 Which would you use if you were designing an ISA for your CPU? (Why?) Simple instructions: LOAD A, eax LOAD B, ebx PROD eax, ebx STORE ebx, A Powerful instructions: MULT B, A A. Simple B. Powerful C. Something else

20 RISC versus CISC (Historically) Complex Instruction Set Computing (CISC) Large, rich instruction set More complicated instructions built into hardware Multiple clock cycles per instruction Easier for humans to reason about Reduced Instruction Set Computing (RISC) Small, highly optimized set of instructions Memory accesses are specific instructions One instruction per clock cycle Compiler: more work, more potential optimization

21 So... Which System Won? Most ISAs (after mid/late 1980 s) are RISC The ubiquitous Intel x86 is CISC Tablets and smartphones (ARM) taking over? x86 breaks down CISC assembly into multiple, RISC-like, machine language instructions Distinction between RISC and CISC is less clear Some RISC instruction sets have more instructions than some CISC sets

22 Intel x86 Family (IA-32) Intel i386 (1985) 12 MHz - 40 MHz ~300,000 transistors Component size: 1.5 µm Intel Core i7 4770k (2013) 3,500 MHz ~1,400,000,000 transistors Component size: 22 nm Everything in this family uses the same ISA (Same instructions)!

23 Assembly Programmer s View of State CPU %eax %ecx %edx %ebx %esi %edi %esp %ebp name %eip 32-bit Registers value next instr addr (PC) BUS Addresses Data Instructions address 0x x Memory value Program: data instrs stack %EFLAGS cond. codes 0xffffffff Registers: PC: Program counter (%eip) Condition codes (%EFLAGS) General Purpose (%eax - %ebp) Memory: Byte addressable array Program code and data Execution stack

24 Processor State in Registers Information about currently executing program Temporary data ( %eax - %edi ) Location of runtime stack ( %ebp, %esp ) Location of current code control point ( %eip, ) Status of recent tests %EFLAGS ( CF, ZF, SF, OF ) %eax %ecx %edx %ebx %esi %edi %esp %ebp General purpose registers Current stack top Current stack frame %eip Instruction pointer (PC) CF ZF SF OF Condition codes

25 General purpose Registers Remaining Six are for instruction operands Can store 4 byte data or address value (ex ) Register name Register value %eax 3 %ecx 5 %edx 8 %ebx %esi %edi %esp %ebp %eip %EFLAGS The low-order 2 bytes and two low-order 1 bytes of some of these can be named. %ax is the low-order 16 bits of %eax %al is the low-order 8 bits of %eax May see their use in ops involving shorts or chars %eax %ax %ah %al %ecx %cx %ch %cl %edx %dx %dh %dl %ebx %bx %bh %bl %esi %edi %esp %ebp %si %di %sp %bp

26 Types of IA32 Instructions Data movement Move values between registers and memory Example: movl Load: move data from memory to register Store: move data from register to memory

27 Data Movement Move values between memory and registers or between two registers. Program Counter (PC): Memory address of next instr 0: (Memory) Instruction Register (IR): Instruction contents (bits) 1: 2: 3: 4: Data in WE Data in WE Data in WE Data in WE 32-bit Register #0 32-bit Register #1 32-bit Register #2 32-bit Register #3 MUX MUX A L U N-1: Register File

28 Types of IA32 Instructions Data movement Move values between registers and memory Arithmetic Uses ALU to compute a value Example: addl

29 Arithmetic Use ALU to compute a value, store result in register / memory. Program Counter (PC): Memory address of next instr 0: (Memory) Instruction Register (IR): Instruction contents (bits) 1: 2: 3: 4: Data in WE Data in WE Data in WE Data in WE 32-bit Register #0 32-bit Register #1 32-bit Register #2 32-bit Register #3 MUX MUX A L U N-1: Register File

30 Types of IA32 Instructions Data movement Move values between registers and memory Arithmetic Uses ALU to compute a value Control Change PC based on ALU condition code state Example: jmp

31 Control Change PC based on ALU condition code state. Program Counter (PC): Memory address of next instr 0: (Memory) Instruction Register (IR): Instruction contents (bits) 1: 2: 3: 4: Data in WE Data in WE Data in WE Data in WE 32-bit Register #0 32-bit Register #1 32-bit Register #2 32-bit Register #3 MUX MUX A L U N-1: Register File

32 Types of IA32 Instructions Data movement Move values between registers and memory Arithmetic Uses ALU to compute a value Control Change PC based on ALU condition code state Stack / Function call (We ll cover these in detail later) Shortcut instructions for common operations

33 Addressing Modes Data movement and arithmetic instructions: Must tell CPU where to find operands, store result You can refer to a register by using %: %eax addl %ecx, %eax Add the contents of registers ecx and eax, store result in register eax.

34 Addressing Mode: Immediate Refers to a constant value, starts with $ movl $10, %eax Put the constant value 10 in register eax.

35 Addressing Mode: Memory Accessing memory requires you to specify which address you want. Put address in a register. Access with () around register name. movl (%ecx), %eax Use the address in register ecx to access memory, store result in register eax

36 Addressing Mode: Memory movl (%ecx), %eax Use the address in register ecx to access memory, store result in register eax name value %eax 0 %ecx CPU Registers 0x1A68 (Memory) 0x0: 0x4: 0x8: 0xC: 0x1A64 0x1A x1A6C 0x1A70 0xFFFFFFFF:

37 Addressing Mode: Memory movl (%ecx), %eax Use the address in register ecx to access memory, store result in register eax name %eax 0 %ecx CPU Registers value 0x1A68 1. Index into memory using the address in ecx. (Memory) 0x0: 0x4: 0x8: 0xC: 0x1A64 0x1A x1A6C 0x1A70 0xFFFFFFFF:

38 Addressing Mode: Memory movl (%ecx), %eax Use the address in register ecx to access memory, store result in register eax name %eax 42 %ecx CPU Registers value 0x1A68 2. Copy value at that address to eax. 1. Index into memory using the address in ecx. (Memory) 0x0: 0x4: 0x8: 0xC: 0x1A64 0x1A x1A6C 0x1A70 0xFFFFFFFF:

39 Addressing Mode: Displacement Like memory mode, but with constant offset Offset is often negative, relative to %ebp movl -12(%ebp), %eax Take the address in ebp, subtract 12 from it, index into memory and store the result in eax

40 Addressing Mode: Displacement movl -12(%ebp), %eax Take the address in ebp, subtract 12 from it, index into memory and store the result in eax name value %eax 0 %ecx %ebp CPU Registers 0x1A68 0x1A70 1. Access address: 0x1A70 12 = 0x1A64 0x0: 0x4: 0x8: 0xC: 0x1A x1A x1A6C 0x1A70 0xFFFFFFFF: (Memory)

41 Addressing Mode: Displacement movl -12(%ebp), %eax Take the address in ebp, subtract 12 from it, index into memory and store the result in eax name value %eax 11 %ecx %ebp CPU Registers 0x1A68 0x1A70 2. Copy value at that address to eax. 1. Access address: 0x1A70 12 = 0x1A64 0x0: 0x4: 0x8: 0xC: 0x1A x1A x1A6C 0x1A70 0xFFFFFFFF: Not this! (Memory)

42 Let s try a few examples...

43 What will memory look like after these instructions? x is 2 at %ebp-8, y is 3 at %ebp-12, z is 2 at %ebp-16 movl -16(%ebp),%eax sall $3, %eax imull $3, %eax movl -12(%ebp), %edx addl -8(%ebp), %edx addl %edx, %eax movl %eax, -8(%ebp) Registers name value %eax? %edx? %ebp 0x1270 address value 0x x x x126c 0x1270 Memory

44 What will memory look like after these instructions? x is 2 at %ebp-8, y is 3 at %ebp-12, z is 2 at %ebp-16 movl -16(%ebp),%eax sall $3, %eax imull $3, %eax movl -12(%ebp), %edx addl -8(%ebp), %edx addl %edx, %eax movl %eax, -8(%ebp) D: address value 0x x x x126c 0x1270 address value address value 0x x A: 0x B: 0x C: 0x x x126c 0x126c 0x1270 0x1270 address value 0x x x x126c 0x1270

45 Solution x is 2 at %ebp-8, y is 3 at %ebp-12, z is 2 at %ebp-16 movl -16(%ebp), %eax sall $3, %eax imull $3, %eax movl -12(%ebp), %edx addl -8(%ebp), %edx addl %edx, %eax movl %eax, -8(%ebp) Equivalent C code: x = z*24 + y + x; name %eax %edx value 0x x x %ebp 0x1270 0x126c 0x1270

46 Solution x is 2 at %ebp-8, y is 3 at %ebp-12, z is 2 at %ebp-16 movl -16(%ebp), %eax # R[%eax] z (2) sall $3, %eax # R[%eax] z<<3 (16) imull $3, %eax # R[%eax] 16*3 (48) movl -12(%ebp), %edx # R[%edx] y (3) addl -8(%ebp), %edx # R[%edx] y + x (5) addl %edx, %eax # R[%eax] 48+5 (53) movl %eax, -8(%ebp) # M[R[%ebp]+8] 5 (x=53) Z*24 Equivalent C code: x = z*24 + y + x; name %eax %edx value 0x z 0x y 0x x %ebp 0x1270 0x126c 0x1270

47 REMINDER All labs will meet in SCI 252 (the robot lab) tomorrow.