ECEN 468 Advanced Digital System Design

Size: px

Start display at page:

Download "ECEN 468 Advanced Digital System Design"

Silvester James
6 years ago
Views:

1 ECEN 468 Advanced Digital System Design Lecture 22: Verilog Behavioral Description

2 Structural vs. Behavioral Descriptions module my_module(); assign ; // continuous assignment and (); // instantiation of primitive adder_16 M(); // instantiation of module initial module Structural, no order Behavior, in order in each procedure 2

3 Behavioral Descriptions In General v Co-exists with gate instantiations v Not all descriptions synthesize v Not all synthesized descriptions are desirable v Within a module o Multiple behaviors are allowed o Nested behaviors are not allowed 3

4 Behavioral Statements initial always single_statement; block_of_statements; v initial o Activated from t sim = 0 o Executed once o Initialize a simulation v always o Activated from t sim = 0 o Executed cyclically o Continue till simulation terminates 4

5 Example of Behavioral Statement module clock1 ( clk ); parameter half_cycle = 50; parameter max_time = 1000; output clk; reg clk; initial clk = 0; always #half_cycle clk = ~clk; initial #max_time $finish; module clk t sim 5

6 Assignment v Continuous assignment o Values are assigned to net variables due to some input variable changes o assign = v Procedural assignment o Values are assigned to register variables when certain statement is executed in a behavior o Procedural assignment, = o Procedural continuous assignment, assign = [deassign] o Non-blocking assignment, <= 6

7 Blocking and Non-blocking Assignment initial a = 1; b = 0; a = b; // a = 0; b = a; // b = 0; initial a = 1; b = 0; a <= b; // a = 0; b <= a; // b = 1; v Blocking assignment = o Statement order matters o A statement has to be executed before next statement v Non-blocking assignment <= o Concurrent assignment o If there are multiple non-blocking assignments to same variable in same behavior, latter overwrites previous 7

8 Procedural Continuous Assignment v Continuous assignment establishes static binding for net variables v Procedural continuous assignment (PCA) establishes dynamic binding for variables o assign deassign for register variables only o force release for both register and net variables 8

assign deassign PCA v Binding takes effect when PCA statement is executed v Can be overridden by another PCA statement v deassign is optional v assign takes control, deassign release control module

9 assign deassign PCA v Binding takes effect when PCA statement is executed v Can be overridden by another PCA statement v deassign is optional v assign takes control, deassign release control module flop ( q, qbar, preset, clear, clock, data ); assign qbar = ~q; initial q = 0; ( negedge clk ) q = data; ( clear or preset ) if (!preset ) assign q = 1; else if (!clear ) assign q = 0; else deassign q; module 9

10 Example of assign module mux4_pca(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out; y_out changes with a; if (select == 0) assign y_out=a; else if (select == 1) assign y_out=b; else if (select == 2) assign y_out=c; else if (select == 3) assign y_out=d; else assign y_out=1 bx; module 10

Alternative module mux4_pca(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out; always @(select or a or b or c or d) Value of a is

11 Alternative module mux4_pca(a, b, c, d, select, y_out); input a, b, c, d; input [1:0] select; output y_out; reg y_out; or a or b or c or d) Value of a is assigned if (select == 0) y_out=a; to y_out at this time else if (select == 1) y_out=b; else if (select == 2) y_out=c; else if (select == 3) y_out=d; else y_out=1 bx; module 11

12 force release PCA force sig1 = 0; force sig2 = 1; moda Sig3 = 0; #9 sig3 = 1; sig2 sig1 modb release sig1; release sig2; sig3 v Similar to assigndeassign v Can be applied to net variables v Often applied in testing 12

13 Comparisons of Assignment Variable Output of primitive Net Seq-reg Continuous assignment mode Procedural assignment assign deassign PCA force release PCA Net Register Register Net and register description Structural Structural Behavioral Behavioral Behavioral binding Static Static Dynamic, one shot Dynamic, continuous Dynamic, continuous 13

14 Delay Control Operator (#) initial #0 in1 = 0; in2 = 1; #10 in3 = 1; #40 in4 = 0; in5 = 1; #60 in3 = 0; 14

Event Control Operator (@) @ ( eventa or eventb ) @ ( eventc ) v Event -> identifier or expression v When @ is reached o Activity flow is susped o The event is monitored o The other

15 Event Control ( eventa or eventb ( eventc ) v Event -> identifier or expression v is reached o Activity flow is susped o The event is monitored o The other events are ignored o Other processes keep going v posedge: 0->1, 0->x, x->1 v negedge: 1->0, 1->x, x->0 v Cannot assign value to the event variable inside the synchronized behavior 15

16 Named Event module moda (); event sth_happens; // declaration always ->sth_happens; // trigger event module module modb(); (top_mod.moda.sth_happens) module v Also called abstract event v Declared only in module with keyword event v Must be declared before it is used v Event is triggered by -> v Provide high level inter-module communication without physical details 16

17 Example of Named Event module flop_event ( clk, reset, data, q, q_bar ); input clk, reset, data; output q, q_bar; reg q; event up_edge; assign q_bar = ~q; ( posedge clk ) -> up_edge; ( up_edge or negedge reset ) if ( reset == 0 ) q = 0; else q = data; module 17

18 The wait Construct module moda (); always wait ( enable ) ra = rb; module v Activity flow is susped if expression is false v It resumes when the expression is true v Other processes keep going 18

Intra-assignment Delay: Blocking Assignment // B = 0 at time 0 // B = 1 at time 4 #5 A = B; // A = 1 C = D; A = #5 B; // A = 0 C = D; A = @(enable) B; C = D; A = @(named_event) B; C= D; v If timing

19 Intra-assignment Delay: Blocking Assignment // B = 0 at time 0 // B = 1 at time 4 #5 A = B; // A = 1 C = D; A = #5 B; // A = 0 C = D; A B; C = D; A B; C= D; v If timing control operator(#,@) on LHS o Blocking delay o RHS evaluated at (#,@) o Assignment at (#,@) v If timing control operator(#,@) on RHS o Intra-assignment delay o RHS evaluated immediately o Assignment at (#,@) 19

Intra-assignment Delay: Non-blocking Assignment always @ ( posedge clk ) G <= @ (bus) acc; C <= D; // not blocked " In 1 st cycle, acc is sampled " What if no bus change in the same cycle?

20 Intra-assignment Delay: Non-blocking Assignment ( posedge clk ) G (bus) acc; C <= D; // not blocked " In 1 st cycle, acc is sampled " What if no bus change in the same cycle? " In next cycle, acc is sampled again " Value of acc from previous cycle is overwritten " Warning message v Sampling RHS immediately in the latest cycle v Wait for time control to execute assignment v Subsequent assignments are not blocked 20

21 Be Cautious module or8( y, a, b ); input [7:0] a, b; output [7:0] y; reg [7:0] y; initial assign y = a b; module v Model combinational logic by one-shot (initial) behavior v Valid v Not preferred v Not accepted by synthesis tool 21

22 Example initial a = #10 1; b = #2 0; c = #3 1; initial d <= #10 1; e <= #2 0; f <= #3 1; t a b c d e f 0 x x x x x x 2 x x x x 0 x 3 x x x x x x x

Tell the Differences always @ (a or b) y = a b; always @ (a or b) #5 y = a b; Which one describes

23 Tell the Differences (a or b) y = a b; (a or b) #5 y = a b; Which one describes or gate? Event control is blocked (a or b) y = #5 a b; (a or b) y <= #5 a b; 23

24 Simulation of Assignments v For each given time step o Evaluate all Right-Hand-Side o Execute blocking assignment, even if it is way after a nonblocking assignment o Execute non-blocking assignment that do not have intraassignment timing control o Execute past non-blocking assignment that is scheduled at this time o Execute $monitor. However, $display is executed whenever it is encountered. o Increment time step 24

25 Simulation of Non-blocking Assignment v Normally the last assignment at certain simulation time step v If it triggers other blocking assignments, it is executed before the blocking assignment it triggers always A <= B; always C D; 25

26 Example initial a = 1; b = 0; a <= b; b <= a; $display( a=%b b=%b, a, b); initial a = 1; b = 0; a <= b; b <= a; $monitor( a=%b b=%b, a, b); a=1 b=0 a=0 b=1 26

Repeated Intra-assignment Delay rega = repeat (5) @ ( negedge clk ) regb; tmp = regb; @ ( negedge

27 Repeated Intra-assignment Delay rega = repeat ( negedge clk ) regb; tmp = ( negedge clk ( negedge clk ( negedge clk ( negedge clk ( negedge clk ); rega = tmp; 27

Indeterminate Assignment module multi_assign(); reg a, b, c, d; initial #5 a = 1; b = 0; always @ ( posedge a ) c = a; always @ ( posedge a ) c = b; always @ ( posedge a ) d = b; always @

28 Indeterminate Assignment module multi_assign(); reg a, b, c, d; initial #5 a = 1; b = 0; ( posedge a ) c = a; ( posedge a ) c = b; ( posedge a ) d = b; ( posedge a ) d = a; module v Multiple assignments are made to same variable in different behavior v Value deps on code order or vor specifications v Similar to raceconditions in hardware 28

29 Activity Flow Control ( if else ) if ( A == B ) P = d; if ( B < C ); if ( a >= b ) v Syntax: if ( expression ) statement [ else statement ] v Value of expression o 0, x or z => false o Non-zero number => true if ( A < B ) P = d; else P = k; if ( A > B ) P = d; else if ( A < B ) P = k; else P = Q; 29

Conditional Operator (? : ) always @ ( posedge clock ) yout = ( sel )?

30 Conditional Operator (? : ) ( posedge clock ) yout = ( sel )? a + b : a b; Conditional operator can be applied in either continuous assignments or behavioral descriptions 30

The case Statement module mux4 ( a, b, c, d, select, yout ); input a, b, c, d; input [1:0] select; output yout; reg yout; always @( a or b or c or d or select ) case ( select ) 0: yout = a; 1: yout =

31 The case Statement module mux4 ( a, b, c, d, select, yout ); input a, b, c, d; input [1:0] select; output yout; reg yout; a or b or c or d or select ) case ( select ) 0: yout = a; 1: yout = b; 2: yout = c; 3: yout = d; default yout = 1`bx; case module v Case items are examined in order v Exact match between case expression and case item v casex don t care bits with x or z v casez don t care bits with z 31

Expression Matching in case Construct Expression or case_item case casex casez 0 0 0 0 1 1 1 1 x x 0 1 x z x

32 Expression Matching in case Construct Expression or case_item case casex casez x x 0 1 x z x z z 0 1 x z 0 1 x z? (explicit don t care) N/A N/A 0 1 x z ( pulse ) casez ( word ) 8`b0000???? : ; 32

33 The repeat Loop word_address = 0; repeat ( memory_size ) memory [word_address] = 0; word_address = word_address + 1; 33

34 The for Loop reg [15:0] rega; integer k; for ( k = 4; k; k = k 1 ) rega [ k+10 ] = 0; rega [ k+2 ] = 1; Loop variables have to be either integer or reg 34

susp external activities module sth ( externalsig ); input

35 The while Loop cnt1s reg [7:0] tmp; cnt = 0; tmp = rega; while ( tmp ) cnt = cnt + tmp[0]; tmp = tmp >> 1; Loop activities susp external activities module sth ( externalsig ); input externalsig; always while ( externalsig ); module Can be less forever 35

36 The disable Statement k = 0; for ( k = 0; k <= 15; k = k + 1 ) if ( word[ k ] == 1 ) disable ; Terminate prematurely in a block of procedural statements 36

37 The forever Loop parameter half_cycle = 50; initial : clock_loop clock = 0; forever #half_cycle clock = 1; #half_cycle clock = 0; initial #350 disable clock_loop; 37

38 always and forever always Declares a behavior Cannot be nested Executes when simulation s forever Computational activity flow within a behavior Can be nested Executes when statement is reached 38

synthesis For simulation in testbench module race ( ); fork #150 a = b; #150

39 Parallel Activity Flow fork // t_sim = 0 join #50 wave = 1; #100 wave = 0; #150 wave = 1; #300 wave = 0; // executes at t_sim = 300 Not supported by synthesis For simulation in testbench module race ( ); fork #150 a = b; #150 c = a; join module module fix_race ( ); fork a = #150 b; c = #150 a; join module 39

ECEN 468 Advanced Logic Design

ECEN 468 Advanced Logic Design Lecture 28: Synthesis of Language Constructs Synthesis of Nets v An explicitly declared net may be eliminated in synthesis v Primary input and output (ports) are always retained