VHDL for Modeling - Module 10

Transcription

1 VHDL for Modeling Module 10 Jim Duckworth, WPI 1

2 Overview General examples AND model Flip-flop model SRAM Model Generics DDR SDRAM Model Constraints Metastability Block Statements Just for reference Jim Duckworth, WPI 2

3 We have covered VHDL for Modeling VHDL for Synthesis VHDL for testing (simulation) Now - VHDL for modeling Describes the expected behavior of a component or device Can be used to test other components for example a model of a CPU could be used to test: UART DRAM memory controller cache controller Jim Duckworth, WPI 3

4 AND gate model -- 74LS08 model (typical delays) ENTITY ls08 IS END ls08; PORT(a, b : IN std_logic; c : OUT std_logic); ARCHITECTURE behav OF ls08 IS BEGIN END behav; c <= 1 AFTER 8 ns WHEN a = 1 AND b = 1 ELSE 0 AFTER 10 ns; Jim Duckworth, WPI 4

5 Simulation Results Jim Duckworth, WPI 5

6 D flip-flop model -- 74LS74 model (typical delays) -- 74LS74 model (typical delays) ENTITY ENTITY ls74 ls74 IS IS PORT(d, PORT(d, clr, clr, pre, pre, clk clk : : IN IN std_logic; std_logic; q : OUT std_logic); q : OUT std_logic); END END ls74; ls74; ARCHITECTURE ARCHITECTURE behav behav OF OF ls74 ls74 IS IS BEGIN BEGIN PROCESS(clk, clr, pre) PROCESS(clk, clr, pre) BEGIN BEGIN IF clr = 0 THEN IF clr = 0 THEN q <= 0 AFTER 25 ns; q <= 0 AFTER 25 ns; ELSIF pre = 0 THEN ELSIF pre = 0 THEN q <= 1 AFTER 13 ns; q <= 1 AFTER 13 ns; ELSIF clk EVENT AND clk = 1 THEN ELSIF clk EVENT AND clk = 1 THEN IF IF d d = = 1 1 THEN THEN q q <= <= 1 1 AFTER AFTER ns; ns; ELSE ELSE q q <= <= 0 0 AFTER AFTER ns; ns; END END IF; IF; END END IF; IF; END END PROCESS; PROCESS; END END behav; behav; Jim Duckworth, WPI 6

7 Simulation Results Jim Duckworth, WPI 7

8 Adding Constants - same as previous -- 74LS74 model (typical delays) ENTITY ls74 IS PORT(d, clr, pre, clk : IN std_logic; q : OUT std_logic); CONSTANT t_rise : TIME := 13 ns; CONSTANT t_fall : TIME := 25 ns; END ls74; ARCHITECTURE behav OF ls74 IS BEGIN PROCESS(clk, clr, pre) BEGIN IF clr = 0 THEN q <= 0 AFTER t_fall; ELSIF pre = 0 THEN q <= 1 AFTER t_rise; ELSIF clk EVENT AND clk = 1 THEN IF d = 1 THEN q <= 1 AFTER t_rise; ELSE q <= 0 AFTER t_fall; END IF; END IF; END PROCESS; END behav; Jim Duckworth, WPI 8

9 Adding setup and pulse width checks LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ls74 IS PORT(d, clr, pre, clk : IN std_logic; q : OUT std_logic); CONSTANT t_rise : TIME := 13 ns; CONSTANT t_fall : TIME := 25 ns; CONSTANT t_setup : TIME := 20 ns; CONSTANT t_width : TIME := 25 ns; END ls74; Jim Duckworth, WPI 9

10 Basic D flip-flop description same ARCHITECTURE behav OF ls74 IS BEGIN PROCESS(clk, clr, pre) BEGIN IF clr = '0' THEN q <= '0' AFTER t_fall; ELSIF pre = '0' THEN q <= '1' AFTER t_rise; ELSIF clk'event AND clk = '1' THEN IF d = '1' THEN q <= '1' AFTER t_rise; ELSE q <= '0' AFTER t_fall; END IF; END IF; END PROCESS; Jim Duckworth, WPI 10

11 Add setup and pulse width checks -- process to check data setup time PROCESS(clk) BEGIN IF clk'event AND clk = '1' THEN ASSERT d'last_event > t_setup REPORT "D changed within setup time" SEVERITY ERROR; END IF; END PROCESS; -- process to check clock high pulse width PROCESS(clk) VARIABLE last_clk : TIME := 0 ns; BEGIN IF clk'event AND clk = '0' THEN ASSERT NOW - last_clk > t_width REPORT "Clock pulse width too short" SEVERITY ERROR; ELSE last_clk := NOW; END IF; END PROCESS; END behav; Jim Duckworth, WPI 11

12 LS74 Model in ModelSim Jim Duckworth, WPI 12

13 Test Bench without SRAM SRAM connections are open DSP Picoblaze ZZ Display Jim Duckworth, WPI 13

14 SRAM model simplified, no delays Jim Duckworth, WPI 14

15 New testbench Adding the SRAM model DSP Picoblaze Display SRAM Model Jim Duckworth, WPI 15

16 Adding the SRAM model to the test bench Jim Duckworth, WPI 16

17 ISSI SRAM Verilog Model (partial) // IS61LV25616 Asynchronous SRAM, 256K x 16 = 4M; speed: 10ns. // Note; 1) Please include "+define+ OEb" in running script if you want to check // timing in the case of OE_ being set. // 2) Please specify access time by defining tac_10 or tac_12. // `define OEb `define tac_10 `timescale 1ns/10ps module IS61LV25616 (A, IO, CE_, OE_, WE_, LB_, UB_); parameter dqbits = 16; parameter memdepth = ; parameter addbits = 18; parameter Toha = 2; parameter Tsa = 2; `ifdef tac_10 parameter Taa = 10, Thzce = 3, Thzwe = 5; `endif `ifdef tac_12 parameter Taa = 12, Thzce = 5, Thzwe = 6; `endif input CE_, OE_, WE_, LB_, UB_; input [(addbits - 1) : 0] A; inout [(dqbits - 1) : 0] IO; wire [(dqbits - 1) : 0] dout; reg [(dqbits/2-1) : 0] bank0 [0 : memdepth]; Jim Duckworth, WPI 17

18 Generics Generics useful for making design units more general purpose Generics allow information to be passed into a design description Example information propagation delays size of component (changing input and output ports) load capacitance/resistance Jim Duckworth, WPI 18

19 LS08 example with generics -- 74LS08 model ENTITY ls08 IS GENERIC(t_rise, t_fall : TIME); END ls08; PORT(a, b : IN std_logic; c : OUT std_logic); ARCHITECTURE behav OF ls08 IS BEGIN END behav; c <= 1 AFTER t_rise WHEN a = 1 AND b = 1 ELSE 0 AFTER t_fall; This is now a parameterized model (general purpose) rather than hard-coded version Actual delay is determined at simulation time (or synthesis) by value passed to model Jim Duckworth, WPI 19

20 Instantiating Components with Generics -- example use of LS08 with generic values ENTITY test IS PORT(in1, in2, in3 : IN std_logic; END test; out1 : OUT std_logic); ARCHITECTURE behav OF test IS BEGIN END behav; COMPONENT ls08 GENERIC(t_rise, t_fall : TIME); PORT(a, b : IN std_logic; c : OUT std_logic); END COMPONENT; SIGNAL int : std_logic; u1: ls08 GENERIC MAP(8 ns, 10 ns) -- typical delays PORT MAP(a => in1, b => in2, c => int); u2: ls08 GENERIC MAP(15 ns, 20 ns)-- max delays PORT MAP(a => int, b => in3, c => out1); Jim Duckworth, WPI 20

21 Another Example (with default values) Can provide default values for generics Only need GENERIC MAP if necessary to change them ENTITY and2 IS GENERIC(t_rise, t_fall : TIME := 10 ns; load : INTEGER := 3); PORT(a, b IN : IN std_logic; c : OUT std_logic); END and2; ARCHITECTURE generic_model OF and2 IS BEGIN c <= 1 AFTER (t_rise + (load * 2 ns)) WHEN a = 1 AND b = 1 ELSE 0 AFTER (t_fall + (load * 2 ns)); END generic_model; u1: and2 GENERIC MAP(5 ns, 7 ns, 4) PORT MAP (a = > ); -- default overridden u2: and2 PORT MAP(a => ); -- uses default values Jim Duckworth, WPI 21

22 Modifying Component Size Jim Duckworth, WPI 22

23 Making two copies different size Jim Duckworth, WPI 23

24 Schematic of two shift registers Jim Duckworth, WPI 24

25 DDR SDRAM Model Jim Duckworth, WPI 25

26 DDR SDRAM Model (cont d) Jim Duckworth, WPI 26

27 DDR SDRAM Model (cont d) Jim Duckworth, WPI 27

28 DDR SDRAM Model (cont d) Jim Duckworth, WPI 28

29 DDR SDRAM Model (cont d) Jim Duckworth, WPI 29

30 Metastability Flip-flops may go metastable if input signals do not meet setup and hold specifications relative to clock signal CLK D Q Rules: Input only drives one FF Add 2-FF synchronizer IF clk EVENT AND clk = 1 THEN input_d <= input; input_dd <= input_d; Jim Duckworth, WPI 30

31 Constraints (for ref) Used to guide the synthesis tools Example 32-bit counter - no constraints (speed grades -4 and -5) ====================================================== Advanced HDL Synthesis Report Macro Statistics # Counters : 1 32-bit up counter : 1 ====================================================== Timing Summary: Speed Grade: -4 Minimum period: 6.680ns (Maximum Frequency: MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 8.094ns Maximum combinational path delay: No path found =============================================== Speed Grade: -5 Minimum period: 5.767ns (Maximum Frequency: MHz) Jim Duckworth, WPI 31

32 Adding timing constraint Add to UCF file: NET "clk" PERIOD = 6ns HIGH 50%; WARNING:Par:62 - Your design did not meet timing Constraint Check Worst Case Best Case Timing Timing Slack Achievable Errors Score * NET "clk_bufgp/ibufg" PERIOD = 6 ns HIGH SETUP ns 6.456ns % HOLD 2.432ns constraint not met. Jim Duckworth, WPI 32

33 Try relaxing constraint NET "clk" PERIOD = 6.5ns HIGH 50%; Constraint Check Worst Case Best Case Timing Timing Slack Achievable Errors Score NET "clk_bufgp/ibufg" PERIOD = 6.5 ns HIG SETUP 0.203ns 6.297ns 0 0 H 50% HOLD 2.280ns All constraints were met. Also see Timing Constraint User Guide Examples: NET abc OFFSET = OUT xx ns AFTER clk ; NET def OFFSET = IN xx ns BEFORE clk ; Jim Duckworth, WPI 33

34 BLOCK statements (for ref) BLOCK statements can be used to partition and logically group areas of the design Like a schematic sheet Example: design of a CPU, divide into ALU block Control block Decode block Blocks represent a self-contained area, each block can: declare lcoal signals types, constants, etc. Blocks can reference signals from a level above Jim Duckworth, WPI 34

35 Example ENTITY cpu IS PORT(clk : IN std_logic; input_bus : IN std_logic_vector(63 DOWNTO 0); ); -- port descriptions END cpu; ARCHITECTURE block_model OF cpu IS SIGNAL instruction_bus, src_operand : std_logic_vector(63 DOWNTO 0); BEGIN alu: BLOCK SIGNAL inst_bus, data_bus : std_logic_vector(31 DOWNTO 0); BEGIN -- statements describing ALU operation END BLOCK alu; decode: BLOCK SIGNAL ; -- signals local to this decode block BEGIN -- statements describing decode operation END BLOCK decode; END block_model; Jim Duckworth, WPI 35