Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs

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1 Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita Dept. of Electronics Engineering, University of Tokyo Dept. of Computer Hardware, University of Aizu VLSI Design and Education Center, University of Tokyo matsumoto@cad.t.u-tokyo.ac.jp, hiroshis@u-aizu.ac.jp, fujita@ee.t.u-tokyo.ac.jp Abstract In this paper, we propose a formal equivalence checking method for source-to-source refinements in C programs for hardware behavioral descriptions. In the method, the textual differences between the two programs are identified at first to get hints where the equivalence must be checked. Then, the equivalence of differences is verified by symbolic simulation and validity checking techniques. If the equivalence is not established, our method incrementally extends statements to be verified based on dependency until the equivalence is proved. For the extensions, the method uses dependence graphs of the programs. Finally, through the experimental results, we show the method can efficiently perform equivalence checking. 1 Introduction As VLSI designs are becoming larger and more complicated, the verification of such large designs is becoming harder and harder. Currently, in many designs, the whole design periods have been dominated by the verification times. Therefore, the design productivities will be much improved if the verification times are reduced. Recently, system-level designs are widely accepted to make design processes more efficient. There are several advantages in system-level design. One is the reduction of designer s effort to write down designs because design descriptions are more abstracted than the ones in RTL. Another is that designers can perform flexible software/hardware partitions as both parts can be described seamlessly in system-level designs, which enables designers to find better implementation from early stages in the design flow. We have proposed a C-based system-level design methodology as shown in Figure 1. In this flow, functionalities of designs are specified in C language or C- based design language such as SpecC [2] or SystemC Source specification for whole system in C (no distinction between hardware and software) Decision which part is to be realized as hardware Refined description in C - algorithm optimizations - restricrion on recursive function calling - free of pointer references Introduction of concurrency - concurrent process - communication Refined description with concurrency (in SpecC, SystemC) HW part SW part Transformations to meet the constraints of the behavioral synthesizer Behivioral Compiler synthesizer Equivalence Checking Powerful optimizations that cannot be carried out by compilers : refinement step Figure 1. C-based system level design flow [10]. From a specification model, the design description is refined by many steps into a software design to be compiled to assembly codes and a hardware design to be synthesized to an RTL design by behavioral synthesis techniques. These refinements are currently executed manually or by interactive ways, because methods or tools which can automate the whole system-level design are not available. In addition, manual refinements are required when a designer wants a highly optimized design that cannot be generated by compilers or behavioral synthesizers. Representative refinements at system-level designs include: Algorithm optimizations

2 Transformations to restrict uses of functions that are difficult to be implemented in hardware (for example, pointer uses, recursive callings, and so on) Transformations to make an input description to behavioral synthesizers (behavioral synthesizers can accept the restricted set of C-based design languages or their own design languages) Introduction of concurrent processes and communication among them To avoid generating new design bugs in these manual refinements, formal equivalence checking is strongly required to be performed between the refinements. In this work, we propose an equivalence checking method to verify manual source-to-source refinements in C programs. The method is based on symbolic simulation which is a well used technique in formal methods. However, if large C programs are given, symbolic simulation may fail because of memory space problem ortakingtoomuchtime. Tosolvetheproblem,in our method, differences between programs are identified and verified separately. Currently, as the first step of the study, textual differences are utilized. For each difference, the equivalence is verified by applying symbolic simulation only for the statements related to the difference. In the case that the equivalence of a difference is not proved or proved to be inequivalent, the verification area is incrementally extended by adding preceding and/or succeeding statements along dependence relation. The analysis is carried out on dependence graphs of given programs. The verification is repeated until the primary output variables are proved to be inequivalent or the extension reaches to the start/end of the programs. Our proposed method can verify the equivalence between two programs efficiently when the verification area for each difference is very small. However, in the worst case, the verification of the whole programs may be required. In the following sections, we explain the proposed method in more detail and show experimental results. 2 Related Work Several formal verification methods for C programs have been proposed. For example, CBMC [6] verifies that a given ANSI-C program satisfies given properties by converting them into bit vector equations and solving satisfiability using Chaff [9]. BLAST [7] also verifies given properties in a given C program. It expresses the state transitions of the given program using binary decision diagrams and abstracts the number of states to be verified. However, these methods cannot verify the equivalence of large programs, since they interpret values of all variables and functionalities of all operators in the given program. Recently, equivalence checking methods that can be applied to C-based designs in system-level or behaviorlevel have been proposed. In [3], an equivalence checking method for scheduling of processes are presented. It can efficiently verify the equivalence of scheduling in which the computation algorithms are preserved. In [4], on the other hand, the equivalence of optimizations within loops are verified. Different from the method, our target of verification is more general refinements for several purposes as described in section 1. 3 Basic Notions 3.1 Symbolic Simulation for Equivalence Checking In our method, equivalence of variables is proved by performing symbolic simulation where each variable is treated as just a symbol. The symbolic simulation technique in our method is taken from the method shown in [5] where the equivalence of RTL or gate-level descriptions in HDL was verified. We modify the method for the verification of C programs. The characteristics of our developed symbolic simulator are as follows: When an expression is simulated symbolically, an equivalence class (EqvClass) for the expression is created. If two variables in different EqvClasses are prove to be equivalent during symbolic simulation, the two EqvClasses are merged into a single EqvClass. When a case split occurs, all potentially executable paths are simulated. Functions can be uninterpreted in symbolic simulation. After symbolic simulation, the two variables are equivalent if they belong to the same EqvClass. A simple example of equivalence checking in terms of symbolic simulation is shown in Figure 2. In this example, we verify the equivalence of the variable reg0 0 in the two programs. Note that a variable is denoted by v i,j where i(i =0...n) means the i-th appearance of the variable in programs and j distinguishes two programs. j = 1 is for the variables in the program 1 while j = 2 is for the variables in the program Cooperating Validity Checker (CVC) In symbolic simulation, the equivalence of pairs of expressions with operators (e.g., a + a and 2 a) cannot be proved, because symbolic simulation does not

3 Assumption: The variables reg10 and reg20 are equivalent in both programs. src10,2 = reg10,2 src20,2 = reg20,2 (A) req00,1 = reg10,1 + reg20,1 reg00,2 = src10,2 + src20,2 (B) Program 1 Program 2 Transitions of EqvClasses Beginning of simulation (from assumption) E1 = (reg10,1, reg10,2) E2 = (reg20,1, reg20,2) (A) E1 = (reg10,1, reg10,2, src10,2) E2 = (reg20,1, reg20,2, src20,2) int sub_abs (int x, int y) { int z; if (x >= y) z = x - y; else z = y - x; return z; } Example C program ENTER sub_abs x := x_in y := y_in if (x >= y) z := x - y Control dependence Data dependence z := y - x return z End of simulation E1 = (reg10,1, reg10,2, src10,2) E2 = (reg20,1, reg20,2, src20,2) E3 = (reg00,1, reg00,2, reg10,1 + reg20,1) (B) E1 = (reg10,1, reg10,2, src10,2) E2 = (reg20,1, reg20,2, src20,2) E3 = (reg00,1, reg10,1 + reg20,1) E4 = (reg00,2, src10,2 + src20,2) reg00,1 and reg00,2 are in the same EqvClass Figure 2. An example of equivalence checking based on symbolic simulation interpret the functionalities of the operators and the values of the variables. To prove the equivalence of these expressions, our method calls Cooperating Validity Checker (CVC) [8] to perform the further verification. CVC is a decision procedure that checks logical validity of given formulas. Formulas are represented by propositional operators and equations between linear mathematical operators. By using CVC in our method, the ability of equivalence checking between variables can be improved. 3.3 System Dependence Graph In our method, if simulated statements in given two programs cannot be proved to be equivalent, statements to be verified are incrementally extended to preceding and/or succeeding statements based on the dependence relation. To identify dependence relation, we use System Dependence Graphs (SDGs) proposed in [1]. An SDG consists of a set of nodes and a set of edges. Basically, each node expresses a statement in a program, and each edge between nodes expresses a data or control dependence. Figure 3 shows the SDG of an example C program. As shown in the figure, a data dependence edge is drawn from the node that defines a variable to the node that uses the defined variable. On the other hand, a control dependence edge is drawn from the node that controls the conditional branch (called control point) to the node that are controlled by it. System Dependence Graph for the example program Figure 3. An example C program and its SDG 4 Our Proposed Equivalence Checking Method The overall flow of our proposed equivalence checking method is shown in Figure 4. As inputs, two C programs are given with the definition of input and output variables. In addition, the correspondence of those variables between programs is given. Then, our method verifies the equivalence of the output variables by using symbolic simulation and reports the verification result ( equivalent or not equivalent ). In the following sections, the verification method is described in detail. 4.1 Restrictions for Input C Programs Our method can verify C programs that satisfy the following restrictions. No pointer uses (or all pointer uses are analyzed and replaced by certain variables) or dynamic memory allocation Loops are unrolled in a certain times No recursive function calls These restrictions come from the limitation of symbolic simulation. Therefore, if these statements are out of the verification by symbolic simulation, it does not matter whether given C programs have these statements or not. Currently, our symbolic simulator aborts the verification when these statements are appeared during symbolic simulation. In practice, however, refinements that are not related to these statements are often carried out. In such cases, our symbolic simulator can carry out verification. 4.2 Identification of Textual Differences In our method, textual differences are identified at first by using UNIX command diff to get hints where the equivalence of programs must be verified.

4 Program 1 Program 2 Identification of textual differences corresponding to the difference (one set from each description). Note that a difference may consist of several statements. We define input variables and output variables of a local verification area as below. Are there any differences to be verified? Yes Decision of the initial verification area and defined/used variables No Termination with the result "equivalent" Local input variable a variable corresponding to a data dependence edge coming from out of the verification area to the area Local output variable a variable corresponding to a data dependence edge coming from the verification area to out of the area Yes Equivalence checking by symbolic simulation Is the equivalence proved? No Is the verification area extended any more? Yes Extension of the verification area No Termination with the result "not equivalent" (counterexample is produced) Figure 4. Our Proposed Verification Flow For the purpose of making correspondence between statements in both descriptions, dummy statements are inserted to the descriptions in the following cases. When an assignment is removed, the assignment to the same variable such as a = a; is inserted. When a conditional branch is removed, the same branch structure is inserted where all assignments are replaced by ones to the same variable. Since these inserted statements clearly preserve the original behavior, the result of verification is not changed. Even if many statements are different, the descriptions after inserted the dummy statements cannot be twice as large as the original descriptions. Then, SDGs for both descriptions are constructed. At the same time, statements are removed from SDGs when they do not affect any output variables and are not affected by any input variables. This reduction can be performed on SDGs and effective when users specify intermediate variables as inputs/outputs. 4.3 Initial Verification In our method, a verification area can be presented by a set of SDG nodes since each node corresponds to a statement in C descriptions. The initial verification area for a difference is two sets of SDG nodes Only when a variable is a local output variable in each description, its equivalence is checked in the verification. Although other local output variables are not checked for this difference, they will be taken into account in verification for other differences if required. A pair of corresponding local input variables is equivalent in the following cases. They are not affected by any differences that are prove to be inequivalent. They are already proved to be equivalent by the verification of another difference. In the verification, equivalences of other pairs of local input variables are considered to be unknown variables. If all pairs of local output variables are proved to be equivalent, the verification area of the difference is also proved to be equivalent. On the other hand, if the equivalence of any local output variables are not proved, the verification area is extended so that preceding and/or succeeding statements are included. 4.4 Extension of Verification Area If the equivalence checking for a local verification area is not proved, the area is extended based on the dependence relation. The reason why the extension is required is that the equivalence of a difference can be proved after extending the verification area. We define some extensions of the verification area as below. Backward extension Adding a directly preceding SDG node that has a data dependence to any local input variable Forward extension along data dependence Adding a directly succeeding SDG node that has a data dependence from any local output variable Forward extension along control dependence Adding all directly succeeding SDG nodes that have a control dependence from any local output variables (This extension can be carried out if any condition nodes are proved to be inequivalent)

5 In extension, multiple SDGs that presents assignments to the same variable are added to the verification area when control dependences of them are different. In the cases, the nodes that control these assignments are also added. After the extensions, the local input/output variables are derived for the new verification area, and verification is carried out. We also define the limitation of extensions. If the equivalences of added SDG nodes are already proved, no backward extension is applied from them If added statements are the top (or end) of programs, no backward extension (or forward extension) is applied from them 4.5 Symbolic Simulation on SDGs In this work, symbolic simulation presented in section 3 is used at SDG-level. To preserve dependence relations, if a data/control dependence from a node A toanodeb exists, A must be symbolically simulated before B is simulated. The ordering can be realized by topologically sorting all SDG nodes in the verification area. 4.6 Verification Example We show how our proposed method works on an example shown in Figure 5. We assume that the variables in1andin2 are the primary inputs of the program, and the variable out is the primary output. The statement x = x; in Description 1 is added as a dummy statement to make a correspondence to x = x + c; in Description 2. At first, the first difference D1 is verified. The first verification area is A in the figure, and its local input variables are a and c, and its local output variable the variable x. Since all local input variables are unknown, the equivalence of x cannot be proved. Thus, in this case, we decide to backwardly extend the area from a. Then, the extended verification area become the area B, and the verification is carried out again. In this case, the local input variables are in1, in2, and c, and the local output variables are x and (in1 >in2). Since the equivalence of x cannot be proved after the verification with the area B, we decide to forwardly extend the area from x and obtain the area C. After the verification with this area C, we can prove the equivalence of x. The verification for the difference D2 is not carried out, since it is included the verification for D1. Then, as the all difference is verified, it can be said that the two descriptions are functionally equivalent. if (in1 > in2) { a = in1 + in2; b = in1 * 3; c = in2 * 5; } else { a = in2 - in1; b = in1 * 5; c = in2 * 3; } x = a + c; y = b - c; x = x; out = x + y; D1 D2 if (in1 > in2) { a = in1 + in2; b = in1 * 3; c = in2 * 5; } else { a = in2 - in1; b = in1 * 5; c = in2 * 3; } x = a; y = b - c; x = x + c; out = x + y; Description 1 Description 2 in1 in2 in1 in2 in2 in1>in2 T F in1 in2 in1>in2 T F in1 a=in1+in2 a=in1-in2 a=in1+in2 a=in1-in2 A B C x=a+c x=x x c x=a x=x+c Figure 5. Equivalence checking example 4.7 Discussion on Strategy of Extension In general, a verification area can have multiple local input/output variables. Therefore, there are a number of combinations to apply backward and forward extensions. This makes us difficult to define the best strategy of extensions. In the followings, we list some reasonable strategies for differences usually happen in practice. Applying backward extensions until the start points of the programs, then applying forward extensions until end points Applying forward extensions and backward extensions in turn First, applying backward extensions m times, then applying forward extensions n times (m, n are predefined number) These strategies are similar to ones in equivalence checking of gate-level circuits. In some cases, designers know which kinds of refinements are carried out. In such cases, a specific strategy for the refinement can be applied to improve the verification speed. 5 Experimental Results We implemented the proposed method with CodeSurfer[11] and CVC. CodeSurfer is used to construct SDGs of programs to be verified. The experiments were performed on the following design examples writteninclanguage. Common sub-expression eliminations in a differential equation solver (total 130 lines, differences are 10 parts, 30 lines) Refinements in IDCT(Inverse Discrete Cosine Transform) (total 420 lines, differences are 16 parts, 96 lines) from MPEG2 program[12] Refinements from 4-Xor into 2-Xor in the encryption function (total 1235 lines, differences are 40 parts, 120 lines) from Rijndael program[13] x c

6 Table 1. Experimental Results result time verified nodes total nodes diffeq1 eqv 0.7 sec diffeq2 ineqv 0.7 sec mpeg1 eqv 1.8 sec mpeg2 ineqv 0.9 sec rijndael1 eqv 0.3 sec rijndael2 ineqv 0.6 sec The refinements in IDCT is to reduce the computation, and it has applied combinations of common subexpression elimination and factorization. All experiments were carried out on PC with 2.4 GHz processor and 2 GB memory. The experimental results are shown in Table 1. All verification results are same as what we have intended. As shown in the table, the numbers of SDG nodes that are symbolically simulated are much smaller than the total SDG nodes in the programs. This is seen especially in the inequivalent cases. This is because the result can be concluded to be inequivalent if a counterexample is found. As for the comparison of verification times with the method that symbolically simulates the whole programs, the proposed method takes shorter times to verify when the verified programs are relatively large. For example, equivalence checking with symbolic simulation of the whole IDCT example, which has eight conditional branches, takes more than 800 sec, while the proposed method takes 1.8 sec as shown in the table. On the other hand, diffeq and rijndael examples can be solved within 1 sec by both of the two methods. In addition, symbolic simulation for the whole MPEG2 or Rijndael cannot be carried out in practical time. Therefore, our approach where only the portions related to the differences are symbolically simulated is effective especially when a given program is very large. 6 Conclusions In this paper, we proposed a equivalence checking method for two C programs. The method utilizes differences between programs and verifies only the portions related those differences. As a result, the amount of symbolically simulated statements is much smaller, which improves the efficiency of the verification. This is confirmed through experiments. As our future work, we plan to develop a method to identify the differences in SDGs and a method that can deal with concurrency. The former will enable to identify the differences more exactly, since sometimes textual difference includes irrelevant statements for equivalence checking. The latter method is required when the design descriptions have concurrent processes, which often occurs in hardware design. References [1] S.Horwitz,T.Reps,andD.Binkley, Interprocedural Slicing Using Dependence Graphs, ACM Transactions on Programming Languages and Systems, Vol.12, No.1, pp.26 60, [2] D. Gajski, J. Zhu, R. Doemer, A. Gerstlauer, and S. Zhao, SpecC: Specification Language and Methodology, Kluwer Academic Publisher, Mar [3] S. Abdi and D. Gajski, Functional Validation of System Level Static Scheduling, Proc. of Design, Automation and Test in Europe 05, pp , Mar [4] K. C. Shashidhar, M. Bruynooghe, F. Catthoor, and G. Janssens, Functional Equivalence Checking for Verification of Algebraic Transformations on Array- Intensive Source Code, Proc. of Design, Automation and Test in Europe 05, pp , Mar [5] G. Ritter, Formal Sequential Equivalence Checking of Digital Systems by Symbolic Simulation, PhD thesis, Darmastadt University of Technology, [6] E. Clarke, D. Kroening, and K. Yorav, Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking, Proc. of Design Automation Conference 03, pp , [7] T. A. Henzinger, R. Jhala, R. Majumdar, and G. Sutre, Lazy Abstraction, Proc. of SIGPLAN- SIGACT Conference on Principles of Programming Languages, pp.58 70, [8] A. Stump, C. Barret, and D. Dill, CVC: a Cooperating Validity Checker, Proc. of 14th International Conference on Computer-aided Verification, pp , [9] M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, Chaff: Engineering an Efficient SAT Solver, Proc. of Design Automation Conference 01, [10] SystemC: [11] CodeSurfer: [12] MPEG Software Simulation Group: [13] J. Daemen and V. Rijmen, AES Proposal: Rijndael, Document Version 2, Sep