UVM in System C based verification
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1 April, 2016 Test Experiences and Verification of implementing Solutions UVM in System C based verification Delivering Tailored Solutions for Hardware Verification and Software Testing
2 EMPLOYEES TVS - Global Leaders in Test and Verification Germany UK USA France India China South Korea Singapore Continuous geographical expansion Number of Employees by quarter Q3-13 Q4-13 Q1-14 Q2-14 Q3-14 Q4-14 Q1-15 Q2-15 Q3-15 Q4-15 Q1-16 Q2-16 (Est.) CALENDAR YEAR Q3-16 (Est.) Q4-16 (Est.) Copyright TVS Limited Private & Confidential Page 2
3 Index Background and challenges The TVS approach Advantages Case study: Client Planned updates & Availability
4 Background TVS has developed a SystemC testbench that is UVM compliant with a TLM 2.0 interface Primary objectives Reusability - across projects using SystemC designs. It is also possible to reuse this on other HDL s. Advanced verification support ability to deploy advanced verification techniques IP quality demonstrable improved IP quality via metrics and bug discovery rates Copyright TVS Limited Private & Confidential Page 4
5 Challenges in Development SystemC did not have any inbuilt class libraries equivalent to the UVM class library when the development was started. SystemC inbuilt constraint based random verification features were very limited and not robust. Replication of Coverage driven verification features supported by UVM is a challenge in SystemC Due to budget constraints, proprietary tools from EDA vendors could not be used initially Copyright TVS Limited Private & Confidential Page 5
6 The TVS Development Approach Developing the C++ equivalent of UVM TVS C++ Class library (TVM) Enabling constrained random verification through CRAVE Achieving Coverage through TVS Functional Coverage Library & asuresign Copyright TVS Limited Private & Confidential Page 6
7 TVM Library Structure Copyright TVS Limited Private & Confidential Page 7
8 TVM TVS implemented a library of base methodology classes and functions in C++ enabling easy conversion of test bench and tests from TVM- >UVM or UVM->TVM The TVM library mimicked UVM phases such as compile, build, run, check etc The library includes base classes for Constraint driven randomization using CRAVE Functional coverage is enabled through a TVM Functional Coverage Library Code Coverage is enabled through gcov & lcov tools Copyright TVS Limited Private & Confidential Page 8
9 Sample Implementation Test case Agent 1 Monitor Func Coverage Driver Sequencer Seq1 DUT Agent 2 Monitor Func Coverage Virtual Sequence Driver Sequencer Seq2 Checker Scoreboard Copyright TVS Limited Private & Confidential Page 9
10 Enabling Constrained Random Verification Enabled through use of external randomization library called CRAVE The CRAVE library allows the users to set constraints in a manner similar to UVM & System Verilog CRAVE allows inline constraints, which can be formulated and changed incrementally at run-time CRAVE is freely available under the MIT license CRAVE is available via public repositories at GitHub. Copyright TVS Limited Private & Confidential Page 10
11 Achieving Coverage TVS developed a Functional Coverage Library (FCL) to enable coverage driven verification Coverage is achieved through TVM functional coverage library and asuresign* Can be used either with TVM or individually on C++ based environments Supports report generation Support for different coverage types *asuresign is TVS in-house requirements driven management and verification tool For more information, please visit Copyright TVS Limited Private & Confidential Page 11
12 Advantages of TVS approach TVM supports many UVM features Constructs for agents, monitors, drivers, sequencers and scoreboard Factory registration and overriding Randomization control using constraints Ability to raise and drop objections config_db mechanism Dynamic casting using DCAST similar to System Verilog's $cast Support for time out mechanism Reporting severity similar to UVM Uses TLM ports (interface method class) Copyright TVS Limited Private & Confidential Page 12
13 Advantages of TVS approach TVM supports System Verilog features Verbosity control of debug messages Fine process control ( like fork-join, tracking process using process handle) through System-C. Interface class Copyright TVS Limited Private & Confidential Page 13
14 UVM Features implemented in TVM Item details TVM + FCL Comments Test bench creation with component classes: agent, sequencer, driver, monitor, scoreboard, etc. Test creation with test, (virtual) sequences, etc. Yes Yes Virtual sequences with p_sequencer present in TVM but need to make them more UVM compliant Configuration and factory mechanism Phasing and objections Policies to print Policies to Compare Policies to pack, unpack, etc. Messaging and reporting Register abstraction layer Yes Yes Yes Not Present Not present Yes Not present CPP allows usage of CPP methods to do compare. But need to write own detailed method for deep compare similar to UVM for seq_items etc. Callbacks SCV callbacks Can use SCV/ CPP callbacks Coverage Groups Constrained randomization Yes SCV or CRAVE Crave is stronger, default SCV randomization not as good Copyright TVS Limited Private & Confidential Page 14
15 Initial Deployment The above methodology has been applied to block verification with the following initial results: Re-usable TVM agents were developed for the proprietary protocols based internal busses. These were re-used on subsequent IP blocks. High rates of both functional and coverage were achieved on all blocks. 100% statement coverage on all blocks. The structured feature extraction process was converted to a functional coverage model. TVS were then able to generate tests to hit 100% of the plan. Throughout the coverage closure process progress was tracked via asuresign and reports generated. 24 bugs were discovered. Copyright TVS Limited Private & Confidential Page 15
16 Portability Ported the whole environment and all the tests to Cadence SystemC simulator Some minor changes required to fix crashes For example - Conflict between global and local static variables Cadence has a list of all of the issues and coding guidelines Environment now ported and works Need to follow Cadence coding guidelines when developing tests Tests now running on RTL under the Cadence simulator Some timeouts needed fixing Copyright TVS Limited Private & Confidential Page 16
17 Future updates planned Call-backs are not implemented. For now, as it is pure C++ library, C++ call-backs can be used (Courtesy: tedfelix.com/software/c++-callbacks.html). TVS has a Virtual Sequencer with p_sequencer based mechanism but it needs further improvement to make it more compatible with methods in UVM. There is currently no UVM-RAL model equivalent. uvm_event, uvm_event_pool and message passing using these functions need to be added. The functional coverage library support needs to be extended. Copyright TVS Limited Private & Confidential Page 18
18 Bubble Sort Proof of Concept for SW Testing Program Specification Input lists of integers, floats, ascii, etc. Reject lists of mixed types Convert unsorted lists to sorted lists Can we test the program with constrained input generation? Generate valid and invalid inputs Direct generation towards corner cases Check outputs for correctness Without re-writing an identical checker program Measure what we have tested Copyright TVS Limited Private & Confidential Page 19
19 Results of Bubble Sort Proof of Concept Lists of Integers Floats Ascii etc List Generator Check output list is ordered Output list contents == input list contents Checkers Software Under Test Lists Constrain towards Empty lists Equal values Reverse ordering Coverage Metrics Empty List Reverse ordered Error cases (mix integers, floats, ascii) Etc. Copyright TVS Limited Private & Confidential Page 20
20 Results for bubble sort Copyright TVS Limited Private & Confidential Page 21
21 Application of Advanced HW verification to complex System SW Testing Robotic vacuum cleaner? Mars rover? Drone landing on ship in rough seas? Automotive Automated parking? Lane keeping assistance? Driverless cars Do we continue to perform directed testing? Hardware adopted constrained random verification And ensure requirements tracing for safety standards compliance with asuresign Copyright TVS Limited Private & Confidential Page 22
22 Availability The SystemC-UVM infrastructure developed by TVS is available for other engineers to use. Compiles to binary and can execute multiple versions in parallel. The libraries can be obtained through the TVS website: Copyright TVS Limited Private & Confidential Page 23
23 Thank You
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