1 The comparison of QC, SC and LIN

Transcription

1 Com S 611 Spring Semester 2009 Algorithms for Multiprocessor Synchronization Lecture 5: Tuesday, 3rd February 2009 Instructor: Soma Chaudhuri Scribe: Jianrong Dong 1 The comparison of QC, SC and LIN Pi Wi Ri [ read(x,0) ] Pj [ write(x,0) ] Wj Rj Figure 1: Execution 1. QC but not SC Execution 1: QC satisfied but SC unsatisfied QC is satisfied. There are two legal sequences W i R j W j R i or W j R i W i R j. Since there are no operations after the quiescent state, and QC requires precedence between those operations before and after the quiescent state. SC is unsatisfied. There are only two possible sequences W i R j W j R i or W j R i W i R j that are legal since reads get values of the most recent preceding writes. However, neither of the two sequences preserve the program order of P j or P i, respectively. Execution 2: SC is satisfied but QC is unsatisfied SC is satisfied. There is a sequence W i1 R j W i2 that satisfies the legal requirement since R j gets 1 from the most recent preceding write W i1, and it also preserves the program order for P i. Therefore it satisfies SC. QC is unsatisfied. Since there are two quiescent states, one between the WRITE s, one between the second WRITE and READ, there is only one sequence W i1 W i2 R j that satisfies the second property of QC, but it is illegal and thus does not satisfy the first property of QC. Refer to the notes from last class for definition of QC. 1

2 Wi1 Wi2 Pi [ write(x,0) ] Pj Rj Figure 2: Execution 2. SC but not QC W0 R0 x=0 [ read(y,1) ] y=0 [ write(y,1) ] W1 R1 Figure 3: Execution 3. LIN and SC are satisfied Execution 3: LIN satisfied and SC satisfied. LIN is satisfied. There is a sequence W 0 W 1 R 0 R 1 that satisfies the legal requirement for registers x and y. Also the response of writes are ahead of the invocations of reads in this sequence as well as in real time. SC is satisfied. The above sequence satisfies the legal requirement for registers x and y. Also it preserves the program order for P 0 and P 1. Execution 3 variation 1. LIN is unsatisfied and SC is satisfied. LIN is unsatisfied. If we preserve the real time order, R 0 cannot return 0 since W 1 has finished writing 1 into y. That is, the operation of register y is not legal. Therefore, LIN is not satisfied. 2

3 W0 R0 x=0 [ read(y,0) ] y=0 [ write(y,1) ] W1 R1 Figure 4: Execution 3 variation 1. LIN is unsatisfied and SC is satisfied SC is satisfied. The sequence W 0 R 0 W 1 R 1 is SC. It preserves the program order. Also since R 0 = [READ(y, 0)] reads the initial value of y(= 0), and R 1 = [READ(x, 1)] reads the value that W 0 writes, the operations of the registers are legal. W0 R0 x=0 [ read(y,0) ] y=0 [ write(y,1) ] [ read(x,0) ] W1 R1 Figure 5: Execution 3 variation 2. Neither LIN nor SC is satisfied Execution 3 variation 2. Neither LIN nor SC is satisfied. LIN is unsatisfied. If we preserve the real time order, R 0 cannot return 0 since W 1 has finished writing 1 into y. That is, the operation of register y is not legal. Similarly the operation of register x is not legal either. Therefore, LIN is not satisfied. SC is unsatisfied. Due to program order W 0 < R 0, W 1 < R 1. Due to register operation legality requirement, R 0 < W 1, R 1 < W 0. Therefore, we have W 0 < R 0 < W 1 < R 1 < W 0. Contradiction. 3

4 2 More on linearizability 2.1 Linearization points The usual way to show that a concurrent object implementation is linearizable is to identify for each method a linearization point where the method takes effect. For lock-based implementations, each method s critical section can serve as its linearization point. For implementations that do not use locking, the linearization point is typically a single step where the effects of the method call become visible to other method calls. 2.2 The nonblocking property Linearizability is a nonblocking property: a pending invocation of a total method is never required to wait for another pending invocation to complete. By definition, linearizability by itself never forces a thread with a pending invocation of a total method to block. Linearizability is an appropriate correctness condition for systems where concurrency and real-time response are important. 3 Progress conditions Definition 1 (blocking) An unexpected delay by one thread can prevent others from making progress. Definition 2 (wait-free operation) Every invocation of a wait-free operation finishes its execution in a finite number of steps. Definition 3 (wait-free object) An object is a wait-free object if all operations on that object are wait-free. Definition 4 (bounded wait-free) Every invocation of a bounded wait-free operation completes in a bounded number of steps. Note wait-free can still be unbounded. Definition 5 (nonblocking progress condition) The nonblocking progress condition means that an arbitrary and unexpected delay by one thread does not necessarily prevent the others from making progress. Wait-free is a nonblocking progress condition. However, wait-free algorithms can be inefficient and sometimes we are willing to settle for a weaker nonblocking property. Definition 6 (lock-free) A method is lock-free if it guarantees that infinitely often some invocation to this object finishes in finite number of steps. Note wait-free lock-free, but not vice versa. 4

5 3.1 Dependent progress conditions The wait-free and lock-free nonblocking progress conditions guarantee that the computation as a whole makes progress, independently of how the system schedules threads. However deadlockfree and starvation free are dependent progress conditions. deadlock-free and starvation free Definition 7 (Dependent progress conditions) Progress occurs only if the underlying platform (i.e. the operating system) provides certain guarantees. Operations rely on lock-based synchronization can guarantee, at best, dependent progress properties. There is another dependent nonblocking progress condition; the obstruction-free property. Definition 8 (Obstruction-free) dependent nonblocking progress condition. An operation is obstruction-free if, from any point after which it executes in isolation, it finishes in a finite number of steps. Obstruction-free is weaker than wait-free. Lock-free obstruction free, but not vice versa. 4 Additional Architecture prefers as weak memory consistency as possible. Programmer prefers as strong as possible. Relaxed memory consistency condition + program rules sequential consistency. It is desirable but not always achievable. We will look at results of that kind later, with different definitions for relaxed MC and program rules. 5 Read/write registers We require that our register implementations to be wait-free. We address the following fundamental question: Can any data structure implemented from the most powerful registers we define also be implemented from the weakest? Three properties are discussed as follows: safe, regular and atomic. Definition 9 (safe) A single-writer, multiple-reader register implementation is safe if A READ that does not overlap a WRITE call returns the value written by the most recent WRITE. 5

6 If a READ overlaps a WRITE, then given the possible values of register {0,..., m 1}, READ returns v {0,..., m 1} regardless what is being written. Definition 10 (regular) A regular register is a multi-reader, single-writer register when writes do not happen atomically. A regular register is safe, so any READ that does not overlap a WRITE call returns the most recently written value. If a READ overlaps one or more WRITE. READ returns value of last preceding WRITE or any overlapping WRITE. 0 [ WRITE 1 ] [ WRITE 2 ] [ READ v1 ] [ READ v2 ] Figure 6: Regular register Note for a regular register v 1 {0, 1, 2} corresponding to one most recent preceding WRITE and two overlapping WRITE. v 2 {1, 2} corresponding to one most recent preceding WRITE and one overlapping WRITE. Definition 11 (atomic) An single-reader single-writer atomic register is a linearizable implementation of the sequential register class. Any concurrent operations can be linearized, taking one spot of time of its READ or WRITE operation. Informally an atomic register behaves exactly as we would expect: each read returns the last value written. In the above example. For an atomic register, if v 1 = 0, v 2 = {1, 2}; if v 1 = 1, v 2 = {1, 2}; if v 1 = 2, v 2 = Construct a multi-reader register Registers can be safe, regular, or atomic, or they can be binary or k-ary. They can have single or multiple reader, and single or multiple writer. We try to construct a multi-reader single-writer register (MRSW) with single-reader single-writer binary safe registers (SRSW). Note the big rectangle is for the MRSW while the small one is for the SRSW s. The MRSW register has the following properties. If SRSW is safe, MRSW is safe. 6

7 R1 V R2 V W Rn V Figure 7: Construct MRSW register with SRSW registers If SRSW is regular, MRSW is regular. For proof, please refer to the notes for the next class. Atomic is a problem. Since the single writer needs to write into different SRSW s, although each write individually is atomic, the whole writing process is not atomic. During the writing process, some READ gets old value because WRITE has not updated its corresponding SRSW yet, while some gets new value as WRITE has updated its corresponding register. 7