Intel 64 and IA-32 Architectures Software Developer s Manual

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1 Intel 64 and IA-32 Architectures Software Developer s Manual Volume 1: Basic Architecture NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of five volumes: Basic Architecture, Order Number ; Instruction Set Reference A-M, Order Number ; Instruction Set Reference N-Z, Order Number ; System Programming Guide, Part 1, Order Number ; System Programming Guide, Part 2, Order Number Refer to all five volumes when evaluating your design needs. Order Number: US September 2008

2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT- ED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Developers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Improper use of reserved or undefined features or instructions may cause unpredictable behavior or failure in developer's software code when running on an Intel processor. Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use. The Intel 64 architecture processors may contain design defects or errors known as errata. Current characterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel processor supporting Hyper- Threading Technology and an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information, see including details on which processors support HT Technology. Intel Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations. Intel Virtualization Technology-enabled BIOS and VMM applications are currently in development. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64 architecture. Processors will not operate (including 32-bit operation) without an Intel 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo, Intel Core 2 Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, Intel Atom, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO or call or visit Intel s website at Copyright Intel Corporation

3 CONTENTS CHAPTER 1 ABOUT THIS MANUAL 1.1 INTEL 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL OVERVIEW OF VOLUME 1: BASIC ARCHITECTURE NOTATIONAL CONVENTIONS Bit and Byte Order Reserved Bits and Software Compatibility Instruction Operands Hexadecimal and Binary Numbers Segmented Addressing A New Syntax for CPUID, CR, and MSR Values Exceptions RELATED LITERATURE CHAPTER 2 INTEL 64 AND IA-32 ARCHITECTURES 2.1 BRIEF HISTORY OF INTEL 64 AND IA-32 ARCHITECTURE bit Processors and Segmentation (1978) The Intel 286 Processor (1982) The Intel386 Processor (1985) The Intel486 Processor (1989) The Intel Pentium Processor (1993) The P6 Family of Processors ( ) The Intel Pentium 4 Processor Family ( ) The Intel Xeon Processor ( ) The Intel Pentium M Processor (2003-Current) The Intel Pentium Processor Extreme Edition ( ) The Intel Core Duo and Intel Core Solo Processors ( ) The Intel Xeon Processor 5100, 5300 Series and Intel Core 2 Processor Family (2006-Current) The Intel Xeon Processor 5200, 5400, 7400 Series and Intel Core 2 Processor Family (2007-Current) The Intel Atom Processor Family (2008-Current) MORE ON SPECIFIC ADVANCES P6 Family Microarchitecture Intel NetBurst Microarchitecture The Front End Pipeline Out-Of-Order Execution Core Retirement Unit Intel Core Microarchitecture The Front End Execution Core Intel Atom Microarchitecture SIMD Instructions PAGE Vol. 1 iii

4 CONTENTS Hyper-Threading Technology Some Implementation Notes Multi-Core Technology Intel 64 Architecture Intel Virtualization Technology (Intel VT) INTEL 64 AND IA-32 PROCESSOR GENERATIONS CHAPTER 3 BASIC EXECUTION ENVIRONMENT 3.1 MODES OF OPERATION Intel 64 Architecture OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT Bit Mode Execution Environment MEMORY ORGANIZATION IA-32 Memory Models Paging and Virtual Memory Memory Organization in 64-Bit Mode Modes of Operation vs. Memory Model Bit and 16-Bit Address and Operand Sizes Extended Physical Addressing in Protected Mode Address Calculations in 64-Bit Mode Canonical Addressing BASIC PROGRAM EXECUTION REGISTERS General-Purpose Registers General-Purpose Registers in 64-Bit Mode Segment Registers Segment Registers in 64-Bit Mode EFLAGS Register Status Flags DF Flag System Flags and IOPL Field RFLAGS Register in 64-Bit Mode INSTRUCTION POINTER Instruction Pointer in 64-Bit Mode OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES Operand Size and Address Size in 64-Bit Mode OPERAND ADDRESSING Immediate Operands Register Operands Register Operands in 64-Bit Mode Memory Operands Memory Operands in 64-Bit Mode Specifying a Segment Selector Segmentation in 64-Bit Mode Specifying an Offset Specifying an Offset in 64-Bit Mode Assembler and Compiler Addressing Modes PAGE iv Vol. 1

5 CONTENTS I/O Port Addressing CHAPTER 4 DATA TYPES 4.1 FUNDAMENTAL DATA TYPES Alignment of Words, Doublewords, Quadwords, and Double Quadwords NUMERIC DATA TYPES Integers Unsigned Integers Signed Integers Floating-Point Data Types POINTER DATA TYPES Pointer Data Types in 64-Bit Mode BIT FIELD DATA TYPE STRING DATA TYPES PACKED SIMD DATA TYPES Bit SIMD Packed Data Types Bit Packed SIMD Data Types BCD AND PACKED BCD INTEGERS REAL NUMBERS AND FLOATING-POINT FORMATS Real Number System Floating-Point Format Normalized Numbers Biased Exponent Real Number and Non-number Encodings Signed Zeros Normalized and Denormalized Finite Numbers Signed Infinities NaNs Operating on SNaNs and QNaNs Using SNaNs and QNaNs in Applications QNaN Floating-Point Indefinite Rounding Rounding Control (RC) Fields Truncation with SSE and SSE2 Conversion Instructions OVERVIEW OF FLOATING-POINT EXCEPTIONS Floating-Point Exception Conditions Invalid Operation Exception (#I) Denormal Operand Exception (#D) Divide-By-Zero Exception (#Z) Numeric Overflow Exception (#O) Numeric Underflow Exception (#U) Inexact-Result (Precision) Exception (#P) Floating-Point Exception Priority Typical Actions of a Floating-Point Exception Handler PAGE Vol. 1 v

6 CONTENTS CHAPTER 5 INSTRUCTION SET SUMMARY 5.1 GENERAL-PURPOSE INSTRUCTIONS Data Transfer Instructions Binary Arithmetic Instructions Decimal Arithmetic Instructions Logical Instructions Shift and Rotate Instructions Bit and Byte Instructions Control Transfer Instructions String Instructions I/O Instructions Enter and Leave Instructions Flag Control (EFLAG) Instructions Segment Register Instructions Miscellaneous Instructions X87 FPU INSTRUCTIONS x87 FPU Data Transfer Instructions x87 FPU Basic Arithmetic Instructions x87 FPU Comparison Instructions x87 FPU Transcendental Instructions x87 FPU Load Constants Instructions x87 FPU Control Instructions X87 FPU AND SIMD STATE MANAGEMENT INSTRUCTIONS MMX INSTRUCTIONS MMX Data Transfer Instructions MMX Conversion Instructions MMX Packed Arithmetic Instructions MMX Comparison Instructions MMX Logical Instructions MMX Shift and Rotate Instructions MMX State Management Instructions SSE INSTRUCTIONS SSE SIMD Single-Precision Floating-Point Instructions SSE Data Transfer Instructions SSE Packed Arithmetic Instructions SSE Comparison Instructions SSE Logical Instructions SSE Shuffle and Unpack Instructions SSE Conversion Instructions SSE MXCSR State Management Instructions SSE 64-Bit SIMD Integer Instructions SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions SSE2 INSTRUCTIONS SSE2 Packed and Scalar Double-Precision Floating-Point Instructions SSE2 Data Movement Instructions SSE2 Packed Arithmetic Instructions PAGE vi Vol. 1

7 CONTENTS SSE2 Logical Instructions SSE2 Compare Instructions SSE2 Shuffle and Unpack Instructions SSE2 Conversion Instructions SSE2 Packed Single-Precision Floating-Point Instructions SSE2 128-Bit SIMD Integer Instructions SSE2 Cacheability Control and Ordering Instructions SSE3 INSTRUCTIONS SSE3 x87-fp Integer Conversion Instruction SSE3 Specialized 128-bit Unaligned Data Load Instruction SSE3 SIMD Floating-Point Packed ADD/SUB Instructions SSE3 SIMD Floating-Point Horizontal ADD/SUB Instructions SSE3 SIMD Floating-Point LOAD/MOVE/DUPLICATE Instructions SSE3 Agent Synchronization Instructions SUPPLEMENTAL STREAMING SIMD EXTENSIONS 3 (SSSE3) INSTRUCTIONS Horizontal Addition/Subtraction Packed Absolute Values Multiply and Add Packed Signed and Unsigned Bytes Packed Multiply High with Round and Scale Packed Shuffle Bytes Packed Sign Packed Align Right SSE4 INSTRUCTIONS SSE4.1 INSTRUCTIONS Dword Multiply Instructions Floating-Point Dot Product Instructions Streaming Load Hint Instruction Packed Blending Instructions Packed Integer MIN/MAX Instructions Floating-Point Round Instructions with Selectable Rounding Mode Insertion and Extractions from XMM Registers Packed Integer Format Conversions Improved Sums of Absolute Differences (SAD) for 4-Byte Blocks Horizontal Search Packed Test Packed Qword Equality Comparisons Dword Packing With Unsigned Saturation SSE4.2 INSTRUCTION SET String and Text Processing Instructions Packed Comparison SIMD integer Instruction Application-Targeted Accelerator Instructions SYSTEM INSTRUCTIONS BIT MODE INSTRUCTIONS VIRTUAL-MACHINE EXTENSIONS SAFER MODE EXTENSIONS PAGE Vol. 1 vii

8 CONTENTS CHAPTER 6 PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS 6.1 PROCEDURE CALL TYPES STACKS Setting Up a Stack Stack Alignment Address-Size Attributes for Stack Accesses Procedure Linking Information Stack-Frame Base Pointer Return Instruction Pointer Stack Behavior in 64-Bit Mode CALLING PROCEDURES USING CALL AND RET Near CALL and RET Operation Far CALL and RET Operation Parameter Passing Passing Parameters Through the General-Purpose Registers Passing Parameters on the Stack Passing Parameters in an Argument List Saving Procedure State Information Calls to Other Privilege Levels CALL and RET Operation Between Privilege Levels Branch Functions in 64-Bit Mode INTERRUPTS AND EXCEPTIONS Call and Return Operation for Interrupt or Exception Handling Procedures Calls to Interrupt or Exception Handler Tasks Interrupt and Exception Handling in Real-Address Mode INT n, INTO, INT 3, and BOUND Instructions Handling Floating-Point Exceptions Interrupt and Exception Behavior in 64-Bit Mode PROCEDURE CALLS FOR BLOCK-STRUCTURED LANGUAGES ENTER Instruction LEAVE Instruction CHAPTER 7 PROGRAMMING WITH GENERAL-PURPOSE INSTRUCTIONS 7.1 PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS PROGRAMMING ENVIRONMENT FOR GP INSTRUCTIONS IN 64-BIT MODE SUMMARY OF GP INSTRUCTIONS Data Transfer Instructions General Data Movement Instructions Exchange Instructions Exchange Instructions in 64-Bit Mode Stack Manipulation Instructions Stack Manipulation Instructions in 64-Bit Mode Type Conversion Instructions Type Conversion Instructions in 64-Bit Mode PAGE viii Vol. 1

9 CONTENTS Binary Arithmetic Instructions Addition and Subtraction Instructions Increment and Decrement Instructions Increment and Decrement Instructions in 64-Bit Mode Comparison and Sign Change Instruction Multiplication and Divide Instructions Decimal Arithmetic Instructions Packed BCD Adjustment Instructions Unpacked BCD Adjustment Instructions Decimal Arithmetic Instructions in 64-Bit Mode Logical Instructions Shift and Rotate Instructions Shift Instructions Double-Shift Instructions Rotate Instructions Bit and Byte Instructions Bit Test and Modify Instructions Bit Scan Instructions Byte Set on Condition Instructions Test Instruction Control Transfer Instructions Unconditional Transfer Instructions Conditional Transfer Instructions Control Transfer Instructions in 64-Bit Mode Software Interrupt Instructions Software Interrupt Instructions in 64-bit Mode and Compatibility Mode String Operations Repeating String Operations String Operations in 64-Bit Mode Repeating String Operations in 64-bit Mode I/O Instructions I/O Instructions in 64-Bit Mode Enter and Leave Instructions Flag Control (EFLAG) Instructions Carry and Direction Flag Instructions EFLAGS Transfer Instructions Interrupt Flag Instructions Flag Control (RFLAG) Instructions in 64-Bit Mode Segment Register Instructions Segment-Register Load and Store Instructions Far Control Transfer Instructions Software Interrupt Instructions Load Far Pointer Instructions Miscellaneous Instructions Address Computation Instruction Table Lookup Instructions Processor Identification Instruction PAGE Vol. 1 ix

10 CONTENTS No-Operation and Undefined Instructions CHAPTER 8 PROGRAMMING WITH THE X87 FPU 8.1 X87 FPU EXECUTION ENVIRONMENT x87 FPU in 64-Bit Mode and Compatibility Mode x87 FPU Data Registers Parameter Passing With the x87 FPU Register Stack x87 FPU Status Register Top of Stack (TOP) Pointer Condition Code Flags x87 FPU Floating-Point Exception Flags Stack Fault Flag Branching and Conditional Moves on Condition Codes x87 FPU Control Word x87 FPU Floating-Point Exception Mask Bits Precision Control Field Rounding Control Field Infinity Control Flag x87 FPU Tag Word x87 FPU Instruction and Data (Operand) Pointers Last Instruction Opcode Fopcode Compatibility Sub-mode Saving the x87 FPU s State with FSTENV/FNSTENV and FSAVE/FNSAVE Saving the x87 FPU s State with FXSAVE X87 FPU DATA TYPES Indefinites Unsupported Double Extended-Precision Floating-Point Encodings and Pseudo-Denormals X86 FPU INSTRUCTION SET Escape (ESC) Instructions x87 FPU Instruction Operands Data Transfer Instructions Load Constant Instructions Basic Arithmetic Instructions Comparison and Classification Instructions Branching on the x87 FPU Condition Codes Trigonometric Instructions Pi Logarithmic, Exponential, and Scale Transcendental Instruction Accuracy x87 FPU Control Instructions Waiting vs. Non-waiting Instructions Unsupported x87 FPU Instructions X87 FPU FLOATING-POINT EXCEPTION HANDLING Arithmetic vs. Non-arithmetic Instructions X87 FPU FLOATING-POINT EXCEPTION CONDITIONS PAGE x Vol. 1

11 CONTENTS Invalid Operation Exception Stack Overflow or Underflow Exception (#IS) Invalid Arithmetic Operand Exception (#IA) Denormal Operand Exception (#D) Divide-By-Zero Exception (#Z) Numeric Overflow Exception (#O) Numeric Underflow Exception (#U) Inexact-Result (Precision) Exception (#P) X87 FPU EXCEPTION SYNCHRONIZATION HANDLING X87 FPU EXCEPTIONS IN SOFTWARE Native Mode MS-DOS* Compatibility Sub-mode Handling x87 FPU Exceptions in Software CHAPTER 9 PROGRAMMING WITH INTEL MMX TECHNOLOGY 9.1 OVERVIEW OF MMX TECHNOLOGY THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT MMX Technology in 64-Bit Mode and Compatibility Mode MMX Registers MMX Data Types Memory Data Formats Single Instruction, Multiple Data (SIMD) Execution Model SATURATION AND WRAPAROUND MODES MMX INSTRUCTIONS Data Transfer Instructions Arithmetic Instructions Comparison Instructions Conversion Instructions Unpack Instructions Logical Instructions Shift Instructions EMMS Instruction COMPATIBILITY WITH X87 FPU ARCHITECTURE MMX Instructions and the x87 FPU Tag Word WRITING APPLICATIONS WITH MMX CODE Checking for MMX Technology Support Transitions Between x87 FPU and MMX Code Using the EMMS Instruction Mixing MMX and x87 FPU Instructions Interfacing with MMX Code Using MMX Code in a Multitasking Operating System Environment Exception Handling in MMX Code Register Mapping Effect of Instruction Prefixes on MMX Instructions PAGE Vol. 1 xi

12 CONTENTS CHAPTER 10 PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE) 10.1 OVERVIEW OF SSE EXTENSIONS SSE PROGRAMMING ENVIRONMENT SSE in 64-Bit Mode and Compatibility Mode XMM Registers MXCSR Control and Status Register SIMD Floating-Point Mask and Flag Bits SIMD Floating-Point Rounding Control Field Flush-To-Zero Denormals-Are-Zeros Compatibility of SSE Extensions with SSE2/SSE3/MMX and the x87 FPU SSE DATA TYPES SSE INSTRUCTION SET SSE Packed and Scalar Floating-Point Instructions SSE Data Movement Instructions SSE Arithmetic Instructions SSE Logical Instructions SSE Comparison Instructions SSE Shuffle and Unpack Instructions SSE Conversion Instructions SSE 64-Bit SIMD Integer Instructions MXCSR State Management Instructions Cacheability Control, Prefetch, and Memory Ordering Instructions Cacheability Control Instructions Caching of Temporal vs. Non-Temporal Data PREFETCHh Instructions SFENCE Instruction FXSAVE AND FXRSTOR INSTRUCTIONS HANDLING SSE INSTRUCTION EXCEPTIONS WRITING APPLICATIONS WITH THE SSE EXTENSIONS CHAPTER 11 PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2) 11.1 OVERVIEW OF SSE2 EXTENSIONS SSE2 PROGRAMMING ENVIRONMENT SSE2 in 64-Bit Mode and Compatibility Mode Compatibility of SSE2 Extensions with SSE, MMX Technology and x87 FPU Programming Environment Denormals-Are-Zeros Flag SSE2 DATA TYPES SSE2 INSTRUCTIONS Packed and Scalar Double-Precision Floating-Point Instructions Data Movement Instructions SSE2 Arithmetic Instructions PAGE xii Vol. 1

13 CONTENTS SSE2 Logical Instructions SSE2 Comparison Instructions SSE2 Shuffle and Unpack Instructions SSE2 Conversion Instructions SSE2 64-Bit and 128-Bit SIMD Integer Instructions Bit SIMD Integer Instruction Extensions Cacheability Control and Memory Ordering Instructions FLUSH Cache Line Cacheability Control Instructions Memory Ordering Instructions Pause Branch Hints SSE, SSE2, AND SSE3 EXCEPTIONS SIMD Floating-Point Exceptions SIMD Floating-Point Exception Conditions Invalid Operation Exception (#I) Denormal-Operand Exception (#D) Divide-By-Zero Exception (#Z) Numeric Overflow Exception (#O) Numeric Underflow Exception (#U) Inexact-Result (Precision) Exception (#P) Generating SIMD Floating-Point Exceptions Handling Masked Exceptions Handling Unmasked Exceptions Handling Combinations of Masked and Unmasked Exceptions Handling SIMD Floating-Point Exceptions in Software Interaction of SIMD and x87 FPU Floating-Point Exceptions WRITING APPLICATIONS WITH SSE/SSE2 EXTENSIONS General Guidelines for Using SSE/SSE2 Extensions Checking for SSE/SSE2 Support Checking for the DAZ Flag in the MXCSR Register Initialization of SSE/SE2 Extensions Saving and Restoring the SSE/SSE2 State Guidelines for Writing to the MXCSR Register Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions Compatibility of SIMD and x87 FPU Floating-Point Data Types Mixing Packed and Scalar Floating-Point and 128-Bit SIMD Integer Instructions and Data Interfacing with SSE/SSE2 Procedures and Functions Passing Parameters in XMM Registers Saving XMM Register State on a Procedure or Function Call Caller-Save Requirement for Procedure and Function Calls Updating Existing MMX Technology Routines Using 128-Bit SIMD Integer Instructions Branching on Arithmetic Operations Cacheability Hint Instructions Effect of Instruction Prefixes on the SSE/SSE2 Instructions PAGE Vol. 1 xiii

14 CONTENTS CHAPTER 12 PROGRAMMING WITH SSE3, SSSE3, AND SSE PROGRAMMING ENVIRONMENT AND DATA TYPES SSE3, SSSE3, SSE4 in 64-Bit Mode and Compatibility Mode Compatibility of SSE3/SSSE3 with MMX Technology, the x87 FPU Environment, and SSE/SSE2 Extensions Horizontal and Asymmetric Processing OVERVIEW OF SSE3 INSTRUCTIONS SSE3 INSTRUCTIONS x87 FPU Instruction for Integer Conversion SIMD Integer Instruction for Specialized 128-bit Unaligned Data Load SIMD Floating-Point Instructions That Enhance LOAD/MOVE/DUPLICATE Performance SIMD Floating-Point Instructions Provide Packed Addition/Subtraction SIMD Floating-Point Instructions Provide Horizontal Addition/Subtraction Two Thread Synchronization Instructions WRITING APPLICATIONS WITH SSE3 EXTENSIONS Guidelines for Using SSE3 Extensions Checking for SSE3 Support Enable FTZ and DAZ for SIMD Floating-Point Computation Programming SSE3 with SSE/SSE2 Extensions OVERVIEW OF SSSE3 INSTRUCTIONS SSSE3 INSTRUCTIONS Horizontal Addition/Subtraction Packed Absolute Values Multiply and Add Packed Signed and Unsigned Bytes Packed Multiply High with Round and Scale Packed Shuffle Bytes Packed Sign Packed Align Right WRITING APPLICATIONS WITH SSSE3 EXTENSIONS Guidelines for Using SSSE3 Extensions Checking for SSSE3 Support SSE3/SSSE3 AND SSE4 EXCEPTIONS Device Not Available (DNA) Exceptions Numeric Error flag and IGNNE# Emulation IEEE 754 Compliance of SSE4.1 Floating-Point Instructions SSE4 OVERVIEW SSE4.1 INSTRUCTION SET Dword Multiply Instructions Floating-Point Dot Product Instructions Streaming Load Hint Instruction Packed Blending Instructions Packed Integer MIN/MAX Instructions Floating-Point Round Instructions with Selectable Rounding Mode Insertion and Extractions from XMM Registers PAGE xiv Vol. 1

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