Tailoring the 32Bit ALU to MIPS

 Alicia Briggs
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1 Tailoring the 32Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance Performance vs. cost Carry lookahead adder Implementation alternatives Branch Instructions beq $t5, $t6, L Use subtraction: (ab) = 0 implies a = b Add hardware to test if the result is 0 OR all 32 results and invert the OR output ZERO = (Result 1 + Result Result 31 ) Note: Signal ZERO is a 1 when the result is zero! 1
2 Branch Support 1 (A = B) 0 otherwise Shift instructions SLL, SRL, and SRA We need a data line for a shifter (L and R) However, shifters are much more easily implemented at the transistor level (outside the ALU) Barrel shifters x 3 x 2 x 1 x 0 Diagonal closed switch pattern controlled by the control unit x 3 x 2 x 1 x 0 x 2 x 1 x x 3 x 2 x 1 Output, x Output, x<<1 Output, x>>1 2
3 Immediate Instructions First input to ALU is the first register (rs) Second input Data from register (rt) Zero or singextended immediate Add a mux at second input of ALU rs rt ALU Registers Sign extend IR: 16 Control Unit Result Zero Overflow Memory address Slt rd, rs, rt rd: Slt Instruction r 1 if (rs < rt) 0 else A < B => A B < 0 1. Perform subtraction using full adder 2. Check highestorder bit (sign bit) 3. Sign bit tells us whether A < B New input line (Less) goes directly to mux New control code for slt Result for slt is not the output from ALU Need a new 1bit ALU for the most significant bit It has a new output line (Set) used only for slt (Overflow detection logic is also associated with this bit) 3
4 First bit (LSB) Slt Support Sign bit What is the control code for slt? Overview I instruction 32bit memory address 4
5 ALU Performance Hardware executes in parallel Is a 32bit ALU as fast as a 1bit ALU? Speed vs. Cost Fewer sequential gates vs. number of gates Two extremes to do addition Ripple carry and sumofproducts How could you get rid of the ripple? carrylookahead adder c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 c 2 = c 2 (a 0,b 0,c 0,a 1,b 1 ) c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 c 3 = c 3 (a 0,b 0,c 0,a 1,b 1,a 2,b 2 ) c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 c 4 = c 4 (a 0,b 0,c 0,a 1,b 1,a 2,b 2,a 3,b 3 ) Not feasible! Too many inputs to the gates Conclusions We can build an ALU to support the MIPS ISA Key Idea: Use multiplexer to select ALU output Subtraction uses two s complement addition Replicate 1bit ALU to produce 32bit ALU Important points about hardware All of the gates in the ALU work in parallel The speed of a gate is affected by the number of inputs Speed of a circuit is affected by the number of gates in series (on the critical path or the deepest level of logic) Our primary focus: (conceptual) Clever changes to organization can improve performance (similar to using better algorithms in software) 5
6 Review: 32bit ALU 1bit ALU Requirements: Control codes operations Datapath rs rt Registers Sign extend 16 Datapath for ALU instructions lw/sw instructions Imm instructions Branch instructions IR: ALU Control Unit Result Zero Overflow Memory address 6
7 3.3 Multiplication More complicated than addition Accomplished via shifting and addition Requires more time and chip area 3 versions of pencilandpaper algorithm 0010 (multiplicand) x_1011 (multiplier) > copy & shift (multiplicand to left) > copy & shift > shift > copy & shift Sum Partial Products First Version (V.1)
8 V.1: Hardware Multiplicand (64 bits) Shift left Problems: half of the bits of multiplicand are always 0 Wasteful, slow 64bit ALU Product (64 bits) Write Multiplier (32 bits) Shift right Multiplier0 Control test V.1: Hardware 8
9 Steps Unsigned multiplication: Shiftandadd Generate one partial product for each digit in the multiplier Partial product = 0 If multiplier digit = 0 Multiplicand If multiplier digit = 1 Total product = sum of (left shifted) partial products The multiplication of two nbit binary integers results in a product of up to 2n bits in length Signed multiplication Convert them to positive numbers and remember the original signs. Need to extend sign of the product there are better techniques Second Version (V.2) Multiplicand Start 32 bits 32bit ALU Multiplier Shift right Multiplier0 = 1 1. Test Multiplier0 Multiplier0 = 0 32 bits Product 64 bits Shift right Write Control test 1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register Product x Multiplier Shift the Product register right 1 bit 3. Shift the Multiplier register right 1 bit No: < 32 repetitions 32nd repetition? Yes: 32 repetitions Done 9
10 Final Version (V.3) Multiplicand Start 32bits Product0 = 1 1. Test Product0 Product0 = 0 32bit ALU Product 64bits Shiftright Write Product Control test x a. Add multiplicand to the left half of the product and place the result in the left half of the Product register 2. Shift the Product register right 1 bit 32nd repetition? Done No: < 32 repetitions Yes: 32 repetitions General View Multiplicand M M Multiplicand (11) x 1101 Multiplier (13) Product (143) C A Q M 32bit ALU Shift right Add Control Initial values Add Shift Shift Add Shift C A A 0 Q Q 0 4 Add Shift Multiplier 10
11 MIPS Multiplication Special purpose registers for the result (Hi, Lo) Two multiply instructions Mult: signed Multu: unsigned mflo, mfhi move contents from Hi, Lo to general purpose registers (GPRs) No overflow detection in hardware => Software overflow detection Hi must be 0 for multu or the replicated sign of Lo for mult Faster Multiplier Uses multiple adders Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel 11
12 3.4 Division Long division of unsigned binary integers Divisor Partial remainders Quotient Dividend Remainder Dividend = Quotient * Divisor + Reminder Division Hardware Initially divisor in left half Initially dividend 12
13 Optimized Divider One cycle per partialremainder subtraction Looks a lot like a multiplier! Same hardware can be used for both MIPS Multiply and divide use existing hardware ALU and shifter Extra hardware: 64bit register able to SLL/SRA Hi contains the remainder (mfhi) Lo contains the quotient (mflo) Instructions Div: signed divide Divu: unsigned divide MIPS ignores overflow? Division by 0 must be checked in software 13
14 MIPS Processor Registers 32 Sign extend M IR: ALU Sub Operation Zero Overflow Memory address Control Unit SLL/SRA Hi Lo 14
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