CPS 104 Computer Organization and Programming


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1 CPS 104 Computer Organization and Programming Lecture 9: Integer Arithmetic. Robert Wagner CPS104 IMD.1 RW Fall 2000
2 Overview of Today s Lecture: Integer Multiplication and Division. Read Appendix B CPS104 IMD.2 RW Fall 2000
3 Integer Multiplication Product = Multiplicand x Multiplier Example: 0011 x 0101 Multiplicand Multiplier Product CPS104 IMD.3 RW Fall 2000
4 Multiplication Algorithm #1 From RightLeft: If multiplier digit = 1: add (shifted) copy of multiplicand to result. If multiplier digit = 0: add 0 to result. (do nothing) 32 steps when multiplier is 32bit number. Example: 3 10 x 5 10 or x Product = Product has twice as many bits as operands CPS104 IMD.4 RW Fall 2000
5 Multiplication Algorithm #1 Start Multiplier0 = 1 1. Test Multiplier0 Multiplier0 = 0 1a. Add multiplicand to product and place the result in Product register 2. Shift the Multiplicand register left 1 bit 3. Shift the Multiplier register right 1 bit 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done Figure Copyright Morgan Kaufmann CPS104 IMD.5 RW Fall 2000
6 Multiplication Hardware #1 Multiplicand starts in right half of register Multiplicand 64 bits Shift left 64bit ALU Multiplier Shift right 32 bits Product 64 bits Write Control test Figure Copyright Morgan Kaufmann CPS104 IMD.6 RW Fall 2000
7 Multiplication Hardware #2 Shift Multiplicand Left works same as Shift Product Right Only need 32 bits for multiplicand Multiplicand 32 bits 32bit ALU Multiplier Shift right 32 bits Product 64 bits Shift right Write Control test Possible to combine multiplier and product registers Keep multiplier in low order 32 bits of product register Figure Copyright Morgan Kaufmann CPS104 IMD.7 RW Fall 2000
8 Multiplication Algorithm #2 Start Multiplier0 = 1 1. Test Multiplier0 Multiplier0 = 0 1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register 2. Shift the Product register right 1 bit 3. Shift the Multiplier register right 1 bit 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done Figure Copyright Morgan Kaufmann CPS104 IMD.8 RW Fall 2000
9 Signed Multiplication II Overflow can occur during the addition step Solution: Make the product register one bit longer Recall that the highorder bit of the multiplier has NEGATIVE weight If the highorder bit of the multiplier is 1, SUBTRACT the multiplicand from the product, instead of adding it CPS104 IMD.9 RW Fall 2000
10 Multiplication Examples (4 bit operands) * * * * subtract subtract = 3*16+17*7 = 49 ( ) 7*7 = 49 CPS104 IMD.10 RW Fall 2000
11 Booth Encoding Observation: Can write number as difference of two numbers. In particular: Can replace a string of 1s with initial subtract when we see a 1, and then an add when we see the bit AFTER the last 1 Example 1: = = Example 2: = = ( ) + ( ) = ( ) + ( ) Works for signed numbers as well! CPS104 IMD.11 RW Fall 2000
12 Booth s Algorithm Similar to previous multiply algorithm. (Current, Previous) bits of Multiplier: 0,0: middle of string of 0s; do nothing 0,1: end of a string of 1s; add multiplicand 1,0; start of string of 1s; subtract multiplicand 1,1: middle of string of 1s; do nothing Shift Product/Multiplier right 1 bit (as before) CPS104 IMD.12 RW Fall 2000
13 Booth Multiplication Examples (4 bit operands) * * * * x x x x x x = 3*16+1 ( ) 7*7 = 497*7 = 49 CPS104 IMD.13 RW Fall 2000
14 Signed Multiplication Convert negative numbers to positive and remember the original signs. In 2scomplement, can multiply directly using a 1bit longer product register Sign extend when shifting Subtract instead of adding on last step Or, use Booth s algorithm Sign extend when shifting CPS104 IMD.14 RW Fall 2000
15 Integer Division Dividend = Quotient x Divisor + Remainder Example: 1,001,010 ten / 1000 ten ten Quotient Divisor 1000 ten ten Dividend ten Remainder Compare shifted divisor and remainder, subtract only if divisor<=remainder CPS104 IMD.15 RW Fall 2000
16 Division Hardware #1 Dividend starts in Remainder register Divisor starts in left half of divisor register Comparison requires extra hardware, not shown, or extra steps Divisor Shift right 64 bits 64bit ALU Quotient Shift left 32 bits Remainder 64 bits Write Control test Figure Copyright Morgan Kaufmann CPS104 IMD.16 RW Fall 2000
17 Division (contd.) Similar to multiplication Shift remainder left instead of shifting divisor right Combine quotient register with right half of remainder register Signed Division Remember the signs and negate quotient if different. Make sign of remainder match the dividend Same hardware can be used for both multiply and divide. Need 64bit register that can shift left and right ALU that adds or subtracts Optimizations possible CPS104 IMD.17 RW Fall 2000
18 Summary Both multiplication and division are MULTISTEP algorithms Multiplication takes some 32 steps, each about 1 cycle Division may take twice as long Some optimizations are possible Multiplication in about 9 cycles (32bit operands) Division in about 32 Each algorithm uses one 64bit register, usually split into a HI 32bit part, and a LO 32bit part MIPS uses MFHI and MFLO operations to read these Both operations (and MOD) are SLOW compared to ADD CPS104 IMD.18 RW Fall 2000
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