# Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

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1 Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point EEL-4713 Ann Gordon-Ross.1 EEL-4713 Ann Gordon-Ross.2 Deriving requirements of ALU with instruction set architecture: must be able to do all operations in ISA Tradeoffs of cost and speed based on frequency of occurrence, hardware budget MIPS ISA MIPS arithmetic instructions Instruction Example Meaning Comments add add \$1,\$2,\$3 \$1 = \$2 + \$3 3 operands; exception possible subtract sub \$1,\$2,\$3 \$1 = \$2 \$3 3 operands; exception possible add immediate addi \$1,\$2,100 \$1 = \$ constant; exception possible add unsigned addu \$1,\$2,\$3 \$1 = \$2 + \$3 3 operands; no exceptions subtract unsigned subu \$1,\$2,\$3 \$1 = \$2 \$3 3 operands; no exceptions add imm. unsign. addiu \$1,\$2,100 \$1 = \$ constant; no exceptions multiply mult \$2,\$3 Hi, Lo = \$2 x \$3 64-bit signed product multiply unsigned multu\$2,\$3 Hi, Lo = \$2 x \$3 64-bit unsigned product divide div \$2,\$3 Lo = \$2 \$3, Lo = quotient, Hi = remainder Hi = \$2 mod \$3 divide unsigned divu \$2,\$3 Lo = \$2 \$3, Unsigned quotient & remainder Hi = \$2 mod \$3 Move from Hi mfhi \$1 \$1 = Hi Used to get copy of Hi Move from Lo mflo \$1 \$1 = Lo Used to get copy of Lo EEL-4713 Ann Gordon-Ross.3 EEL-4713 Ann Gordon-Ross.4

2 MIPS ALU requirements Additional MIPS ALU requirements Add, AddU, Sub, SubU, AddI, AddIU => 2 s complement adder with overflow detection & inverter SLTI, SLTIU (set less than) => 2 s complement adder with inverter, check sign bit of result BEQ, BNE (branch on equal or not equal) => 2 s complement adder with inverter, check if result = 0 And, Or, AndI, OrI => Logical AND, logical OR ALU from last lecture supports these ops Xor, Nor, XorI => Logical XOR, logical NOR Sll, Srl, Sra => Need left shift, right shift, right shift arithmetic by 0 to 31 bits Mult, MultU, Div, DivU => Need 32-bit multiply and divide, signed and unsigned EEL-4713 Ann Gordon-Ross.5 EEL-4713 Ann Gordon-Ross.6 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 Multiplier Product Unsigned Combinational Multiplier: A * B Ai Prev Bj Cout Ai+Prev Control bits B 0 B 1 B 2 m bits x n bits = m+n bit product Binary makes it easy: 0 => place 0 ( 0 x multiplicand) 1 => place a copy ( 1 x multiplicand) 4 versions of multiply hardware & algorithm: successive refinement P 7 P 6 Stage i accumulates A * 2 i if B i == 1 P 5 P 4 Q: How much hardware for 32 bit multiplier? Critical path? P 3 P 2 P 1 P 0 B 3 Bi=0 do not add Bi=1 add EEL-4713 Ann Gordon-Ross.7 EEL-4713 Ann Gordon-Ross.8

4 Multiply Algorithm Version 1: 0011 * 0010 Potential Optimizations Multiplier[0] = 1 Multiplier[0] Multiplier[0] = 0 In state 1: Test multiplier for 0, exit Product Multiplier Multiplicand EEL-4713 Ann Gordon-Ross.13 1a. Add multiplicand to product & place the result in Product register 2. Shift the Multiplicand register left 1 bit. 3. Shift the Multiplier register right 1 bit. 4th No: < 4 repetitions Yes: 4 repetitions Observation: If multiplier[0] = 1, 2 cycles needed (add, then shifts) If multiplier[0] = 0, 1 cycle needed (shifts only) Before start, set multiplier and multiplicand intelligently EEL-4713 Ann Gordon-Ross.14 - Multiplier as smallest value? Find left-most 1 bit for each input, the right-most of those two bits is the smallest value, therefore exit sooner out of state 1 - Multiplier as least number of ones? X = and Y = If multiplier = X, 9 cycles If multiplier = Y, 13 cycles Observations on Multiply Version 1 MULTIPLY HARDWARE Version 2 1 clock per add and shifts (can shift in parallel) => 32*2 clocks per multiply Half of bits in multiplicand always 0 => 64-bit adder is wasted 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Multiplicand 0 s inserted in left of multiplicand as shifted => least significant bits of product never changed once formed 32-bit ALU 32 bits Multiplier 32 bits Shift Right Instead of shifting multiplicand to left, shift product to right? Product 64 bits Shift Right Write Control EEL-4713 Ann Gordon-Ross.15 EEL-4713 Ann Gordon-Ross.16

5 *Multiply Algorithm Version 2 What s going on? Multiplier Multiplicand Product Multiplier[0] = 1 Multiplier[0] Multiplier[0] = B 0 1a. Add multiplicand to the left half (32 MSBs) of product & place the result in the left half (32 MSBs) of Product register B 1 Product Multiplier Multiplicand Shift the Product register right 1 bit. B 2 3. Shift the Multiplier register right 1 bit. B 3 32nd No: < 32 repetitions P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 EEL-4713 Ann Gordon-Ross.17 Yes: 32 repetitions Multiplicand stays still and product moves right EEL-4713 Ann Gordon-Ross.18 Multiply Algorithm Version 2 Observations on Multiply Version 2 EEL-4713 Ann Gordon-Ross.19 Multiplier[0] = 1 Multiplier[0] 1a. Add multiplicand to the left half (32 MSBs) of product & place the result in the left half (32 MSBs) of Product register 3. Shift the Multiplier register right 1 bit. 4th No: < 4 repetitions Yes: 4 repetitions Multiplier[0] = 0 Product Multiplier Multiplicand Shift the Product register right 1 bit Wasted space in the product register exactly matches size of multiplier => combine Multiplier register and Product register 4+4=8 5+3=8 6+2=8 7+1=8 8+0=8 EEL-4713 Ann Gordon-Ross.20 Product Multiplier Multiplicand

6 MULTIPLY HARDWARE Version 3 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg, Multiplier stored in LSBs of Product) Multiplicand 32 bits Multiply Algorithm Version 3 Multiplicand Product Product[0] = 1 Product[0] 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Product[0] = 0 32-bit ALU 2. Shift the Product register right 1 bit. Hi Product (Multiplier) 64 bits Lo Shift Right Write Control 32nd No: < 32 repetitions EEL-4713 Ann Gordon-Ross.21 EEL-4713 Ann Gordon-Ross.22 Yes: 32 repetitions Observations on Multiply Version 3 MIPS registers Hi and Lo are left and right half of Product Gives us MIPS instruction MultU How can you make it faster? What about signed multiplication? easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps) apply definition of 2 s complement - need to sign-extend partial products and subtract at the end Booth s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles - can handle multiple bits at a time Representing sequences of 1s as a difference ! ! = 15 = = 16-0! n n-1 n-2 n-8! !!! 2 n +2 n n-8 = 2 n+1-2 n-8! EEL-4713 Ann Gordon-Ross.23 EEL-4713 Ann Gordon-Ross.24

7 Representing sequences of 1s as a difference Why? x = 2^n + 2^(n-1) +! + 2^k 2x = 2^(n+1) + 2^n +! + 2^(k+1) (essentially shift left 1 bit) 2x x = [2^(n+1) + 2^n +! + 2^(k+1)] [2^n + 2^(n-1) +! + 2^k] 2^n through 2^(k+1) cancel out x = 2^(n+1) 2^k Motivation for Booth s Algorithm Example 2 x 6 = 0010 x 0110: 0010 x shift (0 in multiplier) add (1 in multiplier) add (1 in multiplier) shift (0 in multiplier) Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one. How is this useful? A sequence of (n-k) 1s in a multiplier - (n-k) adds, or - 1 add and 1 sub Look at each sequence of 1s and add together EEL-4713 Ann Gordon-Ross.25 EEL-4713 Ann Gordon-Ross.26 Booth s Algorithm Insight middle end of run of run beginning of run Current Bit Bit to the Right Explanation Example 1 0 Beginning of a run of 1s Middle of a run of 1s Booth s Algorithm 1. Depending on the current and previous bits, do one of the following: 00: a. Middle of a string of 0s, so no arithmetic operations. 01: b. End of a string of 1s, so add the multiplicand to the left half of the product. 10: c. Beginning of a string of 1s, so subtract the multiplicand from the left half of the product. 11: d. Middle of a string of 1s, so no arithmetic operation. 2. As in the previous algorithm, shift the Product register right (arith) 1 bit. 0 1 End of a run of 1s Middle of a run of 0s Speed motivation if shift faster than add Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one EEL-4713 Ann Gordon-Ross.27 EEL-4713 Ann Gordon-Ross.28

8 Booth s Algorithm Multiplicand Product Product[1,0] = 01: OP=Add = 10: OP=Sub Product[1,0] = 01 or 10 Product[1,0] 1a. OP multiplicand to the left half of product & place the result in the left half of Product register Product[1,0] = 00 or Shift the Product register right 1 bit. 32nd No: < 32 repetitions Booths Example: 2 (0010) * 7 (0111) = 14 ( ) 1 extra bit for Operation Multiplicand Product comparison next? 0. initial value > sub add (-m)+1 1a. P = P - m shift P (sign ext) 1b > nop, shift > nop, shift > add 4a shift 4b done 14 EEL-4713 Ann Gordon-Ross.29 Yes: 32 repetitions EEL-4713 Ann Gordon-Ross.30 Booths Example: 2 (0010) * -3 (1101) = -6 ( ) Operation Multiplicand Product next? 0. initial value > sub 1a. P = P - m add (-m) shift P (sign ext) 1b > add a shift P 2b > sub a shift 3b > nop 4a shift 4b done MIPS logical instructions Instruction Example Meaning Comment and and \$1,\$2,\$3 \$1 = \$2 & \$3 3 reg. operands; Logical AND or or \$1,\$2,\$3 \$1 = \$2 \$3 3 reg. operands; Logical OR xor xor \$1,\$2,\$3 \$1 = \$2! \$3 3 reg. operands; Logical XOR nor nor \$1,\$2,\$3 \$1 = ~(\$2 \$3) 3 reg. operands; Logical NOR and immediate andi \$1,\$2,10 \$1 = \$2 & 10 Logical AND reg, constant or immediate ori \$1,\$2,10 \$1 = \$2 10 Logical OR reg, constant xor immediate xori \$1, \$2,10 \$1 = ~\$2 &~10 Logical XOR reg, constant shift left logical sll \$1,\$2,10 \$1 = \$2 << 10 Shift left by constant shift right logical srl \$1,\$2,10 \$1 = \$2 >> 10 Shift right by constant shift right arithm. sra \$1,\$2,10 \$1 = \$2 >> 10 Shift right (sign extend) shift left logical sllv \$1,\$2,\$3 \$1 = \$2 << \$3 Shift left by variable shift right logical srlv \$1,\$2, \$3 \$1 = \$2 >> \$3 Shift right by variable shift right arithm. srav \$1,\$2, \$3 \$1 = \$2 >> \$3 Shift right arith. by variable (sign extend) Neg. 6 EEL-4713 Ann Gordon-Ross.31 EEL-4713 Ann Gordon-Ross.32

9 Shifters Three different kinds: logical-- value shifted in is always "0" Combinational Shifter from MUXes Basic Building Block A B sel 1 0 "0" msb lsb "0" 8-bit right shifter D A 7 A 6 A 5 A 4 S 2 S 1 S 0 arithmetic-- on right shifts, sign extend msb lsb "0" EEL-4713 Ann Gordon-Ross.33 rotating-- shifted out bits are wrapped around (not in MIPS) left right msb lsb msb lsb Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted! How many levels for 32-bit shifter? EEL-4713 Ann Gordon-Ross R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 General Shift Right Scheme using 16 bit example Summary S 0 (0,1) S 1 (0, 2) S 2 (0, 4) Instruction Set drives the ALU design Multiply: successive refinement to see final design 32-bit Adder, 64-bit shift register, 32-bit Multiplicand Register Booth s algorithm to handle signed multiplies What s Missing from MIPS is Divide & Floating Point Arithmetic S 3 (0, 8) If added Right-to-left connections could support Rotate (not in MIPS but found in other ISAs) EEL-4713 Ann Gordon-Ross.35 EEL-4713 Ann Gordon-Ross.36

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