A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators"
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1 A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W ISC-V Processor with Vector Accelerators" Yunsup Lee 1, Andrew Waterman 1, imas Avizienis 1,! Henry Cook 1, Chen Sun 1,2,! Vladimir Stojanovic 1,2, Krste Asanovic 1!! 1 University of California, Berkeley! 2 Massachusetts Institute of Technology! 1!
2 Upheaval in Computer Design" Cost per Million Gates ($)! Vdd HP! Cost per Million Gates ($)" 0.045! 0.04! 0.035! 0.03! 0.025! 0.02! 0.015! 0.01! 0.005! 0! ! ! Moore s Law (cost/transistor) over?! Dennard scaling over (Vdd ~fixed)! ! 0.014! ! ! 90nm! 65nm! 40nm! 28nm! 20nm! 16/14nm! Energy efficiency constrains everything! Incorporate specialized and heterogeneous accelerators into general-purpose processors! Write processor generators to express a design space, and do vertically-integrated design space exploration extensively! Source! [1] Why migration to 20nm bulk CMOS and 16/14nm FINFETS is not the best approach for semiconductor industry, IBS, Handel Jones, 2014.! [2] International Technology oadmap of Semiconductors (ITS)! 5! 4.5! 4! 3.5! 3! 2.5! 2! 1.5! 1! 0.5! 0! Vdd HP" 2!
3 3mm X 6mm Chip Fabricated in 45nm SOI 75m+ transistors! Dual-Core ISC-V Processor with Vector Accelerators! 1MB SAM Memory Structure for Testing! Monolithically-Integrated Silicon Photonic Links" Transmitter: Wade OFC 14! eceiver: Georgas VLSI 14!! 3!
4 Chip Architecture" 3mm 2.8mm VF L1D$ 6mm 1MB SAM Array Core Logic ocket Scalar Core L1I$ L1VI$ Hwacha Vector Accelerator ocket Scalar Core Core Hwacha Vector Accelerator 1.1mm 16K L1I$ 32K L1D$ 8KB L1VI$ 16K L1I$ 32K L1D$ 8KB L1VI$ Dual-Core ISC-V Vector Processor FPGA FSB/ HTIF Arbiter Coherence Hub 1MB SAM Array Arbiter 4!
5 ISC-V is a new, open, and completely free general-purpose ISA! Developed at UC Berkeley! ISC-V designed to be flexible and extensible! Better integrate accelerators with host cores! ISC-V software ecosystem! binutils, GCC, Newlib, glibc, GDB, LLVM, Linux, QEMU! External users contributing to ecosystem! 5!
6 ocket Scalar Core" PC! IF! ID! EX! MEM! WB! ITLB Int.F DTLB PC Gen. I$ Inst. Int.EX D$ Commit Access Decode Access bypass paths omitted for simplicity ocket Pipeline to Hwacha FP.F FP.EX1 FP.EX2 FP.EX3 64-bit 6-stage single-issue in-order pipeline! Design minimizes impact of long clock-to-output delays of compiler-generated AMs! 64-entry BTB, 256-entry BHT, 2-entry AS! MMU supports page-based virtual memory! IEEE compliant FPU! Supports SP, DP FMA with hw support for subnormals! 6!
7 AM Cortex-A5 vs. ISC-V ocket" Category" AM Cortex-A5" ISC-V ocket" ISA! 32-bit AM v7! 64-bit ISC-V v2! Architecture! Single-Issue In-Order! Single-Issue In-Order 6-stage! Performance! 1.57 DMIPS/MHz! 1.72 DMIPS/MHz! Process! TSMC 40GPLUS! TSMC 40GPLUS! Area w/o Caches! 0.27 mm 2! 0.14 mm 2! Area with 16K Caches! 0.53 mm 2! 0.39 mm 2! Area Efficiency! 2.96 DMIPS/MHz/mm 2! 4.41 DMIPS/MHz/mm 2! Frequency! >1GHz! >1GHz! Dynamic Power! <0.08 mw/mhz! mw/mhz! PPA reporting conditions! 85% utilization, use Dhrystone for benchmark, frequency/ power at TT 0.9V 25C, all regular VT transistors! 10% higher in DMIPS/MHz, 49% more area-efficient! 7!
8 Hwacha Vector Accelerator" L1 VI$ Vector Issue Unit Bank0 Ctrl Bank0 11W SAM Bank1 Ctrl Bank1 11W SAM Bank7 Ctrl Bank7 11W SAM 64-bit Integer Multiplier SP/DP Floating-Point Units Vector Memory Unit Shared L1 D$ from ocket int int int ead Ports Write Ports 8!
9 Bank Execution Diagram" W W W After a 2-cycle initial startup latency, the banked F is effectively able to read out 2 operands/cycle.! 9!
10 Processor Generators" Express hardware as highly parameterized generators! Helps tune the design under different performance, power, and area constraints! Parameters include:! number of cores! cache sizes, associativity, number of TLB entries, cache-coherence protocol! number of floating-point pipeline stages! width of off-chip I/O, and more! 10!
11 Writing Generators with Chisel" TL generator written in Chisel! HDL embedded in Scala! Full power of Scala for writing generators! object-oriented programming, functional programming! C++ code! C++ Compiler! Chisel Program! Scala/JVM! FPGA Verilog! ASIC Verilog! Software Simulator! FPGA Tools! FPGA Emulation! ASIC Tools! GDS Layout! 11!
12 Physical Design Flow" Chisel Source Code! Chisel! TL Code (Verilog)! Synthesis! Place-and-oute! The core is synthesized and place-and-routed independently, and instantiated twice Gate-level Netlist! Formality! Formal Verification! PrimeTime/StarC! Static Timing Analysis! VCS Post-PN! Gate-level Simulation! Signed-Off Design! 12!
13 Chip esults" Process! Package! Chip Parameters" 45nm SOI CMOS, 11 metal layers! C4 area I/O, flip-chip bonded to PCB! Size! Processor! 2.8mm X 1.1mm! Standard Cells! SAM Bits! 1 Core! 1.37mm X 1.06mm! SAM Array! Processor! 1.1mm X 4mm! 425K (85K flip-flops)! 1 Core! 192K (36K flip-flops)! Processor! 1246K! 1 Core! 621K! Frequency! 1GHz (Nominal), 250MHz-1.3GHz! Voltage! Power! 1V (Nominal), 0.65V-1.2V! 300mW-430mW (Nominal), 40mW-960mW! 13!
14 Measurement Setup" 45nm ISC-V Vector Processor FSB 150MHz Virtex 6 FPGA Board 1Gbps Ethernet Laptop 512MB DAM only used in basic testing mode 14!
15 Shmoo Plot of DP GFLOPS/W" unning Double-Precision Matrix Multiplication on Vector Accelerator! Vdd (V) Not Operational Frequency (MHz) More Efficient" Less Efficient" Nominal" 7.3 GFLOPS/W! Max Frequency" 4.2 GFLOPS/W! Most Efficient" 16.7 GFLOPS/W! VDD at 0.8V" 12.5 GFLOPS/W! 15!
16 Energy Efficiency Frequency (GHz)" 64-bit GFLOPS" Power" (W)" Efficiency (GFLOPS/W)" Blue Gene/Q! 1.60! 204.8! 29.7! 6.9! IBM Cell! 3.20! 108.8! 22.5! 4.8! This Work" 0.55" 1.72" 0.138" 12.5" BG/Q and IBM Cell fabricated in same 45nm SOI! Conservatively assume BG/Q and Cell achieves peak GFLOPS, we achieve 78% of peak GFLOPS! Power numbers only for the core with private caches! Blue Gene/Q: Cores dissipate 54% of total power! IBM Cell: Assume that cores dissipate 50% of total power! Why better energy efficiency than others?! Simpler, but yet more energy-efficient microarchitecture! 16!
17 More on Comparison" But BG/Q is clocked 3X faster and Cell is 6X faster?! If the end goal is to provide better energy efficiency then use simpler microarchitectures and rely on parallelism for performance.! But BG/Q and Cell have big on-chip caches? What about I/O power?! We only count the power dissipated in the core and the private L1 caches.! But BG/Q and Cell have 100X more total GFLOPS!! Sorry, we only had budget for a small test chip.! 17!
18 Conclusions" Processor generators written in high-level languages can produce energy-efficient, high-performance hardware! Our dual-core ISC-V vector processor achieves 16.7 DP GFLOPS/W at 0.65 V and a maximum frequency of 1.3 GHz at 1.2 V! Open-source ISC-V ISA can serve as a competitive base ISA for integrating specialized heterogeneous accelerators! ocket chip generator and software tools open-sourced at 18!
19 Acknowledgment" DAPA award H C-0100! DAPA award H ! Center for Future Architecture esearch, a member of STAnet, a Semiconductor esearch Corporation program sponsored by MACO! NVIDIA graduate fellowship! ASPIE Lab industrial sponsors and affiliates Intel, Google, Nokia, NVIDIA, Oracle, and Samsung! All POEM team members at MIT, UC Berkeley, CU Boulder! 19!
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