ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "ECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013"

Transcription

1 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck! Your Name (please print) total

2 Problem 1 (2 parts, 28 points) Storage Allocation and Pointers In the following problems, assume all data types are word aligned. Pay attention to the word size, which is different in each part. Part A (8 points) Assuming a 64-bit operating system, show how the following global variables map into static memory. Assume they are allocated starting at address For each variable, draw a box showing its size and position in memory. Label the box with the variable name. Label each element of an array (e.g., Name[0]) float f = 2.0; double B[] = {3.14, 6.28; float *fp = &f; double *dp = B; Part B (20 points) For this part, assume a 32-bit operating system. Suppose the following variables are allocated beginning at address Complete the table below, listing the value of the expression following this definition. int x = 8; int y = 9; double D = 6.25; double E = 9.33; int A[3] = {17, 6, 5; int *P = A+1; double *Q = &D; float w = 7.5; *(P-1) *(A+2) P+1 &(A[1]) A Q Q++ &w 2

3 Problem 2 (1 part, 20 points) Parameter Passing Consider the following C code fragment. Foo is called by main. int main() { int x = 100, V[] = {10, 3, 5, 6; float F[] = {3.14, 5.25; int y=25, d; int *z = &y; <more code here> d = Foo(x, F, F[0], V, z); <more code here> int Foo (int a, float *b, float c, int *S, int *g) { <Foo's code goes here> For each statement from Foo below, list the resulting value. If the result is an address, just list address. Also determine if it affects Foo s activation frame variables, main s activation frame variables, or both. Consider each statement independently and non-cumulatively (i.e., as if it is the only statement in Foo). statement in Foo result (assigned value) modify Foo s AF variables modify main s AF variables c = *b + 3.0; Yes No Yes No a *= 3; Yes No Yes No *g = *g + S[2]; Yes No Yes No S[1] += 2; Yes No Yes No b++; Yes No Yes No 3

4 Problem 3 (2 parts, 16 points) Array Access Part A (4 points) Suppose a 64x64 image array is stored in memory as in Project 1: each pixel is represented by 1 byte of storage. Each row of pixels is stored contiguously, one after another. Suppose register $4 holds the linear offset into the array (i.e., it would be added to the base address of the image array to access a particular pixel). Write a MIPS code fragment that computes the row and column number and places the row number into $5 and the column number into $6. For 3 bonus points, use only 2 instructions. Label Instruction Comment Part B (12 points) Write the MIPS code implementation of the dynamically allocated array access below in the smallest number of instructions. A pointer to the array (declared below) is stored in $3. Variables X, Y, Z, and R reside in $4, $5, $6, and $2 respectively. Modify only registers $1 and $2. int Array[4][3][32]; /* array declaration */ R = Array[Z][Y][X]; /* implement this */ Label Instruction Comment 4

5 Problem 4 (2 parts, 36 points) Consider the following C code fragment: typedef struct { int x; int y; pair; Activation Frames int Bar() { int M = 3; int N = 4; pair P; int Q[] = {10, 20, 30; int Foo(int, pair *, int *); P.x = 5; P.y = 6; N = Foo(M, &P, Q); return(n); int Foo(int A, pair *B, int *C) { int D = 25; int E; C[2] = C[1] + A; E = B->y + D; return(e); Part A (20 points) Describe the current state of the stack just before Foo returns to Bar. Fill in the unshaded boxes to show Bar s and Foo s activation frames. Include a symbolic description and the actual value (in decimal). For return addresses, show only the symbolic description; do not include a value. Label the frame pointer and stack pointer. address description Value 9900 RA of Bar s caller 9896 FP of Bar s caller SP, Bar s FP

6 Part B (16 points) Write MIPS code fragments to implement the subroutine Foo by following the steps below. Do not use absolute addresses in your code; instead, access variables relative to the frame pointer. Assume no parameters are present in registers (i.e., access all parameters from Foo s activation frame). First, write code to properly set Foo s frame pointer and to allocate space for Foo s local variables and initialize them if necessary. C[2] = C[1] + A; E = B->y + D; return(e); (compute return value, deallocate locals, and return) 6

7 MIPS Instruction Set (core) instruction example meaning arithmetic add add $1,$2,$3 $1 = $2 + $3 subtract sub $1,$2,$3 $1 = $2 - $3 add immediate addi $1,$2,100 $1 = $ add unsigned addu $1,$2,$3 $1 = $2 + $3 subtract unsigned subu $1,$2,$3 $1 = $2 - $3 add immediate unsigned addiu $1,$2,100 $1 = $ set if less than slt $1, $2, $3 if ($2 < $3), $1 = 1 else $1 = 0 set if less than immediate slti $1, $2, 100 if ($2 < 100), $1 = 1 else $1 = 0 set if less than unsigned sltu $1, $2, $3 if ($2 < $3), $1 = 1 else $1 = 0 set if < immediate unsigned sltui $1, $2, 100 if ($2 < 100), $1 = 1 else $1 = 0 multiply mult $2,$3 Hi, Lo = $2 * $3, 64-bit signed product multiply unsigned multu $2,$3 Hi, Lo = $2 * $3, 64-bit unsigned product divide div $2,$3 Lo = $2 / $3, Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 / $3, Hi = $2 mod $3, unsigned transfer move from Hi mfhi $1 $1 = Hi move from Lo mflo $1 $1 = Lo load upper immediate lui $1,100 $1 = 100 x logic and and $1,$2,$3 $1 = $2 & $3 or or $1,$2,$3 $1 = $2 $3 and immediate andi $1,$2,100 $1 = $2 & 100 or immediate ori $1,$2,100 $1 = $2 100 nor nor $1,$2,$3 $1 = not($2 $3) xor xor $1, $2, $3 $1 = $2 $3 xor immediate xori $1, $2, 255 $1 = $2 255 shift shift left logical sll $1,$2,5 $1 = $2 << 5 (logical) shift left logical variable sllv $1,$2,$3 $1 = $2 << $3 (logical), variable shift amt shift right logical srl $1,$2,5 $1 = $2 >> 5 (logical) shift right logical variable srlv $1,$2,$3 $1 = $2 >> $3 (logical), variable shift amt shift right arithmetic sra $1,$2,5 $1 = $2 >> 5 (arithmetic) shift right arithmetic variable srav $1,$2,$3 $1 = $2 >> $3 (arithmetic), variable shift amt memory load word lw $1, 1000($2) $1 = memory [$2+1000] store word sw $1, 1000($2) memory [$2+1000] = $1 load byte lb $1, 1002($2) $1 = memory[$2+1002] in least sig. byte load byte unsigned lbu $1, 1002($2) $1 = memory[$2+1002] in least sig. byte store byte sb $1, 1002($2) memory[$2+1002] = $1 (byte modified only) branch branch if equal beq $1,$2,100 if ($1 = $2), PC = PC (100*4) branch if not equal bne $1,$2,100 if ($1 $2), PC = PC (100*4) jump jump j PC = 10000*4 jump register jr $31 PC = $31 jump and link jal $31 = PC + 4; PC = 10000*4 7

ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016

ECE 2035 A Programming Hw/Sw Systems Fall problems, 10 pages Final Exam 14 December 2016 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam 29 April 2015 Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

More information

MIPS Instruction Reference

MIPS Instruction Reference Page 1 of 9 MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly

More information

MIPS Reference Guide

MIPS Reference Guide MIPS Reference Guide Free at PushingButtons.net 2 Table of Contents I. Data Registers 3 II. Instruction Register Formats 4 III. MIPS Instruction Set 5 IV. MIPS Instruction Set (Extended) 6 V. SPIM Programming

More information

Assembly Programming

Assembly Programming Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming

More information

Week 10: Assembly Programming

Week 10: Assembly Programming Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +

More information

SPIM Instruction Set

SPIM Instruction Set SPIM Instruction Set This document gives an overview of the more common instructions used in the SPIM simulator. Overview The SPIM simulator implements the full MIPS instruction set, as well as a large

More information

CPS311 - COMPUTER ORGANIZATION. A bit of history

CPS311 - COMPUTER ORGANIZATION. A bit of history CPS311 - COMPUTER ORGANIZATION A Brief Introduction to the MIPS Architecture A bit of history The MIPS architecture grows out of an early 1980's research project at Stanford University. In 1984, MIPS computer

More information

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

ECE232: Hardware Organization and Design. Computer Organization - Previously covered ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization

More information

Mips Code Examples Peter Rounce

Mips Code Examples Peter Rounce Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then

More information

MIPS Instruction Format

MIPS Instruction Format MIPS Instruction Format MIPS uses a 32-bit fixed-length instruction format. only three different instruction word formats: There are Register format Op-code Rs Rt Rd Function code 000000 sssss ttttt ddddd

More information

MIPS%Assembly% E155%

MIPS%Assembly% E155% MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary

More information

ECE Exam I February 19 th, :00 pm 4:25pm

ECE Exam I February 19 th, :00 pm 4:25pm ECE 3056 Exam I February 19 th, 2015 3:00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and

More information

CS 61c: Great Ideas in Computer Architecture

CS 61c: Great Ideas in Computer Architecture MIPS Functions July 1, 2014 Review I RISC Design Principles Smaller is faster: 32 registers, fewer instructions Keep it simple: rigid syntax, fixed instruction length MIPS Registers: $s0-$s7,$t0-$t9, $0

More information

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats

Today s Lecture. MIPS Assembly Language. Review: What Must be Specified? Review: A Program. Review: MIPS Instruction Formats Today s Lecture Homework #2 Midterm I Feb 22 (in class closed book) MIPS Assembly Language Computer Science 14 Lecture 6 Outline Assembly Programming Reading Chapter 2, Appendix B 2 Review: A Program Review:

More information

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers

Instruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers

More information

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions

Outline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713

More information

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5

ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local

More information

Concocting an Instruction Set

Concocting an Instruction Set Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Read: Chapter 2.1-2.7 L03 Instruction Set 1 A General-Purpose Computer The von

More information

A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction

A General-Purpose Computer The von Neumann Model. Concocting an Instruction Set. Meaning of an Instruction. Anatomy of an Instruction page 1 Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... A General-Purpose Computer The von Neumann Model Many architectural approaches

More information

Computer Architecture Experiment

Computer Architecture Experiment Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU

More information

Review of Activation Frames. FP of caller Y X Return value A B C

Review of Activation Frames. FP of caller Y X Return value A B C Review of Activation Frames In general, activation frames are organized like this: HI LO Bookkeeping/preserved registers I/O parameters Locals and temps RA of caller FP of caller Y X Return value A B C

More information

We will study the MIPS assembly language as an exemplar of the concept.

We will study the MIPS assembly language as an exemplar of the concept. MIPS Assembly Language 1 We will study the MIPS assembly language as an exemplar of the concept. MIPS assembly instructions each consist of a single token specifying the command to be carried out, and

More information

EE 109 Unit 8 MIPS Instruction Set

EE 109 Unit 8 MIPS Instruction Set 1 EE 109 Unit 8 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system

More information

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA

Mark Redekopp, All rights reserved. EE 352 Unit 3 MIPS ISA EE 352 Unit 3 MIPS ISA Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the vocabulary the HW can understand and the SW is composed

More information

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda

MIPS ISA and MIPS Assembly. CS301 Prof. Szajda MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done

More information

CSc 256 Final Spring 2011

CSc 256 Final Spring 2011 CSc 256 Final Spring 2011 NAME: Problem1: Convertthedecimalfloatingpointnumber 4.3toa32 bitfloat(inbinary)inieee 754standardrepresentation.Showworkforpartialcredit.10points Hint:IEEE754formatfor32 bitfloatsconsistsofs

More information

2. dead code elimination (declaration and initialization of z) 3. common subexpression elimination (temp1 = j + g + h)

2. dead code elimination (declaration and initialization of z) 3. common subexpression elimination (temp1 = j + g + h) Problem 1 (20 points) Compilation Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version (in C) to the right. Assume f is a pure function

More information

EE108B Lecture 3. MIPS Assembly Language II

EE108B Lecture 3. MIPS Assembly Language II EE108B Lecture 3 MIPS Assembly Language II Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Urgent: sign up at EEclass and say if you are taking 3 or 4 units Homework

More information

Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary

Announcements. EE108B Lecture MIPS Assembly Language III. MIPS Machine Instruction Review: Instruction Format Summary Announcements EE108B Lecture MIPS Assembly Language III Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b PA1 available, due on Thursday 2/8 Work on you own (no groups) Homework

More information

A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor. Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3 A Processor Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Let s build a MIPS CPU but using Harvard architecture Basic Computer System Registers ALU

More information

The MIPS R2000 Instruction Set

The MIPS R2000 Instruction Set The MIPS R2000 Instruction Set Arithmetic and Logical Instructions In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions

More information

Compiling Techniques

Compiling Techniques Lecture 10: An Introduction to MIPS assembly 18 October 2016 Table of contents 1 Overview 2 3 Assembly program template.data Data segment: constant and variable definitions go here (including statically

More information

Digital System Design II

Digital System Design II Digital System Design II 数字系统设计 II Peng Liu ( 刘鹏 ) Dept. of Info. Sci. & Elec. Engg. Zhejiang University liupeng@zju.edu.cn Lecture 2 MIPS Instruction Set Architecture 2 Textbook reading MIPS ISA 2.1-2.4

More information

Midterm. CS64 Spring Midterm Exam

Midterm. CS64 Spring Midterm Exam Midterm LAST NAME FIRST NAME PERM Number Instructions Please turn off all pagers, cell phones and beepers. Remove all hats & headphones. Place your backpacks, laptops and jackets at the front. Sit in every

More information

Computer Architecture. Chapter 3: Arithmetic for Computers

Computer Architecture. Chapter 3: Arithmetic for Computers 182.092 Computer Architecture Chapter 3: Arithmetic for Computers Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, Morgan Kaufmann Publishers and Mary Jane Irwin

More information

CHW 362 : Computer Architecture & Organization

CHW 362 : Computer Architecture & Organization CHW 362 : Computer Architecture & Organization Instructors: Dr Ahmed Shalaby Dr Mona Ali http://bu.edu.eg/staff/ahmedshalaby14# http://www.bu.edu.eg/staff/mona.abdelbaset Assignment What is the size of

More information

Inequalities in MIPS (2/4) Inequalities in MIPS (1/4) Inequalities in MIPS (4/4) Inequalities in MIPS (3/4) UCB CS61C : Machine Structures

Inequalities in MIPS (2/4) Inequalities in MIPS (1/4) Inequalities in MIPS (4/4) Inequalities in MIPS (3/4) UCB CS61C : Machine Structures CS61C L8 Introduction to MIPS : Decisions II & Procedures I (1) Instructor Paul Pearce inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures http://www.xkcd.org/627/ Lecture 8 Decisions & and Introduction

More information

Chapter 6. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 6 <1>

Chapter 6. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 6 <1> Chapter 6 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 6 Chapter 6 :: Topics Introduction Assembly Language Machine Language Programming Addressing

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures $2M 3D camera Lecture 8 MIPS Instruction Representation I Instructor: Miki Lustig 2014-09-17 August 25: The final ISA showdown: Is ARM, x86, or

More information

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation

ICS 233 COMPUTER ARCHITECTURE. MIPS Processor Design Multicycle Implementation ICS 233 COMPUTER ARCHITECTURE MIPS Processor Design Multicycle Implementation Lecture 23 1 Add immediate unsigned Subtract unsigned And And immediate Or Or immediate Nor Shift left logical Shift right

More information

Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21

Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...

More information

CS 61c: Great Ideas in Computer Architecture

CS 61c: Great Ideas in Computer Architecture Introduction to Assembly Language June 30, 2014 Review C Memory Layout Local variables disappear because the stack changes Global variables don t disappear because they are in static data Dynamic memory

More information

CS 4200/5200 Computer Architecture I

CS 4200/5200 Computer Architecture I CS 4200/5200 Computer Architecture I MIPS Instruction Set Architecture Dr. Xiaobo Zhou Department of Computer Science CS420/520 Lec3.1 UC. Colorado Springs Adapted from UCB97 & UCB03 Review: Organizational

More information

MIPS Assembly Programming

MIPS Assembly Programming COMP 212 Computer Organization & Architecture COMP 212 Fall 2008 Lecture 8 Cache & Disk System Review MIPS Assembly Programming Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2

More information

Chapter 6 :: Topics. Chapter 6 :: Architecture

Chapter 6 :: Topics. Chapter 6 :: Architecture Chapter 6 :: Architecture Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Chapter 6 :: Topics Introduction Assembly Language Machine Language Programming Addressing Modes

More information

Problem maximum score 1 35pts 2 22pts 3 23pts 4 15pts Total 95pts

Problem maximum score 1 35pts 2 22pts 3 23pts 4 15pts Total 95pts University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS61c Summer 2001 Woojin Yu Midterm Exam This is a closed-book exam. No calculators

More information

Concocting an Instruction Set

Concocting an Instruction Set Concocting an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... Lab is posted. Do your prelab! Stay tuned for the first problem set. L04 Instruction

More information

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA. Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic

More information

CS61C Machine Structures. Lecture 10 - MIPS Branch Instructions II. 2/8/2006 John Wawrzynek. (www.cs.berkeley.edu/~johnw)

CS61C Machine Structures. Lecture 10 - MIPS Branch Instructions II. 2/8/2006 John Wawrzynek. (www.cs.berkeley.edu/~johnw) CS61C Machine Structures Lecture 10 - MIPS Branch Instructions II 2/8/2006 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS 61C L10 MIPS Branch II (1) Compiling C if into

More information

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer

More information

CS3350B Computer Architecture

CS3350B Computer Architecture CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,

More information

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam Solutions 29 April 2015

ECE 2035 A Programming Hw/Sw Systems Spring problems, 8 pages Final Exam Solutions 29 April 2015 Problem 1 (20 points) Optimization Perform at least five standard compiler optimizations on the following C code fragment by writing the optimized version (in C) to the right. Assume f and g are pure functions

More information

Architecture II. Computer Systems Laboratory Sungkyunkwan University

Architecture II. Computer Systems Laboratory Sungkyunkwan University MIPS Instruction ti Set Architecture II Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Making Decisions (1) Conditional operations Branch to a

More information

COMP 303 MIPS Processor Design Project 3: Simple Execution Loop

COMP 303 MIPS Processor Design Project 3: Simple Execution Loop COMP 303 MIPS Processor Design Project 3: Simple Execution Loop Due date: November 20, 23:59 Overview: In the first three projects for COMP 303, you will design and implement a subset of the MIPS32 architecture

More information

Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:

Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#: Computer Science and Engineering 331 Midterm Examination #1 Fall 2000 Name: Solutions S.S.#: 1 41 2 13 3 18 4 28 Total 100 Instructions: This exam contains 4 questions. It is closed book and notes. Calculators

More information

Numbers: positional notation. CS61C Machine Structures. Faux Midterm Review Jaein Jeong Cheng Tien Ee. www-inst.eecs.berkeley.

Numbers: positional notation. CS61C Machine Structures. Faux Midterm Review Jaein Jeong Cheng Tien Ee. www-inst.eecs.berkeley. CS 61C Faux Midterm Review (1) CS61C Machine Structures Faux Midterm Review 2002-09-29 Jaein Jeong Cheng Tien Ee www-inst.eecs.berkeley.edu/~cs61c/ Numbers: positional notation Number Base B B symbols

More information

MIPS Instructions: 64-bit Core Subset

MIPS Instructions: 64-bit Core Subset MIPS Instructions: 64-bit Core Subset Spring 2008 General notes: a. R s, R t, and R d specify 64-bit general purpose registers b. F s, F t, and F d specify 64-bit floating point registers c. C d specifies

More information

Review (1/2) IEEE 754 Floating Point Standard: Kahan pack as much in as could get away with. CS61C - Machine Structures

Review (1/2) IEEE 754 Floating Point Standard: Kahan pack as much in as could get away with. CS61C - Machine Structures Review (1/2) CS61C - Machine Structures Lecture 11 - Starting a Program October 4, 2000 David Patterson http://www-inst.eecs.berkeley.edu/~cs61c/ IEEE 754 Floating Point Standard: Kahan pack as much in

More information

A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3

A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University. See: P&H Chapter , 4.1-3 A Processor! Hakim Weatherspoon CS 3410, Spring 2010 Computer Science Cornell University See: P&H Chapter 2.16-20, 4.1-3 Announcements! HW2 available later today HW2 due in one week and a half Work alone

More information

CS152 Computer Architecture and Engineering. Lecture 1 Introduction & MIPS Review Dave Patterson. www-inst.eecs.berkeley.

CS152 Computer Architecture and Engineering. Lecture 1 Introduction & MIPS Review Dave Patterson. www-inst.eecs.berkeley. CS152 Computer Architecture and Engineering Lecture 1 Introduction & MIPS Review 2003-08-26 Dave Patterson (www.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs152/ CS 152 L01 Introduction &

More information

CPU Design for Computer Integrated Experiment

CPU Design for Computer Integrated Experiment CPU Design for Computer Integrated Experiment Shan Lu, Guangyao Li, Yijianan Wang CEIE, Tongji University, Shanghai, China Abstract - Considering the necessity and difficulty of designing a CPU for students,

More information

MIPS (SPIM) Assembler Syntax

MIPS (SPIM) Assembler Syntax MIPS (SPIM) Assembler Syntax Comments begin with # Everything from # to the end of the line is ignored Identifiers are a sequence of alphanumeric characters, underbars (_), and dots () that do not begin

More information

CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14

CO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14 CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017 Frame Pointer (1) The stack is also used to store variables that are local to function, but

More information

Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B

Anne Bracy CS 3410 Computer Science Cornell University. See P&H Chapter: , , Appendix B Anne Bracy CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. See P&H Chapter: 2.16-2.20, 4.1-4.4,

More information

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University. Instructions: ti Language of the Computer Rui Wang, Assistant professor Dept. of Information and Communication Tongji University it Email: ruiwang@tongji.edu.cn Computer Hierarchy Levels Language understood

More information

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero Do-While Example In C++ do { z--; while (a == b); z = b; In assembly language loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero 25 Comparisons Set on less than (slt) compares its source registers

More information

EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design

EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown

More information

ECE 2035 Programming HW/SW Systems Spring problems, 7 pages Exam One Solutions 4 February 2013

ECE 2035 Programming HW/SW Systems Spring problems, 7 pages Exam One Solutions 4 February 2013 Problem 1 (3 parts, 30 points) Code Fragments Part A (5 points) Write a MIPS code fragment that branches to label Target when register $1 is less than or equal to register $2. You may use only two instructions.

More information

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:

More information

HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b;

HW2 solutions You did this for Lab sbn temp, temp,.+1 # temp = 0; sbn temp, b,.+1 # temp = -b; sbn a, temp,.+1 # a = a (-b) = a + b; HW2 solutions 3.10 Pseuodinstructions What is accomplished Minimum sequence of Mips Move $t5, $t3 $t5=$t3 Add $t5, $t3, $0 Clear $t5 $t5=0 Xor $t5, $t5, $t5 Li $t5, small $t5=small Addi $t5, $0, small

More information

Tailoring the 32-Bit ALU to MIPS

Tailoring the 32-Bit ALU to MIPS Tailoring the 32-Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance

More information

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation Levels of Representation/Interpretation

More information

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction

More information

Overview of Today s Lecture

Overview of Today s Lecture Overview of Today s Lecture CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance January 18, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) Review from Last

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems The MIPS Instruction Set Martha A. Kim Columbia University Fall 2015 1 / 67 Instruction Set Architectures MIPS The GCD Algorithm MIPS Registers Types of Instructions Computational

More information

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access

More information

REGISTERS INSTRUCTION SET DIRECTIVES SYSCALLS

REGISTERS INSTRUCTION SET DIRECTIVES SYSCALLS MARS REGISTERS INSTRUCTION SET DIRECTIVES SYSCALLS ΗΥ 134: ΕΙΣΑΓΩΓΗ ΣΤΗΝ ΟΡΓΑΝΩΣΗ ΚΑΙ ΣΧΕΔΙΑΣΗ Η/Υ Ι Registers MIPS has 32 integer registers. The hardware architecture specifies that: General purpose register

More information

All instructions have 3 operands Operand order is fixed (destination first)

All instructions have 3 operands Operand order is fixed (destination first) Instruction Set Architecture for MIPS Processors Overview Dr. Arjan Durresi Louisiana State University Baton Rouge, LA 70803 durresi@csc.lsu.edu These slides are available at: http://www.csc.lsu.edu/~durresi/_07/

More information

UCB CS61C : Machine Structures

UCB CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 10 Introduction to MIPS Procedures I Sr Lecturer SOE Dan Garcia 2014-02-14 If cars broadcast their speeds to other vehicles (and the

More information

ECE 154A Introduction to. Fall 2012

ECE 154A Introduction to. Fall 2012 ECE 154A Introduction to Computer Architecture Fall 2012 Dmitri Strukov Lecture 4: Arithmetic and Data Transfer Instructions Agenda Review of last lecture Logic and shift instructions Load/store instructionsi

More information

CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014

CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 B CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 DUE : March 3, 2014 READ : - Related sections of Chapter 2 - Related sections of Chapter 3 - Related sections of Appendix A - Related sections

More information

MIPS PROJECT INSTRUCTION SET and FORMAT

MIPS PROJECT INSTRUCTION SET and FORMAT ECE 312: Semester Project MIPS PROJECT INSTRUCTION SET FORMAT This is a description of the required MIPS instruction set, their meanings, syntax, semantics, bit encodings. The syntax given for each instruction

More information

MIPS Hello World. MIPS Assembly 1. # PROGRAM: Hello, World! # Data declaration section. out_string:.asciiz "\nhello, World!\n"

MIPS Hello World. MIPS Assembly 1. # PROGRAM: Hello, World! # Data declaration section. out_string:.asciiz \nhello, World!\n MIPS Hello World MIPS Assembly 1 # PROGRAM: Hello, World!.data # Data declaration section out_string:.asciiz "\nhello, World!\n".text # Assembly language instructions main: # Start of code section li $v0,

More information

CSE Lecture In Class Example Handout

CSE Lecture In Class Example Handout CSE 30321 Lecture 07-09 In Class Example Handout Part A: A Simple, MIPS-based Procedure: Swap Procedure Example: Let s write the MIPS code for the following statement (and function call): if (A[i] > A

More information

Lecture 6 Decision + Shift + I/O

Lecture 6 Decision + Shift + I/O Lecture 6 Decision + Shift + I/O Instructions so far MIPS C Program add, sub, addi, multi, div lw $t0,12($s0) sw $t0, 12($s0) beq $s0, $s1, L1 bne $s0, $s1, L1 j L1 (unconditional branch) slt reg1,reg2,reg3

More information

Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology

Computer Organization MIPS Architecture. Department of Computer Science Missouri University of Science & Technology Computer Organization MIPS Architecture Department of Computer Science Missouri University of Science & Technology hurson@mst.edu Computer Organization Note, this unit will be covered in three lectures.

More information

Operands and Addressing Modes

Operands and Addressing Modes Operands and Addressing Modes Where is the data? Addresses as data Names and Values Indirection L5 Addressing Modes 1 Assembly Exercise Let s write some assembly language programs Program #1: Write a function

More information

COMP MIPS instructions 2 Feb. 8, f = g + h i;

COMP MIPS instructions 2 Feb. 8, f = g + h i; Register names (save, temporary, zero) From what I have said up to now, you will have the impression that you are free to use any of the 32 registers ($0,..., $31) in any instruction. This is not so, however.

More information

CSE Lecture In Class Example Handout

CSE Lecture In Class Example Handout CSE 30321 Lecture 07-08 In Class Example Handout Part A: J-Type Example: If you look in your book at the syntax for j (an unconditional jump instruction), you see something like: e.g. j addr would seemingly

More information

Solutions for Chapter 2 Exercises

Solutions for Chapter 2 Exercises Solutions for Chapter 2 Exercises 1 Solutions for Chapter 2 Exercises 2.2 By lookup using the table in Figure 2.5 on page 62, 7fff fffa hex = 0111 1111 1111 1111 1111 1111 1111 1010 two = 2,147,483,642

More information

Lecture 7: MIPS Functions Part 2. Nested Function Calls. Lecture 7: Character and String Operations. SPIM Syscalls. Recursive Functions

Lecture 7: MIPS Functions Part 2. Nested Function Calls. Lecture 7: Character and String Operations. SPIM Syscalls. Recursive Functions Part Part Part What if we need to call a function inside of a function? Will this work? int twofun(int a, int b) { int res; res = addfun(a, b) a / ; return res; } twofun: addi $sp, $sp, -4 sw $s0, 0($sp)

More information

COMP2421 COMPUTER ORGANZATION. Lab 3

COMP2421 COMPUTER ORGANZATION. Lab 3 Lab 3 Objectives: This lab shows you some basic techniques and syntax to write a MIPS program. Syntax includes system calls, load address instruction, load integer instruction, and arithmetic instructions

More information

Lab 4 Report. Single Cycle Design BAOTUNG C. TRAN EEL4713C

Lab 4 Report. Single Cycle Design BAOTUNG C. TRAN EEL4713C Lab 4 Report Single Cycle Design BAOTUNG C. TRAN EEL4713C Added Hardware : Andi and Ori : For this instruction, I had to add a zero extender into my design. Which therefore required me to add a mux that

More information

CS3350B Computer Architecture MIPS Procedures and Compilation

CS3350B Computer Architecture MIPS Procedures and Compilation CS3350B Computer Architecture MIPS Procedures and Compilation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada

More information

Lab 3: Pipelined MIPS Assigned: Wed., 2/13; Due: Fri., 3/1 (Midnight)

Lab 3: Pipelined MIPS Assigned: Wed., 2/13; Due: Fri., 3/1 (Midnight) CMU 18-447 Introduction to Computer Architecture Spring 2013 1/7 Lab 3: Pipelined MIPS Assigned: Wed., 2/13; Due: Fri., 3/1 (Midnight) Instructor: Onur Mutlu TAs: Justin Meza, Yoongu Kim, Jason Lin It

More information

ISA: The Hardware Software Interface

ISA: The Hardware Software Interface ISA: The Hardware Software Interface Instruction Set Architecture (ISA) is where software meets hardware In embedded systems, this boundary is often flexible Understanding of ISA design is therefore important

More information

Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College

Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor

More information

Arithmetic. Chapter 3 Computer Organization and Design

Arithmetic. Chapter 3 Computer Organization and Design Arithmetic Chapter 3 Computer Organization and Design Addition Addition is similar to decimals 0000 0111 + 0000 0101 = 0000 1100 Subtraction (negate) 0000 0111 + 1111 1011 = 0000 0010 Over(under)flow For

More information

EE380 Spring 2014 Exam 1 Answer Key

EE380 Spring 2014 Exam 1 Answer Key Your name is: Your email address is: The two questions you skipped are: There are 15 questions. Each of the first 14 questions is wor th 8points; you must answer any 12 and indicate above which 2 you skipped

More information