CPU Structure and Function
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1 CPU Structure and Function Chapter 12 Lesson 17 Slide 1/36
2 Processor Organization CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data Lesson 17 Slide 2/36
3 CPU With Systems Bus Lesson 17 Slide 3/36
4 CPU Internal Structure Lesson 17 Slide 4/36
5 Registers CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy Registers: User-visible registers Control and status registers Lesson 17 Slide 5/36
6 User-Visible Registers General Purpose Data Address Condition Codes Lesson 17 Slide 6/36
7 General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data Accumulator Addressing Segment Lesson 17 Slide 7/36
8 General Purpose Registers (2) Make them general purpose Increase flexibility and programmer options Increase instruction size & complexity Make them specialized Smaller (faster) instructions Less flexibility Lesson 17 Slide 8/36
9 How Many GP Registers? Between 8-32 Fewer = more memory references More does not reduce memory references and takes up processor real estate But in RISC processors, hundreds of registers Lesson 17 Slide 9/36
10 Large enough to hold full address Large enough to hold full word Often possible to combine two data registers C programming double int a; long int a; How big? Lesson 17 Slide 10/36
11 Condition Code Registers Flags Sets of individual bits e.g. result of last operation was zero Can be read (implicitly) by programs e.g. Jump if zero Can not (usually) be set by programs Lesson 17 Slide 11/36
12 Control & Status Registers For instruction execution: Program Counter (PC) Instruction Register (IR) Memory Address Register (MAR) Memory Buffer Register (MBR) Lesson 17 Slide 12/36
13 Program Status Word (PSW) A set of bits Includes Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor Lesson 17 Slide 13/36
14 Supervisor Mode Kernel mode Allows privileged instructions to execute Used by operating system Not available to user programs Lesson 17 Slide 14/36
15 Other Registers May have registers pointing to: Process control blocks Interrupt Vectors CPU design and operating system design are closely linked Lesson 17 Slide 15/36
16 Example Register Organizations Lesson 17 Slide 16/36
17 Instruction Cycle Subcycles: Fetch: Read the next instruction from memory into the CPU Execute: Interpret the opcode and perform the indicated operation Interrupt: If interrupts are enabled and an interrupt has occurred, save the current process state and service the interrupt Lesson 17 Slide 17/36
18 Indirect Cycle May require memory access to fetch operands Indirect addressing requires more memory accesses Can be thought of as additional instruction subcycle Lesson 17 Slide 18/36
19 Instruction Cycle with Indirect Lesson 17 Slide 19/36
20 Instruction Cycle State Diagram Lesson 17 Slide 20/36
21 Depends on CPU design In general: Data Flow (Instruction Fetch) Fetch PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1 Lesson 17 Slide 21/36
22 Data Flow (Data Fetch) IR is examined If indirect addressing, indirect cycle is performed Right most N bits of MBR transferred to MAR Control unit requests memory read Result (address of operand) moved to MBR Lesson 17 Slide 22/36
23 Data Flow (Fetch Diagram) Lesson 17 Slide 23/36
24 Lesson 17 Slide 24/36 Data Flow (Indirect Diagram)
25 Data Flow (Execute) May take many forms Depends on instruction being executed May include Memory read/write Input/Output Register transfers ALU operations Lesson 17 Slide 25/36
26 Data Flow (Interrupt) Simple Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched Lesson 17 Slide 26/36
27 Data Flow (Interrupt Diagram) Lesson 17 Slide 27/36
28 Fetch accessing main memory Prefetch Execution usually does not access main memory Can fetch next instruction during execution of current instruction Called instruction prefetch Lesson 17 Slide 28/36
29 But not doubled: Improved Performance Fetch usually shorter than execution Any jump or branch means that prefetched instructions are not the required instructions Add more stages to improve performance Lesson 17 Slide 29/36
30 Pipelining Fetch instruction (FI) Decode instruction (DI) Calculate operands (CO) Fetch operands (FO) Execute instructions (EI) Write operand (WO) Overlap these operations Lesson 17 Slide 30/36
31 Two Stage Instruction Pipeline Lesson 17 Slide 31/36
32 Lesson 17 Slide 32/36 Timing of Pipeline
33 Lesson 17 Slide 33/36 Branch in a Pipeline
34 Six Stage Instruction Pipeline Lesson 17 Slide 22/36
35 Alternative Pipeline Depiction Lesson 17 Slide 22/36
36 Speedup Factors with Instruction Pipelining Lesson 17 Slide 22/36
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