Timing in synchronous systems

Transcription

1 BO 1 esign of sequential logic Outline Timing in synchronous networks Synchronous processes in VHL VHL-code that introduces latches andf flip-flops Initialization of registers Mealy- and Moore machines in VHL Building blocks: counters, registers, RAM/ROM FSM FSM and ata path Copyright Bengt Oelmann Timing in synchronous systems General model for a synchronous system Q1 2 Q2 Combinational logic t C-Q and t SETUP are delays in the flip-flop t C-Q t SETUP C t LOGIK C On clock cycle is the sum of the delays: T = tc Q + tlogik + tsetup + tmarginal Q1 2 t C-Q t LOGIK t SETUP With no timing margin we have obtained the highest possible clock frequency: f max 1 = T min = t C Q + t 1 LOGIK + t SETUP t MARGIN Copyright Bengt Oelmann

2 BO 2 Synchronous processes in VHL Synchronous processes Also called clocked processes All activated simultaneously at the active clock edge Signal assignments in a synchronous process results in flip-flops inputs outputs clock Copyright Bengt Oelmann Example: positive edge-triggered -FF in VHL dff library ieee; use ieee.std_logic_1164.all d q entity dff IS port (d, clk : in std_logic; q : out std_logic); end dff; architecture behavior of dff is process(clk) if (clk event and clk = 1 ) then q <= d; else q <= q; end behavior; clk clk event clk Latches the new value in the FF clk event and clk= 1 Keeps the old value Copyright Bengt Oelmann

3 BO 3 More examples of FF s architecture dataflow of pos_dff is q <= d when (clk event and clk= 1 ) else q; end dataflow; Q architecture dataflow of neg_dff is q <= d when (clk event and clk= 0 ) else q; End dataflow; Q Copyright Bengt Oelmann Example: -latch architecture dataflow of dlatch is q <= d when (clk = 1 ) else q; end dataflow; Q Copyright Bengt Oelmann

4 BO 4 Example: Code that introduces FF s in the design Write a function that stores an 8-bit number in a register if it is greater than 10. If it is less than 10 the register shall contain 10. entity load_ge_10 is port ( clk : in std_logic; d : in std_logic_vector (7 downto 0); q : out std_logic_vector (7 downto 0)); end load_ge_10; architecture rtl of load_ge_10 is process (clk) if (clk'event and clk = '1') then if d > 10 then q <= d; else q <= conv_std_logic_vector(10,8); end rtl; d :1 MUX Signal assignment leads to introduction of FF s 0 1 d>10 clk q Copyright Bengt Oelmann Initialization of FF s At system start the FF s needs to be initialized Two types of initializations Synchronous reset/preset Asynchronous reset/preset Example: synchronous reset if (clk event and clk = 1 ) then if reset = 1 then q <= 0 ; else q <= d; reset Q Copyright Bengt Oelmann

5 BO 5 Cont. Initialization of FF s Exempel: Asynkron reset process (clk, reset) if reset = 1 then q <= 0 ; elsif (clk event and clk = 1 ) then q <= d; reset Q Exempel: Asynkron preset process (clk, preset) if preset = 1 then q <= 1 ; elsif (clk event and clk = 1 ) then q <= d; preset Q Copyright Bengt Oelmann esign of state machines Manual design work flow: evelop a state graph that captures the problem evelop a state graph that captures the problem evelop a state graph evelop a state graph Coding of states Coding of states Select register elements (-,T-,JK-?) Select register elements (-,T-,JK-?) evelop a transition table evelop a transition table evelop boolean functions for λ and δ evelop boolean functions for λ and δ esign circuitry at gate level esign circuitry at gate level Copyright Bengt Oelmann

6 BO 6 esign of state machines Automatic synthesis evelop a state diagram for the problem evelop a state diagram for the problem Write VHL-code that captures the problem Write VHL-code that captures the problem Automatic Automatic synthesis synthesis will will perform perform coding coding of of state state graph graph and and generate generate a a gate gate level level netlist netlist Copyright Bengt Oelmann Example of state machine in VHL architecture rtl of fsm_simple is type state_type is (start, r1, r2); signal state : state_type; -- rtl update_state : process (clk, reset) -- process fsm if reset = '0' then state <= start; elsif clk'event and clk = '1' then case state is when start => if A = '0' then state <= start; else state <= r1; when r1 => if A = '0' then state <= r1; else state <= r2; when r2 => if A = '0' then state <= r2; else state <= start; end case; end process update_state; A=0 output_logic : process(state) case state is when start => z <= '0'; when r1 => z <= '1'; when r2 => z <= '0'; end case; end process output_logic; end rtl; A=0 start z=0 r2 z=0 A=1 r1 z=1 A=1 A=0 A=0 Copyright Bengt Oelmann

7 BO 7 Mealy type in VHL ain=0/yout=0 architecture mealy of fsm2 is ain=1/yout=0 type state is (S1, S2, S3, S4); S1 S4 signal present_state, next_state: state; process (ain, present_state) ain=-/ ain=0/ CASE present_state IS yout=1 yout=1 ain=1/yout=1 when s1 => if (ain = 1 ) then yout <= 0 ; next_state <= s4; else yout <= 1 ; next_state <= s3; S3 S2 ain=-/yout=1 when s2 => yout <= 1 ; next_state <= s3; when s3 => yout <= 1 ; next_state <= s1; when s4 => if (ain = 1 ) then yout <= 1 ; next_state <= s2; else yout <= 0 ; next_state <= s1; end case; process wail until clk = 1 ; present_state <= next_state; end mealy; ain present_state yout next_state Copyright Bengt Oelmann Moore type in VHL library ieee; use ieee.std_logic_1164.all; entity fsm1 is port (ain, clk: in std_logic; yout: out std_logic); end fsm1; architecture moore of fsm1 is type state is (s1, s2, s3, s4); signal present_state, next_state: state; process (ain, present_state) case present_state is when s1 => yout <= 0 ; if (ain = 1 ) then next_state <= s1 else next_state <= s2; when s2 => yout <= 0 ; next_state <= s3; when s3 => yout <= 1 ; next_state <= s4; when s4 => yout <= 1 ; next_state <= s1; end case; process wait until clk = 1 ; present_state <= next_state; end moore; ain=1 ain=0 S1 yout=0 ain=0 S4 yout=1 ain=0 S2 yout=0 ain=0 S3 yout=1 Copyright Bengt Oelmann

8 BO 8 Counters in VHL Modulo-8 counter library ieee; use ieee.std_logic_1164.all; use work.numeric_std.all; entity modulo8 IS PORT(clk: in std_logic; cnt: buffer unsigned (7 downto 0)); EN count8; architecture rtl of count8 is process (clk) if rising_edge(clk) then cnt <= cnt +1; end if end rtl; Copyright Bengt Oelmann Shift-register in VHL entity shift_r is port ( clk, resetn, d_in, shift_en : in std_logic; shift_out : out std_logic_vector(3 downto 0)); end shift_r; architecture rtl of shift_r is signal shift_reg: std_logic_vector(3 downto 0); process (clk, resetn) if resetn = '0' then shift_reg <= (others=>'0'); elsif clk'event and clk = '1' then if shift_en='1' then shift_reg(3 downto 1) <= shift_reg(2 downto 0); -- shift_reg <= shl(shift_reg, "1"); -- shift_reg <= shift_reg sll 1; shift_reg(0) <= d_in; d_in shift_out shift_en resetn Alternative ways shift_out <= shift_reg; end rtl; Copyright Bengt Oelmann

9 BO 9 Memories in VHL A RAM or ROM can be designed in two ways Use the datatype array Use a pre-defined macro cell for the memory device Copyright Bengt Oelmann Example: 4 8 ROM in VHL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ROM is port ( address : in std_logic_vector(1 downto 0); dout : out std_logic_vector(7 downto 0)); end ROM; architecture rtl of ROM is type rom_table is array (0 to 3) of std_logic_vector(7 downto 0); constant rom_contents : rom_table := rom_table'(" ", " ", " ", " "); -- rtl dout <= rom_contents(conv_integer(address)); end rtl; Copyright Bengt Oelmann

10 BO 10 Example #1: RAM in VHL architecture rtl of rmodul is component RAM4_8 port ( din: in std_logic_vector(7 downto 0), address0, address1, we : in std_logic; dout : out std_logic_vector(7 downto 0); end component; efine existing RAM module existing in a library -- rtl ram1: RAM4_8 port map ( din => d, address0 => a0, address1 => a1, we => we, dout => q) end rtl; din a0 a1 we RAM4_8 din dout address0 address1 we q Copyright Bengt Oelmann Example #2: RAM in VHL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ram32_16 is port ( addr : in std_logic_vector(4 downto 0); clk, we_n : in std_logic; din : in std_logic_vector(15 downto 0); dout : out std_logic_vector(15 downto 0)); end ram32_16; architecture rtl of ram32_16 is type ram_type is array (31 downto 0) of std_logic_vector(15 downto 0); signal ram_array : ram_type; process(clk) if clk'event and clk='1' then if we_n='0' then ram_array(conv_integer(addr)) <= din; efine an matrix RAM32_16 din dout addr we_n dout <= ram_array(conv_integer(addr)); end rtl; Copyright Bengt Oelmann

11 BO 11 FSM and datapath Contents General design modell esign example Copyright Bengt Oelmann Components in an digital design A digital design consists of At least one control unit (FSM) At least one datapath unit For example, adder, multiplier, comparator Register for temporary storage of variables Often a design consists of many controllers and datapaths esign modell: FSM with datapath escribes the function of the designs containing both control unit and datapath Copyright Bengt Oelmann

12 BO 12 FSM with datapath Control inputs Control signals ata inputs Control unit atapath control outputs Status signals ata outputs control inputs ata inputs FSM control outputs ata outputs Copyright Bengt Oelmann esign example esign a function computing: y = a x + b Type escription #bits in, data values, positive integer, for a, x and b in sequence 8 start in, control Activate computation of Y, aktive high 1 busy out, control indicate that unit is busy computing 1 Y out, data The computed value Y 17 reset in, control Initialize the unit 1 clk start a = 5 x = 3 b = 10 busy Y Y=25 Copyright Bengt Oelmann

13 BO 13 Cont. esign example start reset clk Y = a x + b Y busy External control signals Controlling the unit External data signals reset start internal control signals Control unit storea storepr atapath External control signal busy Y Copyright Bengt Oelmann Cont. esign example Start=0 start busy = 0 storea = 0 storepr = 0 storea clk EN geta Start=1 busy = 1 storea = 1 storepr = 0 A X multax busy = 1 storea = 0 storepr = 1 storepr clk EN B addb busy = 1 storea = 0 storepr = 0 A X + Y A X+B Copyright Bengt Oelmann

14 BO 14 Summary All digital designs follow the modell of FSM esign flow Specify the algorithm to be implemented Identify Which components are needed in the datapath Which states are needed in the control unit Which control signals are needed to the datapath Which status signals are needed to the control unit evelop State Transition Graph for the control unit Block diagram for the data path Copyright Bengt Oelmann