The CPU and Memory. How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram:

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1 The CPU and Memory How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram: 1

2 Registers A register is a permanent storage location within the CPU. Registers may contain: a memory address for communication with memory an input or output address data is stored for an arithmetic or logic operation an instruction in process of execution codes for special purposes - e.g. keeping track of status conditions for conditional branch instructions The Little Man Computer had a single register - the accumulator 2

3 Register Characteristics: directly wired within CPU not addressed as memory locations for which access time is slow manipulated by CPU during execution may be of different sizes depending on function Register names and functions: program counter register (PC) - holds address of current instruction instruction register (IR) - holds actual instruction being executed together with parameters memory address register (MAR) - holds address of a memory location memory data register (MDR) - holds data being stored or retrieved from memory location addressed by MAR status registers - indicate such as: arithmetic/logic conditions, memory overflow, power failure, internal error, etc. 3

4 Memory- operation - capacity - implementations Operations on memory - role of the MAR and MDR MAR holds an address of a sequence of adjacent bytes - usually 8 A decoder interprets address - opens up circuits (lines) to location Each bit of MDR may be connected to each bit of memory - so when MAR opens circuits to addressed location : a connection is made from each of the data bits at addressed location to corresponding bit in MDR condition of memory bit is transfered to corresponding MDR bit conversely condition of MDR bit can be transfered to corresponding memory bit 4

Relation between MAR and MDR For the case when addresses are expressed in 32 bits and memory locations are addressed as large 8 byte chunks = 64 bits --- A given 32 bit memory address is decoded by

5 Relation between MAR and MDR For the case when addresses are expressed in 32 bits and memory locations are addressed as large 8 byte chunks = 64 bits --- A given 32 bit memory address is decoded by Address Decoder to effectively open circuits (lines) between bits of the memory data register and bits of the 8 byte addressed memory location. Data in memory location can be transferred to MDR by turning on bits in MDR that correspond to bits turned on in memory. Conversely data can be transfered from MDR to an addressed memory location. 5

6 Memory capacity The addressable capacity of a computer is related to the size of the Memory Address Register. A 32 bit registrar allows 2 32 = 4,294,967,296 addresses Each address indicates position of a byte A 32 bit register allows possibility of addressing 4 GB (gigabytes) - 4 billion bytes. Notice we round to the nearest billion For full capacity to be realized computer must contain at least 4GB of physical memory 6

7 Memory implementations Magnetic core memory - small bit of magnetic material for each bit of memory. Small wires connect to magnetic bits that allow to electrical current that will change polarity. Expensive - but non-volatile - military & space applications RAM (random access memory) dynamic RAM = DRAM network of electrically-charged points quickly accessible any portion can be directly accessed - thus random access charge must be renewed every few milliseconds - thus volatile inexpensive 7

8 static RAM = SRAM faster, more expensive, most computers have small amount for high speed access - also called cache memory - also volatile ROM - read only memory fixed part of computer circuits - called mask ROM used in older computers more recent types allow for in frequent and slow re-writing - EEPROM or Flash Rom - used in electronic devices - cameras, cell- phones, automobiles,... 8

9 Fetch-Execute Instruction Cycle Computer designed to execute instructions sequentially. The program counter register (PC) contains the address in memory of location containing next instruction to execute. Program counter was set by previous instruction Following steps occur automatically - hardwired - part of control unit Step 1: address of instruction moved from PC to MAR - this automatically transfers content of addressed location to MDR - thus MDR contains the instruction and its parameters Step 2: contents of MDR is transfered to instruction register (IR) Step 3: address part of instruction (if there is one) moved to MAR Step 4: the instruction in IR is executed Step 5: the program counter register is updated to address of next instruction 9

10 Example: (Little Man Computer syntax) Given information: PC contains number 65 - the address of 65th box Box 65 contains the instruction that is: load contents of box 90 to accumulator (A). Box 90 contains number 111 The cycle: Step 1: address 65 transfers to MAR - the contents of box 65 transfered automatically to MDR - thus MDR contains 590 Step 2: contents of MDR transfered to IR - thus IR contains 590 Step 3: the address part of the instruction - that is 90 - is transfered to MAR and the contents of address 90 automatically transfered to MDR Step 4: contents of 90 added to accumulator (A) - thus A contains 111 Step 5: PC updated 10

Fetch-Execute Example: Load Accumulator Assume: Simple Eight bit system. Thirty-two memory locations (0 to 31). Load instruction is 0101 binary or 5 decimal.

11 Fetch-Execute Example: Load Accumulator Assume: Simple Eight bit system. Thirty-two memory locations (0 to 31). Load instruction is 0101 binary or 5 decimal. Value in location 15 is ten (ie: binary ) PC (program counter) is at 5 and is about to be incremented. The instruction, , is in location 6 - instructions are considered to consists of 2 parts - 3 bits at high end for operation code followed to right by 5 bits for address Then... 11

12 CPU Before PC increments PC: = 05 IR: (previous) MAR: (previous) MDR: (previous) A: (previous) 06: = 5 15 Location 0 12

13 Increment PC: PC = PC + 1 Using instruction in location 6 load contents of location 15 to accumulator PC: = 06 IR: (previous) MAR: (previous) MDR: (previous) A: (previous) 06: = 5 15 Location 0 13

14 MAR loaded with PC: PC -> MAR PC: = 06 IR: (previous) MAR: = 06 MDR: (previous) A: (previous) 06: = 5 15 Location 0 14

15 Memory Location Accessed and Contents to be Placed in MDR: PC: = 06 IR: (previous) MAR: = 06 MDR: (previous) A: (previous) 06: =

16 Memory Location Accessed and Contents Placed in MDR: PC: = 06 IR: (previous) MAR: = 06 MDR: = 5 15 A: (previous) 06: Location 0 16

17 MDR copied to IR: MDR -> IR PC: = 06 IR: MAR: = = 06 MDR: = A: (previous) 06: Location 0 17

18 IR [ address part ] -> MAR PC: = 06 IR: = 5 15 MAR: 1111 =15 Address portion transfered to MAR MDR: = 5 15 A: (previous) 06: Location 0 18

19 Location in MAR (01111) Accessed PC: = 06 IR: MAR: 1111 = connection to memory established =15 MDR: A: (previous) 06: Location 0 19

20 Contents of loaded into MDR PC: = 06 IR: MAR: 1111 MDR: data in memory transfered A: (previous) 06: Location 0 20

21 IR [op code] executed: MDR -> A PC: = 06 IR: MAR: 1111 MDR: op code 5 loads contents of MDR A: : Location 0 21

22 Finished! PC: = 06 IR: MAR: 1111 MDR: A: : Location 0 22

Now the next instruction: Assume: Value in location 7 is 001 10010. Add instruction is 001.

23 Now the next instruction: Assume: Value in location 7 is Add instruction is 001. Value in location 18 is seventy-one (i.e.: binary ) Everything else is as we left it! Then... 23

24 PC = PC + 1 PC: = 7 IR: MAR: MDR: A: : : : Location 0 24

25 PC -> MAR PC: IR: MAR: MDR: A: : : : Location 0 25

26 MAR Accesses Location = 7 PC: IR: MAR: MDR: A: : : : Location 0 26

27 Contents of > MDR PC: IR: MAR: MDR: A: : : : Location 0 27

28 MDR -> IR PC: IR: MAR: MDR: A: : : : Location 0 28

29 IR [address] -> MAR PC: IR: MAR: MDR: A: : : : Location 0 29

30 Location =18 [MAR] Accessed PC: IR: MAR: MDR: A: : : : Location 0 30

31 Contents of [10010] -> MDR PC: IR: MAR: MDR: A: : : : Location 0 31

32 IR [opcode] executed: A = A + MDR PC: IR: MAR: MDR: A: : : : Location 0 32

33 To Continue: The process continues in the same fashion, more or less, until a stop or halt instruction is encountered. 33

34 Instructions General Format: Op code 8 bits address fields How address fields are used varies with CPU design Sometimes - an address implicit in operation definition - Little Man load and store operations always explicitly stated - fixed length instruction sets Explicit addresses: memory addresses or register codes 34

35 Example: Assume: an amount x in location with address X an amount y in location with address Y R pointer to location of a register Add R X Y adds contents of address X to contents of address Y and places result in register R 35

36 Instruction types: Data movement - one memory location to another memory location to register register to memory location register to register Arithmetic operations - different operations for: add, subtract, multiply, divide for integers and for floating point different operations for various expressions of integers - signed or unsigned and various byte lengths bits signed name 8 byte char 16 short short 32 int int unsigned name 64 long lomg 36

37 Boolean Operations Given a bit stream - a sequence of zeros and ones 1 means the bit is on or true 0 means the bit is off or false The operation not - indicated as or! every 0 becomes 1 and every 1 becomes 0 ( ) = ( ) For pair of bit streams p and q AND, OR and XOR operations - 37

38 Boolean Operations Given a bit stream - a sequence of zeros and ones 1 means the bit is on or true 0 means the bit is off or false The operation not - indicated as or! every 0 becomes 1 and every 1 becomes 0 ( ) = ( ) For pair of bit streams p and q AND, OR and XOR operations - p q p ANDq p OR q p xor q

39 Single operand instructions Add one or subtract one from register or memory location Bit manipulation instructions Shift and rotate instructions Various conventions Program control jump and call/return instructions Stack instructions address values of locations of data (e.g. intermediate calculations) stored sequentially in memory. 32 bit stack - sequential blocks of 32 bits - lower order block called bottom - high order block called top push adds to top - pop removes from top Multiple data instructions operations on blocks of data e.g. in graphics, multiplication of 4x4 matrices 38

The von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store.

The von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store. IT 3123 Hardware and Software Concepts February 11 and Memory II Copyright 2005 by Bob Brown The von Neumann Architecture 00 01 02 03 PC IR Control Unit Command Memory ALU 96 97 98 99 Notice: This session