End Semester Examination CSE, III Yr. (I Sem), 30002: Computer Organization

Transcription

1 Ed Semester Examiatio CSE, III Yr. (I Sem), 30002: Computer Orgaizatio Istructios: GROUP -A 1. Write the questio paper group (A, B, C, D), o frot page top of aswer book, as per what is metioed i the questio paper. 2. Attempt all questios. 3. Write thecorrect choice a, b, c, or diaswer book, formultiple choice questios (MCQs). 4. Wrog aswer for a MCQ carries 1 4 of its full weightage. 5. Except MCQs, give the detailed aswer/solutio for each questio. Max. Marks=40 Time= 3 Hrs. 1. (a) The ALU, S, T, the bus ad all the registers i the data path are of idetical size. All operatios icludig icremetatio of the PC ad the GPRs (geeral purpose registers) are to be carried out i the ALU. Two clock cycles are eeded for memory read operatio the first oe for loadig address i the MAR ad the ext oe for loadig data from the memory bus ito the MDR. (ext two questios) MAR MDR S T IR PC GPRs ALU i. The istructio add R0, R1 has the register trasfer iterpretatio R0 R0 + R1. The miimum umber of clock cycles eeded for executio cycle of this istructio is: (2) (a) 2 (b) 3 (c) 4 (d) 5 Aswer: (b) 3. Oe cycle to load R0 i accumulator register S, oe cycle to add, oe cycle to store value i register R0. ii. The istructio call R, sub is a two word istructio. Assumig that PC is icremeted durig the fetch cycle of the first word of the istructio, its register trasfer iterpretatio is R <= PC +1; PC <= M[PC]; 1

2 The miimum umber of CPU clock cycles eeded durig the executio cycle of this istructio is: (2) (a) 2 (b) 3 (c) 4 (d) 5 Aswer: (b) 3. Oe cycle to icremet PC, oe cycle to load PC ito MAR, oe cycle to fetch memory cotet ad load ito PC. (b) i. A CPU has 24-bit istructios. A program starts at address 300 (i decimal). Which oe of the followig is a legal program couter (all values i aswers are i decimal)? Assume that each memory locatio is of oe byte size. (2) (a) 400 (b) 500 (c) 600 (d) 700 Aswer: (c) 600. Sice each istructio is 3 byte (24 bit) log ad memory locatios are oe byte each, the legal PC values are address, where address mode 3 == 0. ii. Which oe of the followig is true for a CPU havig a sigle iterrupt request lie ad a sigle iterrupt grat lie? (1) (a) Neither vectored iterrupt or multiple iterruptig devices are possible (b) Vectored iterrupts are ot possible but multiple iterruptig devices are possible. (c) Vectored iterrupts ad multiple iterruptig devices are both possible (d) Vectored iterrupt is possible but multiple iterruptig devices are ot possible Aswer (b). Because the vectored iterrupts requires separate iterrupts. iii. For the elemets of sets {A,B,C,D} ad {1,2,3,4} (1) (A) DMA I/O (1) High speed RAM (B) Cache (2) Disk (C) Iterrupt I/O (3) Priter (D) Coditio code Register (4) ALU followig is the correct matchig: (a) A-4 B-3 C-1 D-2 (b) A-2 B-1 C-3 D-4 (c) A-4 B-3 C-2 D-1 (d) A-2 B-3 C-4 D-1 Aswer (b) iv. Purpose of start-bit i RS232C serial commuicatio protocol is: (1) (a) to sychroize receiver for receivig every byte (b) to sychroize receiver for receivig a sequece of bytes (c) a parity bit (d) to sychroize receiver for receivig the last byte Aswer (a) v. I serial commuicatio employig 8-data bits, a parity bit ad 2 stop bits, the miimum baud rate required to sustai a trasfer rate of 300 characters per secods is: (1) (a) 2400 baud (b) baud (c) 4800 baud (d) 1200 baud Total bits per characters = 8+2+1=11, bits for 300 characters/sec = 300*11 = 3300 (baud). So miimum speed out of the give speeds is Aswer: (c) 4800 baud vi. A hard disk with a trasfer rate of Mbytes/secod is costatly trasferrig data to memory usig DMA. The processor rus at 600 MHz, ad takes 300 ad 900 clock cycles to iitiate ad complete DMA trasfer respectively. If the size of the trasfer is 20 Kbytes, what is the percetage of processor time cosumed for the trasfer operatio? (3) (A) 5.0% (B) 1.0% (c) 0.5% (D) 0.1% Aswer:(D) 0.1% Time for trasfer of 20kbytes= = 3 sec. This is because for a oe word trasfer, the address is set o bus i oe clock ad 2

3 other cycle for memory read. No. of cycles for trasfer = = 6 5 cycles. Total cycles The fractio of time of cpu spet = = 0.1% vii. The followig code is to ru o a pipelied processor with oe brach delay slot: I1 : ADD R2 <- R7 + R8 I2 : SUB R4 <- R5 R6 I3 : ADD R1 <- R2 + R3 I4 : STORE Memory [R4] <- R1 BRANCH to Label if R1 == 0 Which of the istructios I1, I2, I3 or I4 ca legitimately occupy the delay slot without ay other program modificatio? (2) (a) I1 (b) I2 (c) I3 (d) I4 Aswer: (D) I4: sice R1 is oly read i I4, ad its value will remai as it is while BRANCH is executed ad after BRANCH get executed, sice i BRANCH R1 is oly read. 2. Suppose a stack represetatio supports, i additio to PUSH ad POP, a operatio REVERSE, which reverses the order of the elemets o the stack. (a) To implemet a queue usig the above stack implemetatio, show how to implemet ENQUEUE usig a sigle operatio ad DEQUEUE usig a sequece of three operatios. (3) For Queue, we keep TOS (top of stack) as rear of the queue, ad BOS (bottom of stack) as frot of the queue. Thus, to add i queue from back, there is oly istructio: PUSH. To remove from the frot of queue, the three istructios i order are: REVERSE, POP, REVERSE. (b) The followig postfix expressio, cotaiig sigle digit operads ad arithmetic operators + ad *, is evaluated usig a stack. (3) show the cotets of stack: i after evaluatio of 5 2 * 3 4 * the steps are as follows: i. 5 is read from iput ad pushed oto stack ii. 2 is read from iput ad pushed oto stack iii. * is read ad result pop*pop = is pushed oto stack iv. 3 is read from iput ad pushed oto stack v. 4 is read from iput ad pushed oto stack vi. * is read ad result pop*pop =12 is pushed oto stack The resultat stack is as show below: 12 ii after evaluatio of 5 2 * 3 4 * 5 2 The resultat stack is:

4 iii at the ed of evaluatio. The resultat stack is: Aew microprocessor is beig desiged with a covetioal architecture employig sigleaddress istructios ad 8-bit words. Due to physical size costraits, oly eight distict 3-bit opcodes are allowed. The use of modifiers or the address field to exted the opcode is forbidde. (a) What eight istructios would you implemet? specify the operatios performed by each istructio as well as the locatio of its operads. (3) Aswer The followig eight Istructios are sufficiet: add, load, stor, ad, or, cma, jmp, hlt. Followig is explaatio: i. CMA is complemet accumulator, jp is jump. All istructios, except cma, have two operads, o is explicit ad other is implicit, which is accumulator. cma has o operad, ad takes accumulator as oe implicit operad. ii. The remaiig five bits (d 0...d 4 ) are for operad. d 4 = 0 idicates that operad is i ay oe of the 16 registers, whose umber is represeted by d 3...d 0. iii. whe d 4 = 1, it idicates that operad is i memory, whose address is idicated by the register d 3...d 0. iv. Each of these registers d 0...d 15 is 16 bit, hece total memory of 64 k ca be addressed. v. The register r 0 is accumulator register (8 bits) ad status register to hold status flag for zero/o-zero. jmp is ucoditioal jump istructio. (b) Demostrate that your istructio set is fuctioally complete i some reasoable sese; or if it is ot, describe a operatio caot be programmed usig your istructio set. (3) Aswer It is possible to do ay arithmetic usig add, cma. For example, for subtractio, we do 2 s complemet additio. 2 s complemet is cma, followed with add 1. This 1 ca be kept i a register. The remaiig justificatio is as follows: i. The jump ca be made coditioal subject to the cotet of a register, say r1. If r1=0, the jumps else ot. For ucoditioal jump, keep r1=0. ii. loop ad brachig are thus implemeted, which are ecessary for cotrol. iii. all the logical operatios are possible by ad, or, ot. iv. memory store, ad load from it, are possible by load ad store istructios. v. The RR, RM, MR, MM based istructios are possible. The idirect addressig is ot provided. But that is ot compulsory, as may HLLs have o provisio. vi. You caot do the rotate accumulator. 4. It is required to desig a hardwired cotroller to hadle the fetch cycle of a sigle address of a istructio. The operad should be delivered i the fetch cycle itself. Assume that lower 8-bits of a istructio costitute the operad field. 4

5 (a) Draw the logic schematic of the hardwired cotroller icludig the data paths. (4) Aswer. The aswer is similar to the cotets of slide 9, page 8. The istructio op-code part goes ito IR, ad operad part goes to ay register or accumulator. The cotrol sigals are geerated as give i slide 9 page. The data bus is 16 bits. (b) Give the micro-operatios to realize the above istructio s fetch cycle. (3) Aswer. The aswer ca be foud i slide set 9, page A istructio pipelie has five stages, each stage takes 2 aosecods ad all istructios use all five stages. Brach istructios are ot overlapped, i.e., the istructio after the brach is ot fetched till the brach istructio is completed. Uder ideal coditios, (a) calculate the average istructio executio time assumig that 20% of all istructios executed are brach istructios. Igore the fact that some brach istructios are may be coditioal. (3) Aswer: The five stages are say: FI, DI, FO, EI, WO. After first five istructios, every 2 sec, oe istructio is executed, provided that there is o brach istructio. A brach istructio will take oly 4 states, as there is o WO. So cosumig 4 * 2 = 8 sec. Average time = 1 * * 8 = 3.6 sec. Note: Because the brach istructios are ot overlapped. Explaatio: Avg,time = 0.2 (5 2) +0.8 ((5 2)+( 1) 2) = (+( 1)2) = lim = = 3.6sec (b) If a brach istructio is a coditioal brach istructio, the brach eed ot be take. If brach is ot take, the istructio followig to that istructio ca be overlapped. Whe 80% of all brach brach istructios are coditioal brach istructios, ad 50% of the coditioal brach istructios are such that the brach is take, calculate the average istructio executio time. (3) Aswer 1: Tavg = (1+stall frequecy*stall pealty)*clock time 20% are brach istructios out of which 20% ucoditioal ad 80%coditioal 50% of coditioal are take, we have to cosider oly take brach coditios: so Tavg=(1+0.2( * 0.5)*(5-1) ) *2 =2.96 s (cosiderig 80% as fractio of origial 20%). The detailed explaatio is as follows: Out of 20%, 80% ae coditioal brach istructios. Thus, coditioal brach istructios are= =0.16. The co-coditioal istructios are For 50% of coditioal brach istructios, there is brach, = =0.08. Thus total time is= 2( )+(0.08 )+(0.04 )+( ) 2 = 2(4+0.8) (0.08+4) 2 = lim = 2.96sec Aswer 2: (1+0.8*(0.5*(5-1)))*2 =5.2; here 0.5 correspods to 50% brach istructios where brach has take. (cosiderig 80% as fractio of 0) 5

6 Cosiderig 80% total brach istructios: 0.8(0.5( )+0.5(+( 1)2))+0.2(+( 1)2) Avg.time = = 0.8(5+(5+( 1)))+0.2(8+2) = 0.8(5+(4+)) = = lim = = 5.2sec. 6