Computer Architecture and Organization: L09: CPU Organization
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1 Computer Architecture and Organization: L09: CPU Organization By: A. H. Abdul Hafez 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
2 Outlines 1. Introduction 2. General Register Organization 3. Stack Organization 4. Instruction formats 5. Addressing Modes 6. End 2 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
3 CPU Organization Central Processing Unit (CPU): performs a bulk of data-processing operations. Register set: stores intermediate data used during the execution of the instructions. Arithmetic Logic Unit (ALU): performs the required microoperations for executing the instructions. Control Unit: supervises the transfer of information among the registers and instructs the ALU as to which operations to perform. 3 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU Based on register set, there are three types of CPU Organization: 1. Single accumulator organization: like basic computer design. 2. General register organization: a set of general registers to store data. 3. Stack organization.
4 2- General Register Organization In single accumulator organization, memory locations are needed for storing counters, return address, temporary results, and partial products during multiplication. Memory access is the most time consuming operation in a computer. More convenient and more efficient to store these intermediate values in processor registers. They are connected among themselves through a common bus system. 4 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
5 Example R1 R2 + R3 - MUX A selector (SELA): to place the content of R2 into bus A. - MUX B selector (SELB): to place the content of R3 into bus B. - ALU operation selector (OPR): to provide the arithmetic addition A + B. - Decoder destination selector (SELD): to transfer the content of the output bus into R1. 5 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
6 Control Word - Control word of 14 bits is needed to specify a microoperation in the CPU. - Control words are stored in the control memory. - Binary control word for the CPU (microops) will come from the outputs of the control memory. - 3 bits of SELA select a source register for A input of the ALU. - 3 bits of SELB select a source register for B input of the ALU. - 3 bits of SELD select a destination register using the decoder and its seven load outputs. - 5 bits of OPR select one of the operations in the ALU. When SELA or SELB = 000 Selection of external input data. When SELD = 000 Selection of external output data. 6 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
7 Operation Selection OPR field has five bits and each operation is designated with a symbolic name. 7 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
8 Examples of Microoperations R1 R2 R3 R2 = A input R3 = B input A - B R1 = Destination register 8 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
9 Other Microoperations - We assign 000 to any unused field when formulating the binary contol word. - ALU operation TSFA places the data from register, through the ALU, into the output terminals. - Direct transfer from input to output is accomplished with a control word of all 0 s. 9 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
10 3- Stack Organization Stack is a memory unit with an address register that can count only (after an initial value is loaded into it). The register that holds the address for the stack is called a Stack Pointer (SP). SP always points at the top item in the stack. Two operations of the stack: - Insertion: PUSH - Deletion: POP Incrementing or Decrementing SP 10 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
11 Register Stack Stack of 64 words reserved into the memory (SP = 6). LIFO: Last In First Out PUSH A, B, C: SP is incremented. POP C, B, A: SP is decremented. At the first: SP = 0 At the end of PUSH: SP = 3 (Increment) At the end of POP: SP = 0 (Decrement) - First item is stored at address 1. - Last item is stored at address CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
12 When EMTY = 1: EMTY: one bit register, EMTY = 1: when stack is empty. FULL: one bit register, FULL = 1: when stack is full. SP SP + 1: increment SP. M[SP] DR: write item on top of stack. If SP = 0 then FULL 1: check if stack is full. EMTY 0: mark the stack not empty. PUSH write into stack from DR When EMTY = 0: DR M[SP]: read item from top of stack. SP SP - 1: decrement SP. If SP = 0 then EMTY 1: check if stack is empty. FULL 0: mark the stack not full. POP read from stack to DR 12 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
13 Memory Stack Portion of computer memory partitioned into 3 segments: - Program (pointed by PC): fetch phase. - Data (pointed by AR): execute phase (read an operand). - Stack (pointed by SP): PUSH or POP into or from the stack. PUSH operation: SP SP - 1 M[SP] DR Overflow (full stack): Processor register holds the upper limit = Underflow (empty stack): Processor register holds the lower limit = POP operation: DR M[SP] SP SP CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
14 The end of the Lecture Thanks for your time Questions are welcome 14 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
15 4- Instruction formats Structure computers is normally described in reference manuals provided with the system. Internal construction of the CPU: processor registers, all hardware-implemented instructions Interpret each instruction code by the control unit. Control functions needed to process the instruction. 15 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
16 Instruction format : rectangular box symbolizing the bits of the instruction as they appear in memory words. The most common fields found in instruction formats are: - Operation code: specifies the operation to be performed. - Addresse field: designates a memory address or a processor register. - Mode field: specifies the way the operand or the effective address is determined. Address Field Operands in memory: specified by their memory addresses. Operands in processor registers: specified by register address of k K bits one of 2 registers in the CPU. 16 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
17 CPU Organization 1- Single accumulator organization: ADD X : AC AC + M[X] (one address field ) 2- General register organization: ADD R1, R2, R3: R1 R2 + R3 (3 register address fields) ADD R1, R2: R1 R1 + R2 (2 register address fields) MOV R1, R2: R1 R2 (2 register address fields) ADD R1,X: R1 R1 + M[X] (2 address fields) 3- Stack organization: ADD: (no address field) is performed on the two items that are on top of the stack. POP the two numbers from the stack (source). PUSH the sum into the stack (destination). 17 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
18 Influence of the number of addresses on computer programs X = (A + B) * (C + D) General Register Computer with Three-Address Instructions 18 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
19 X = (A + B) * (C + D) General Register Computer with Tow-Address Instructions 19 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
20 X = (A + B) * (C + D) Accumulator type Computer with One-Address Instructions 20 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
21 X = (A + B) * (C + D) Stack Organized Computer with Zero-Address Instructions 21 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
22 X = (A + B) * (C + D) RISC Instructions RISC : Reduced Instruction Set Computer 22 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
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