Computer Organization CS 206 T Lec# 2: Instruction Sets

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1 Computer Organization CS 206 T Lec# 2: Instruction Sets

2 Topics What is an instruction set Elements of instruction Instruction Format Instruction types Types of operations Types of operand Addressing mode RISC & CISC

3 1. What is an Instruction Set? The operation of the processor is determined by the instruction it executes, referred to as machine instructions or computer instructions The complete collection of different instructions that the processor can execute is referred to as the processor instruction set Machine language: binary representation of operations and (addresses of) arguments Assembly language: mnemonic representation for humans, e.g., OP A,B,C (meaning A <- OP(B,C))

4 2. Elements of an Instruction Operation code (opcode): specifies the operation to be performed (binary code) Do this: ADD, SUB, MPY, DIV, LOAD, STOR Source operand reference: the operation may involve one or more source operand as input for the operation. To this: (address of) argument of op, e.g. register, memory location

5 2. Elements of an Instruction Result operand reference: the operation may produce a result. Put the result here (as above) Next instruction reference (often implicit): this tells the processor where to fetch the next instruction after complete the current one (in most cases the next instruction is immediately follow the current one). When you have done that, do this: BR

6 Instruction Cycle State Diagram

7 3. Instruction Formats An instruction format defines the layout of the bits of an instruction. An instruction format must include an opcode and, implicitly or explicitly, zero or operands. The format must implicitly or explicitly, indicate the addressing mode for each operand. Usually more than one instruction format in an instruction set

8 A simple Instruction Format (using two addresses)

9 3.1 Instruction Representation Each instruction is represented by a sequenced of bits. The instruction is divided into fields according to the constituent elements of the instruction.

10 3.2Instruction Length Affected by and affects: Memory size Memory organization - addressing Bus structure, e.g., width CPU complexity CPU speed Trade off between powerful instruction repertoire and saving space

11 4. Instruction Types Data transfer: registers, main memory, stack or I/O Data processing: arithmetic, logical Control: systems control, transfer of control Data Movement: I/O instruction.

12 5. Types of Operations The number of different opcodes varies widely from machine to machine. However, the same general types of operations are found on all machines.

13 5.1 Data Transfer Store, load, exchange, move, clear, set, push, pop Specifies: source and destination (memory, register, stack), amount of data May be different instructions for different (size, location) movements, e.g., IBM S/390: L (32 bit word, R<-M), LH (halfword, R<-M), LR (word, R<-R), plus floatingpoint registers LER, LE, LDR, LD Or one instruction and different addresses, e.g. VAX: MOV

14 5.2 Input/Output May be specific instructions, e.g. INPUT, OUTPUT (issue command to I/O module May be done using data movement instructions (memory mapped I/O) May be done by a separate controller (DMA): Start I/O, Test I/O

15 5.3 Arithmetic Add, Subtract, Multiply, Divide for signed integer (+ floating point and packed decimal) may involve data movement May include Absolute ( a ) Increment (a++) Decrement (a--) Negate (-a)

16 5.4 Logical Bitwise operations: AND, OR, NOT, XOR, TEST, CMP, SET Shifting and rotating functions, e.g. logical right shift for unpacking: send 8-bit character from 16-bit word arithmetic right shift: division and truncation for odd numbers arithmetic left shift: multiplication without overflow

17 5.5 Transfer of Control Update program counter Skip, e.g., increment and skip if zero: ISZ Reg1, cf. jumping out from loop, return, execute.

18 6. Types of Operand Addresses: immediate, direct, indirect, stack Numbers: integer or fixed point (binary, twos complement), floating point (sign, significand, exponent), (packed) decimal (246 = ) Characters: ASCII (128 printable and control characters + bit for error detection) Logical Data: bits or flags, e.g., Boolean 0 and 1

19 7. Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack

20 8.1 Immediate Addressing Operand is part of instruction Operand = address field e.g., ADD #5 Add 5 to contents of accumulator 5 is operand No memory reference to fetch data Fast Limited range

21 8.2 Direct Addressing Address field contains address of operand Effective address (EA) = address field (A) e.g., ADD A Add contents of cell A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations needed to work out effective address Limited address space (length of address field)

22 Direct Addressing Diagram Opcode Instruction Address A Memory Operand

23 8.3 Indirect Addressing (1) Memory cell pointed to by address field contains the address of the operand EA = (A) Look in A, find effective address and look there for operand E.g. ADD (A) Add content of cell pointed to by content of A to accumulator

24 Indirect Addressing (2) Large address space 2 n where n = word length May be nested, multilevel, cascaded e.g. EA = (((A))) Multiple memory accesses to find operand Hence slower

25 Indirect Addressing Diagram Instruction Opcode Address A Memory Pointer to operand Operand

26 8.4 Register Addressing (1) Operand is held in register named in address field EA = R Limited number of registers Very small address field needed Shorter instructions Faster fetch

27 Register Addressing (2) No memory access Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing see register renaming cf. direct addressing

28 Register Addressing Diagram Opcode Instruction Register Address R Registers Operand

29 8.5 Register Indirect Addressing Cf. indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2 n ) One fewer memory access than indirect addressing

30 Register Indirect Addressing Diagram Opcode Instruction Register Address R Memory Registers Pointer to Operand Operand

31 8.6 Displacement Addressing EA = A + (R) Address field holds two values A = base value R = register that holds displacement or vice versa See segmentation

32 Displacement Addressing Diagram Opcode Register R Instruction Address A Memory Registers Displacement + Operand

33 Instruction Set Architecture (ISA) CISC is an acronym for complex instruction set computer. E.g. x86 family RISC stands for reduced instruction set computer, e.g. Pentium and MIPS

34 RISC Reduced Instruction Set Computer Key features Large number of general purpose registers (or use of compiler technology to optimize register use) Limited and simple instruction set Emphasis on optimising the instruction pipeline

35 RISC Characteristics One instruction per cycle Register to register operations Few, simple addressing modes Few, simple instruction formats Also Hardwired design (no microcode) Fixed instruction format But More compile time/effort

36 9.2 RISC Machines The underlying philosophy of RISC machines is that a system is better able to manage program execution when the program consists of only a few different instructions that are the same length and require the same number of clock cycles to decode and execute. RISC systems access memory only with explicit load and store instructions. In CISC systems, many different kinds of instructions access memory, making instruction length variable and fetch-decode-execute time unpredictable. 36

37 9.2 RISC Machines The difference between CISC and RISC becomes evident through the basic computer performance equation: RISC systems shorten execution time by reducing the clock cycles per instruction. CISC systems improve performance by reducing the number of instructions per program. 37

38 9.2 RISC Machines It is becoming increasingly difficult to distinguish RISC architectures from CISC architectures. Some RISC systems provide more extravagant instruction sets than some CISC systems. Some systems combine both approaches. The following two slides summarize the characteristics that traditionally typify the differences between these two architectures. 38

39 9.2 RISC Machines RISC Multiple register sets. Three operands per instruction. Parameter passing through register windows. Single-cycle instructions. Hardwired control. Highly pipelined. Continued... CISC Single register set. One or two register operands per instruction. Parameter passing through memory. Multiple cycle instructions. Microprogrammed control. Less pipelined. 39

40 9.2 RISC Machines RISC Simple instructions, few in number. Fixed length instructions. Complexity in compiler. Only LOAD/STORE instructions access memory. Few addressing modes. CISC Many complex instructions. Variable length instructions. Complexity in microcode. Many instructions can access memory. Many addressing modes. 40

41 End of Slides Chapter 10: Instruction Sets: Characteristics and Functions Addressing Modes. Chapter 11: Instruction Sets: Addressing Modes and Format. Chapter 13: Reduced Instruction Set Computers (RISC).

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