An Environment of State Transition Diagram Translation

Transcription

1 International Conference on Manufacturing and Engineering Systems An Environment of State Transition Diagram Translation Alexandre C. R. Silva(*), Tiago da Silva Almeida, Silvano R. Rossi UNESP São Paulo State University, UNESP São Paulo State University, UNCPBA Universidad Nacional del Centro de la Provincia de Buenos Aires Abstract The lack of standard to electronic circuits modeling made possible the development of a lot of tools and modeling languages for electronic circuits. In this way it is necessary the use of several tools to be used on different descriptions stage of the designs. This paper presents a tool called SF2HDL (Stateflow to Hardware Description Language or State Transition Table) that translates a finite state machine on state transition diagram representation, described by Stateflow tool, into a input file standard for TABELA program or into a file behavioral VHDL directly. Using the TABELA program, after an optimization process, the VHDL code on register transfer level is generated what permits comparisons with results obtained of synthesis. The finite state machine must be described by Mealy model and the user can describe the machine on high level abstraction using all Simulink support. The tool was very efficient on computational cost and it made translation of several cases, for the two VHDL description models. Every state machine translated was simulated and implemented on device EP2C20F484C7, using Quartus II environment. Keywords: Finite state machine, VHDL, Synthesis. Introduction The integrated circuits are responsible for fast development in digital systems area. The size minimization and cost of circuit components allow quite complex systems to be implemented inexpensively and in a small time space. Day after day the integrated circuits technology has allowing that more components are inserted into single silicon chip, consequently digital systems have also been increasing its complexity. Therefore, the design details on gate-level have become tedious and began to consume much time to design. For that reason the modelling task and simulation become more and more important before the process of synthesis of an electronic circuit. That importance is evidenced in [1] where was proposed a simulator for the language VHDL-AMS developed in the Matlab environment, denominated S.A.M.S.A.. In that work, it was used as case study a converter model ADC (Analog to Digital Converter) of low potency. The tool is compared with others simulators of VHDL-AMS code available commercially. Efficient modeling of digital systems projects can be made through of finite state machine, as example in [2] was presented a tool capable to translate a finite states machine described through the language VHDL in a visual representation of the same. The focus of the work was the modeling and the verification (through finite state machine) of systems with critical applications as, for example, systems of air traffic control. The work presented in [2] is the evidence of importance of translation tools between different modeling forms. An other example that we can cite is the tool called SF2VHD, presented in [3]. That tool is capable to translate hierarchical models of finite states machine, modeled in the Stateflow environment, in a code corresponding structural VHDL. In the work [4] it was developed a tool called Sim2HDL, which accomplishes the automatic translation of Simulink models in a hardware description language, in the attempt to drastically reduce the time of project. The generated language can be VHDL as Verilog, on behavioral level description, and the system can be implemented in FPGAs using commercial synthesizers. In this sense, this paper presents a tool that translates finite state machine described by state transition diagram into a suitable VHDL code directly or into an input file for TABELA program, which generates and performs the optimization of control function and output function. The diagrams must be described by Mealy model using the Stateflow environment from Simulink

2 ICMES 2009 The Matlab software is a mixture of mathematics and models used on projects. It is used primarily to perform mathematical calculations, visualizing and analyzing data and writing new computer programs. The Simulink is the main product composed of a variety of components. The Simulink is used in simulation, analysis and development of complex dynamic systems, continuous, discrete or hybrid [5]. The Stateflow can be considered as a continuation of Simulink. This is an important tool used in modeling and simulation of finite state machines. The Stateflow allows the modeling of both machines as Mealy or Moore model and allows a classical description, native of the tool. The modeling can be done independently using only the Stateflow, but also there may be an interaction with Simulink and Matlab [5]. Some modeling tools commercial incorporate the translation need for different forms of modeling. An example is a Matlab C Compiler tool, developed by Mathworks. That tool translates programs written in Matlab for a corresponding program in the C language. The tool can be installed separately of the Matlab environment. The functionality and main advantages of these tools are described in [6]. Finite State Machine Finite state machines (FSM) or sequential machines are abstract representations of sequential circuit. Their behavior can be described as a sequence of events that occurs in discrete time. A finite state machine can be represented by state diagrams. State diagrams are used to graphically represent a state transition functions set. Having an input event set, the output event set and the next state set can be determined [7]. There are also several other forms to represent finite state machine that differ slightly and have different semantic. The State Transition Table and Petri Net are two examples. Figure 1 shows generic schematic of a finite state machine. The circuit has a finite number of inputs, representing all input variable set {N 1, N 2,,N n }. Thus, the circuit has a finite number m of outputs, determined by the output set of variables {M 1, M 2,,M m } [7]. Figure 1. Schematic of a Finite State Machine. The value in each memory element is called state variables, and the set denoted by {K 1, K 2,,K k } form the state variable set. The values contained in k memory elements define the internal state of finite state machine. The outputs {M 1, M 2,M m } and internal transition functions {S 1, S 2,, S s } depend on external inputs (input functions) and internal states (state functions) of state machine and they are defined by combinational circuits. The values S, which appear in the role of state transitions of machine at time t, determine values of state variables at time t+1 and therefore define the next state of machine [7]. The state transition diagram or the state transition table makes the relationship between present state, next state, input and output. The finite state machines that determine the next state K(t+1) only in the present state K(t) and present input N(t) are called deterministic machines or Markovian. Deterministic machines can be represented by the following equation: Kt ( 1) f[ Kt ( ), Nt ( )] (1) Where, f is a state transition function. The value of output M(t) is obtained through of two ways: or, Mt () gkt [ ()] Mt () gkt [ (), Nt ()] Where, g is an output function. (2) (3) A finite state machine with properties described in equations (1) and (2) is called Moore model and a machine described by equations (1) and (3) is called Mealy model [7]. To illustrate states transition diagram in the Figure 2 is presented a states transition diagram of HDB3 code line, in hexadecimal representation propose in [8]. The encoder needed three parts of memory to store and to identify four successive 0. After, it was necessary a -302-

3 International Conference on Manufacturing and Engineering Systems flip-flop to store the polarity of the pulse (0 for + or 1 for -), and finally other flip-flop to store the polarity of the violation, like this, the encoder requests a minimum of 2 5 = 32 state. The state 00 represents the initial state of the machine, and the two pairs of state 07 and 0F (in the left) and 1F and 17 (in the right) represent the description AMI, what causes the alternate code between +1 and -1 [8]. Figure 2. State transition Diagram for HDB3 code. As case study was used the HDB3 (High Density Bipolar 3) line code, which is a technique for detecting synchronism with bipolar signaling, and it has been used over the years in systems of digital Methodology C++ was the language used to create the SF 2 HDL (Stateflow to Hardware Description Language or states transition table) program, developed on Borland C++ Builder 6 environment. Being a refinement of C language and, consequently, it has its applicability, but use an object-oriented approach [9]. The SF 2 HDL program is a simplified graphical interface that allow user to select between generate an input file to be processed by TABELA program or a file.vhd with a behavioral VHDL description obtained directly from state transition diagram. Figure 3 illustrates the main interface of SF 2 HDL program. The program has a menu called Ferramentas with the following options: a) Nova Tradução, used to open the file with a finite state machine modeled in Stateflow environment, b) Traduzir, which performs the model translation, c) Sair, which terminates the program, and d) Sobre option that displays a screen with a brief comment on the tool developed [9]. The program performs the file reading containing finite state machine, simulated on Stateflow environment. Then, the program finds the state machine structure and it makes a temporary storage of each information. After that state location is generated a list of all states and through the transition locations is generated a transitions list, conditions of inputs and outputs. When the user selects generate the input file for TABELA program, the program shows a message asking what the memory element (flip-flop) will be used in the generated file. The memory element type must be put manually by the user [9]. Thus, from all the information found in the file it is possible to determine the present state, the next state, the input and output of finite state machine. According to the structure of each file all the information is grouped and then is generated the input file for TABELA program and/or the corresponding behavioral VHDL. Figure 4 presents the functional diagram of SF 2 HDL program with all necessary steps to perform the translation, as previously reviewed [9]. Figure 3. Main interface of SF 2 HDL program

4 ICMES 2009 Read File Find State Machine Find State File (Stateflow) Find Transitions List of Transitions List of Input Conditions specified on table form using one line per state transition, so: present state, next state, input, output. The description end is represented by notation "- 100". Figure 5 shows the standard file for TABELA program input with base in the behavior of the states transition diagram of the code HDB3 presented in the Figure 2. The states, the inputs and outputs must be in decimal notation. The finite state machines can be completely or incompletely specified [7]. List of States List of Outputs Obtain Flip- Flop Create File Selected File.vhd (VHDL) File.tab (TABELA) Figure 4. Block diagram of SF 2 HDL. The TABELA program was developed for synthesize of a finite state machine and was implemented in Pascal language by researchers from UNICAMP (Campinas State University). The program generates combinational functions that implement the finite machine described by state transition table. The transition functions and output functions are minimized and the cost of minimization using minterms and maxterms [7]. The transitions are Figure 5. Input file for TABELA program. The program assembles a state transition table storing it in output file. From this table are obtained minterms, maxterms and don t care states of transition functions of all internal flip-flops and circuit output functions. Using Quine-McCluskey algorithm is made the minimization of Boolean functions. Figure 6. Description of HDB3 code on Stateflow

5 International Conference on Manufacturing and Engineering Systems Results For modeling the state transition diagram on Stateflow environment, some rules must obey, as to give a name to the state, contained within the symbol, should never begin with numeric character (0, 1, 2, 3, 4, 5, 6, 7, 8 or 9), and the condition in the transition to the Mealy model must meet the following syntax: [[] et 0]{ s 0;} (4) where e represents the variable that will receive input value. t is a variable that represents a discrete time. s is an output variable. The more external bracket represents the input condition in the transition from one state to another to obtain output. The double equal signs (==) represent the verification of a condition and the equal sign alone (=) represents the allocation of value [5]. For proper functionality of SF 2 HDL program is necessary that the values in transition of model in Stateflow environment, both at input and output are decimal representations. Figure 6 presents the state diagram of HDB3 code on Stateflow environment. In simulation were used several words with signs and bits from varying sizes. However, was standardized in using an entrance word in the simulation of 24 bits being formed by the following bits: The result of the simulation is presented in the Figure 7. Figure 7. Results of simulation on Stateflow. The TABELA program creates a new file, containing a description of Boolean functions from the circuit already minimized. The list below describes some functions generated from the states transition table presented in the Figure 2. FUNCAO D4 ========= MINTERMOS : 0; 8; 48; 17; 49; 18; 50; 19; 51; 20; 52; 21; 53; 22; 54; 23; 55; 25; 57; 26; 58; 27; 59; 28; 60; 29; 61; 30; 62; 31; 63; IMPLICANTES PRIMOS ESSENCIAIS : ESSENCIAL: 20 REDUNDANCIA: 43 -> X1X1XX ESSENCIAL: 18 REDUNDANCIA: 45 -> X1XX1X ESSENCIAL: 17 REDUNDANCIA: 46 -> X1XXX1 ESSENCIAL: 48 REDUNDANCIA: 15 -> 11XXXX ESSENCIAL: 0 REDUNDANCIA: 8 -> 00X000 CUSTO FINAL DE D4 = 18 FUNCAO Z1 ========= MINTERMOS : 1; 33; 7; 39; 8; 11; 43; 13; 45; 17; 49; 23; 55; 27; 59; 29; 61; IMPLICANTES PRIMOS ESSENCIAIS : ESSENCIAL: 16 REDUNDANCIA: 48 -> XX1101 ESSENCIAL: 8 REDUNDANCIA: 48 -> XX1011 ESSENCIAL: 8 REDUNDANCIA: 0 -> ESSENCIAL: 7 REDUNDANCIA: 48 -> XX0111 ESSENCIAL: 1 REDUNDANCIA: 48 -> XX0001 CUSTO FINAL DE Z1 = 27 CUSTO TOTAL DAS 7 FUNCOES = 88 After the minimization by TABELA was used TAB2VHDL program which was generated VHDL code in RTL (Register Transfer Level). The other option is to generate the behavioral VHDL directly without using TABELA program. Figure 8 shows the file with behavioral VHDL code generated. ENTITY Mealy_HD IS PORT( ent: IN INTEGER RANGE 0 TO 1; sai: OUT INTEGER RANGE 0 TO 3; clk, clr: IN BIT ); END Mealy_HD; ARCHITECTURE lpssd OF Mealy_HD IS TYPE tipo_est IS (S0, S1, S2... S31); SIGNAL est_atual, prox_est: tipo_est; BEGIN PROCESS (ent, est_atual) BEGIN CASE est_atual IS WHEN S0 => IF (ent = 0) THEN sai <= 1; prox_est <= S2; ELSE sai <= 1; prox_est <= S12; END IF; END CASE; END PROCESS; PROCESS (clr, clk) BEGIN IF clr = '0' THEN est_atual <= S14; ELSIF clk'event AND clk ='1' THEN est_atual <= prox_est; END IF; END PROCESS; Figure 8. VHDL code generated by SF2HDL

6 ICMES 2009 Figure 9. Simulation of the code of line HDB3. In Figure 9 is shown the simulation of VHDL code generated by SF 2 HDL program on Quartus II environment. After reset signal has been inserted, being used the same word of data used in the simulation that in the Stateflow environment to verify accuracy and violation of HDB3 code too in the Quartus II. The VHDL codes generated by SF 2 HDL program were synthesized and implemented on Cyclone II EP2C20F484C7 model. Conclusion The SF 2 HDL tool was tested in several cases of finite state machines and all have been simulated and synthesized in Quartus II environment and Cyclone II FPGA model EP2C20F484C7, respectively. For the case study of HDB3 code described in this paper, SF 2 HDL program was very effective for translation code modeled on Stateflow, a computational low cost, being accurate in VHDL generation code and the input file for TABELA program corresponding with another programs. Thus this research generated a good tool that allows to the designers to model a finite state machine at high level of abstraction and obtain a corresponding VHDL model which can be synthesized on synthesis tools available commercially. It is also important to say this new translation tools interact with several other tools developed by research group with TABELA program, creating this way a digital synthesis environment. Note that SF 2 HDL program makes the translation of finite state machine and it does not perform work optimize circuit work. Hence, it also needs a translation into a file that serves as input to TABELA program that is able to perform this work. The SF 2 HDL program does not make optimal state assignment to the state machine as well. Thus, it is necessary to use another tool to do that task. In this way circuit synthesis can be really optimize using all the potentialities of developed tools. As next work intend to extend this tool to also realize the translation of finite state machines for the structural VHDL code and the Verilog code corresponding. Acknowledgments The authors acknowledge the PPGEE-FEIS-UNESP, Brazil, Universidad Nacional del Centro del la Pcia. De Buenos Aires, Argentina, CAPES (Program of Social Demand). References [1] ZORZI M., FRANZÈ F. and SPECIALE N. Construction of VHDL-AMS simulator in MatlabTM. In: PROCEEDINGS OF THE 2003 INTERNATIONAL WORKSHOP ON BEHAVIORAL MODELING, 2003, San Jose, USA. Anais San Jose, USA. p [2] NEHME, Carl; LUNDQVIST, Kristina. A TOOL FOR TRANSLATING VHDL TO FINITE STATE MACHINES.In: DIGITAL AVIONICS SYSTEMS ONFERENCE, 22., 2003, USA. Anais... USA, p.1-7. [3] CAMERA, Kevin. SF2VHD: A Stateflow to VHDL Translator f. Dissertação (Mestrado em Electrical Engineering and Computer Science) University of California, Berkeley, [4] SBARCEA, Bogdan; NICULA, Dan. Automatic Conversion of Matlab/Simulink Models to HDL Models. Disponível em: < Acesso em: 19 ago [5] KARRIS, Steven T. Introduction to Stateflow with Applications. Califórnia, USA. Orchard Publications, [6] MIROTZNIK, Mark S.. Translating Matlab programs into C code. IEEE Spectrum, New York, USA, v. 33, n., p.63-64, [7] DA SILVA, Alexandre César Rodrigues. Contribuição à Minimização e Simulação de Circuitos Lógicos f.. Dissertação (Mestrado em Engenharia Elétrica) Faculdade de Engenharia Elétrica e de Computação, Universidade Estadual de Campinas, Campinas/SP, [8] KEOGH, D. B. The State Diagram of HDB3. IEEE Transactions on Communications. Vol. Com. 32, Nº 11, November, 1984, p [9] SILVA, Alexandre César Rodrigues da; ALMEIDA, Tiago da Silva. SF2TAB+VHDL: UM AMBIENTE DE TRADUÇÃO DE MÁQUINAS DE ESTADOS FINITOS PARA REALIZAÇÃO DE SÍNTESE LÓGICA. In: DINCON'09, 2009, Bauru. Anais... Bauru: UNESP - Bauru, v. 8. p