Pipeline issues. Pipeline hazard: RaW. Pipeline hazard: RaW. Calcolatori Elettronici e Sistemi Operativi. Hazards. Data hazard.
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1 Calcolatori Elettronici e Sistemi Operativi Pipeline issues Hazards Pipeline issues Data hazard Control hazard Structural hazard Pipeline hazard: RaW Pipeline hazard: RaW : add R,R,R : add R,R,R instr - instr - instr - 5 instr - 6 instr - 7 D+OF RAW hazard: add stalls : add R,R,R : add R,R,R instr - instr - instr - 5 instr - 6 instr - 7 D+OF E WB NOP NOP R R R R 5 R R R R 5
2 Pipeline hazard: RaW Pipeline hazard: RaW : add R,R,R : add R,R,R instr - instr - instr - 5 instr - 6 instr - 7 D+OF E WB NOP NOP D+OF E WB D+OF E D+OF : add R,R,R : add R,R,R instr - instr - instr - 5 instr - 6 instr - 7 D+OF E WB NOP NOP D+OF E WB D+OF E WB D+OF E WB R R R R R R R R Pipeline hazard: RaW Pipeline hazard: RaW : add R,R,R : add R,R,R instr - instr - instr - 5 instr - 6 instr - 7 D+OF E D+OF : data forwarding : add R,R,R : add R,R,R instr - instr - instr - 5 instr - 6 instr - 7 D+OF E D+OF WB E D+OF R R R R 5 R R R R 5
3 Data forwarding Pipeline hazard: WaR ID OF E ME WB : add R,R<<,R : mov R, D+OF E E E OF E D+OF E WB write-after-read WB DF : add R,R<<,R D+OF E E E OF E WB : mov R, D+OF E NOP NOP WB Pipeline hazard: latency () Pipeline hazard: latency () : ld R, M[R5] : add R,R,R instr - instr - D+OF E NOP data hazard : ld R, M[R5] : add R,R,R instr - instr - D+OF E E NOP D+OF NOP data forwarding
4 Pipeline hazard: latency () Pipeline hazard: latency () : ld R, M[R5] : add R,R,R D+OF E E WB NOP D+OF E WB NOP D+OF E WB NOP D+OF E WB : ld R, M[R5] : add R,R,R instr - instr - D+OF E E D+OF NOP D+OF structural hazard Pipeline hazard: latency () Pipeline hazard: control : ld R, M[R5] : add R,R,R D+OF E E WB D+OF NOP E WB D+OF NOP E WB D+OF NOP E WB : jnz 6 :nop D+OF NOP control hazard
5 Pipeline hazard: control Pipeline hazard: control : jnz 6 : instr - D+OF E WB NOP NOP NOP branch information available : jnz 6 : instr - D+OF E WB NOP NOP NOP D+OF E WB D+OF E WB Pipeline issues Register renaming Hazards stall different instruction times or out of order execution DIVF F6, F, F8 WaR Static register renaming Compiler Data hazard (RaR, RaW, WaR, WaW) data forwarding register renaming Control hazard branch prediction static dynamic conditional execution speculative execution Structural hazard pseudocode R = R-R if (R<) R= using branches SUB R, R, R ; R <- R-R BPL LABEL ; result is negative? MOV R, ; R <- LABEL:... using conditional execution SUB R, R, R ; R <- R-R MOVMI R, ; R <- if result is negative SUBF F8, F, F WaW ADDF F6, F, F8 rename registers DIVF S, F, F8 SUBF T, F, F RaW (data forwarding) ADDF F6, F, T must take into account: branches subroutines Dynamic register renaming Reservation Station Tomasulo's algorithm IBM 6/9 FP unit
6 Branch prediction Branch prediction Static delay slots to fill (programmer/compiler) [MIPS] branch is predicted as not-taken prediction bit Dynamic history prediction pseudocode R = R = R-R if (R<) R= static not-taken prediction using branches MOV R, ; R <- SUB R, R, R ; R <- R-R JnN LABEL ; result is negative? NOP always executed MOV R, ; R <- LABEL:... Static delay slots to fill (programmer/compiler) [MIPS] branch is predicted as not-taken prediction bit Dynamic history prediction pseudocode R = R = R-R if (R<) R= static not-taken prediction using branches SUB R, R, R ; R <- R-R JnN LABEL ; result is negative? MOV R, ; R <- always executed MOV R, ; R <- LABEL:... Branch prediction Branch Target Buffer Branch prediction Branch Target Buffer STAT STAT DEST TAG ID N N /T /T T /N /N T T T N N T,T N,T T,N N,N P T { TAG STAT DEST Miss always predict as not taken (do not insert in BTB if correctly predicted) always predict as taken (insert in BTB) taken if DEST <
7 Branch prediction Branch Target Buffer Conditional execution - Speculative execution TAG ID { TAG STAT DEST TAG STAT DEST Conditional execution instruction is fetched but executed if a condition is true ARM ADDEQ R, R, R Speculative execution n-ways both jump branches are executed wrong results are discarded Multiple exec units E E ID OF E ME WB ID OF E ME WB E n E n Many (even heterogeneous) execution units Mitigate structural hazards Slow instructions cause stalls even with no hazards addf F, F,F 5 cycles mov R, R cycle
8 In-order execution Reservation Shift Register In order start, in order end Reorder buffer FU Rd V FU: Functional Unit used Rd: Destination Register V: Valid : Program Counter In order start, out of order end, in order write back History buffer In order start, out of order end and write back Instruction that requires k cycles is inserted in row k All position before k are marked as used At each cycle, data in are shifted to up ( row) In-order execution: in order start, in order end Reservation Shift Register Reservation Shift Register FU Rd V FU: Functional Unit used Rd: Destination Register V: Valid : Program Counter FU Rd V FU: Functional Unit used Rd: Destination Register V: Valid : Program Counter : mul R, R, R cycles : mov R, cycle 8: addf F, F, F cycles FU mul Rd R V : mul R, R, R cycles : mov R, cycle 8: addf F, F, F cycles FU mul Rd R V
9 Reservation Shift Register Reservation Shift Register FU Rd V FU: Functional Unit used Rd: Destination Register V: Valid : Program Counter FU Rd V FU: Functional Unit used Rd: Destination Register V: Valid : Program Counter : mul R, R, R cycles : mov R, cycle 8: addf F, F, F cycles FU mov Rd R V : mul R, R, R cycles : mov R, cycle 8: addf F, F, F cycles FU Rd V addf F 8 ReOrder Buffer ReOrder Buffer FU V ptr FU V addf ptr F ptr: pointer to entry head = tail = Instruction that requires k cycles is inserted in row k of An entry in is filled (not entirely) is a circular buffer At each cycle, data in are shifted to up ( row) When an instruction exits from, result is written in When an instruction exits from, result is written in destination : addf F, F, F cycles : mov R, cycle 8: mul R, R, R cycles In-order execution: in order start, out of order end, in order write back
10 ReOrder Buffer ReOrder Buffer FU V ptr add addf F R FU V addf ptr F R head = tail = head = tail = : addf F, F, F cycles : mov R, cycle 8: mul R, R, R cycles : addf F, F, F cycles : mov R, cycle 8: mul R, R, R cycles ReOrder Buffer ReOrder Buffer FU V addf mul ptr F R R 8 FU V mul ptr F. R R 8 head = tail = head = tail = : addf F, F, F cycles : mov R, cycle 8: mul R, R, R cycles : addf F, F, F cycles : mov R, cycle 8: mul R, R, R cycles Instruction in () can exit write. in F
11 ReOrder Buffer ReOrder Buffer FU V mul ptr R R 8 FU V ptr mul R R 5 8 head = tail = head = tail = : addf F, F, F cycles : mov R, cycle 8: mul R, R, R cycles : addf F, F, F cycles : mov R, cycle 8: mul R, R, R cycles ReOrder Buffer History Buffer FU V mul ptr R R 5 8 FU V HBptr Rd Rd C OLD OLD: Old destination value head = tail = allows faster WB HB : addf F, F, F cycles : mov R, cycle 8: mul R, R, R cycles Instruction in () can exit write to R Instruction that requires k cycles is inserted in row k of An entry in is filled (the current value of destination is saved in OLD) HB is a circular buffer At each cycle, data in are shifted to up ( row) When an instruction exits from, result is written in destination Until an instruction is in HB, old data can be restored if needed (interrupt, exception, branch) In-order execution: in order start, out of order end and write back
12 Store buffer Superscalar architecture Processing core Store buffer Writes: to a small and fast buffer data is forwarded to memory Reads: first search in the store buffer Memory latency hidden for writes More complex mem. interface control Memory interface ID ID OF E ME OF E WB E n More instructions in a single cycle Higher hazards probability ME WB Superscalar HW multithreading Very Long Instruction Word Parallelism is explicit in instructions Control simplified Compiler complex High bandwitdh CPU/Memory Instructions in pipeline are from different tasks Independent execution flows hazard probability is reduced more register files (or register mapping) needed op Rd Rsa Rsb op Rd Rsa Rsb op n Rd n Rsa n Rsb n FU FU FU n
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