Internal architecture of 8086

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1 Case Study: Intel Processors Internal architecture of 8086 Slide 1

2 Case Study: Intel Processors FEATURES OF 8086 It is a 16-bit μp has a 20 bit address bus can access up to 220 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14, 16 -bit registers. Word size 16 bit. It has multiplexed address and data bus AD0- AD15 and A16 A19. Slide 2

3 Case Study: Intel Processors FEATURES OF is designed to operate in two modes, Minimum and Maximum. It can prefetch up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package Address ranges from 00000H to FFFFFH. Slide 3

4 BIU EU Case Study: Intel Processors Slide 4

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6 Internal Architecture of has two blocks -- Bus Interface Unit(BIU) and Execution unit(eu). Dividing the work between these two units speed up processing. The BIU sends out addresses, fetches instruction from memory, reads data from ports and memory, and writes data to ports and memory. The BIU handles all transfer of data and addresses on the buses for the execution unit. The execution unit of 8086 tells the BIU where to fetch instruction or data from, decode instructions and executes instructions. Case Study: Intel Processors Slide 6

7 THE BUS INTERFACE UNIT(BIU) BIU Contains 4-byte instruction Queue (Q) The segment registers (CS, DS, ES, SS). The instruction Pointer (IP). The Address summing block( ) The function of BIU is that its fetches instructions, read data from memory or I/O ports and writers data to memory of I/O ports an buffers them into the queue. While the execution units decode or executes an instruction that does not involve uses of the bus, the BIU fetches up to 6-byte instruction byte for preceding instruction. The BIU stores this pre-fetched instruction byte in FIFO register called queue. Fetching the next instruction while executing the current instruction is referred as the instruction pipeline. The BIU has a dedicated Adder; the main function of the adder is to produce 20 bit physical address. Case Study: Intel Processors Slide 7

8 BUS INTERFACE UNIT(BIU) The bus control logic of the BIU generates all bus control signals such as read and writes for memory I/O ports. BIU sends out 20-bit addresses, so it can address any of 2 20 bytes in memory. Four segment registers in the BIU are used to hold the upper 16-bits of the starting addresses of four memory segments that the 8086 is working with at particular time. The four segment registers are the Code segment (CS), Stack segment (SS), Extra Segment (ES) and Data Segment (DS). In short the Bus Interface unit is responsible for performing all following external bus operations. It sends the address of the memory or I/O. It fetches instruction from memory. It read data from port/memory. It writes data into port/memory. It supports instruction queuing. It provides the address relocation facility. Case Study: Intel Processors Slide 8

9 Instruction Queue To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory. All six bytes are then held in first in first out 6 byte register called instruction queue. Then all bytes have to be given to EU one by one. This pre fetching operation of BIU may be in parallel with execution operation of EU, which improves the speed execution of the instruction. Case Study: Intel Processors Slide 9

10 Segment Register In 8086 processor has 4 segments registers Code Segment register (CS), Data Segment register(ds), Extra Segment register(es) and Stack Segment (SS)register. All are16 bit registers. Each of the Segment registers store the upper 16 bit address of the starting address of the corresponding segments. Case Study: Intel Processors Slide 10

11 Memory Segments of 8086 Case Study: Intel Processors Slide 11

12 Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment of the memory, where the executable program is stored. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data Segment by an offset address or the content of other register that holds the offset address. Stack Segment (SS): SS defined the area of memory used for the stack. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold the destination data. Case Study: Intel Processors Slide 12

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16 Segmented Memory The memory in an 8086 based system is organized as segmented memory. The CPU 8086 is able to address 1Mbyte of memory. The Complete physically available memory may be divided into a number of logical segments. The 4 segments are Code, Data, Extra and Stack segments. A Segment is a 64kbyte block of memory. The16 bit contents of the segment registers in the BIU actually Point to the starting location of a particular segment. Segments may be overlapped or non-overlapped Case Study: Intel Processors Slide 16

17 Advantages of Segmented memory Scheme Allows the memory capacity to be 1Mb although the actual addresses to be handled are of 16 bit size. Allows the placing of code, data and stack portions of the same program in different parts(segments)of the memory, for data and code protection. Permits a program and/or its data to be put into different areas of memory each time program is executed, i.e. provision for relocation may be done. Case Study: Intel Processors Slide 17

18 Instruction Pointer (IP) and the address Summing Block The IP register hold the 16 bit offset address or the offset, of the next code byte within the Code segment. An offset is the distance (in terms of address) from the beginning of a segment to a particular instruction or variable. The IP always references the Code segment register (CS). The physical address of the next instruction is formed by combining the CS and IP. To form a 20bit address of the next instruction, the 16 bit address of the IP is added (by the address summing block) to the address contained in the CS, which has been shifted four bits to the left. The following examples shows the CS:IP scheme of address formation Case Study: Intel Processors Slide 18

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20 Registers in 8086 Case Study: Intel Processors Slide 20

21 EXCECUTION UNIT Case Study: Intel Processors Slide 21

22 EXECUTION UNIT(EU) The execution unit includes the ALU, eight 16-bit general purpose register, a 16-bit flag register and a control unit. EU contains control circuitry which directs internal operations. A decoder in the EU translates instructions fetched from memory into a series of actions which the EU carries out. The EU has a 16-bit arithmetic logic unit which can add, subtract, AND, OR, increment, decrement, complement, Binary numbers. Case Study: Intel Processors Slide 22

23 EXECUTION UNIT(EU) The EU contains eight 16-bit general purpose registers- AX, BX, CX, DX, SP, BP, SI and DI. Among these registers AX, BX, CX, DX can be further into two 8-bit registers AH&AL, BH&BL, CH&CL and DH&DL. The general purpose registers can be used to store 16-bit data during program execution. A 16-bit flag register in the EU contains nine active flags. Six of the nine flags are used to indicate some condition produced by an instruction. The three remaining flags in the flag registers are used to control certain operations of the processors. or Case Study: Intel Processors Slide 23

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25 Case Study: Intel Processors EXCECUTION UNIT-GENERAL PURPOSE REGISTERS Slide 25

26 EXCECUTION UNIT-General Purpose Registers Normally used for storing temporary results Each of the registers is 16 bits wide (AX, BX, CX, DX) Can be accessed as either 16 or 8 bits AX, AH, AL Case Study: Intel Processors Slide 26

27 EXCECUTION UNIT-General Purpose Registers Register------Purpose AX Word multiply, word divide, word I /O AL Byte multiply, byte divide, byte I/O, decimal arithmetic AH Byte multiply, byte divide BX Store address information CX String operation, loops CL Variable shift and rotate DX Word multiply, word divide, indirect I/O Case Study: Intel Processors Slide 27

28 EU--Pointer and Index Registers(SP,BP,SI,DI) used to keep offset addresses. Used in various forms of memory addressing. In the case of SP and BP the default reference to form a physical address is the Stack Segment(SS-will be discussed under the BIU) Case Study: Intel Processors Slide 28

29 Pointer And Index Registers The index registers (SI & Di) and the BX generally default to the Data segment register(ds). SP: Stack pointer Used with SS to access the stack segment BP: Base Pointer Primarily used to access data on the stack Can be used to access data in other segments Case Study: Intel Processors Slide 29

30 Pointer And Index Registers SI: Source Index register It performs to point to memory locations in the data segment. by incrementing the contents of SI consecutive memory locations can be accessed. is required for some string operations. When string operations are performed, the SI register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations. Case Study: Intel Processors Slide 30

31 Case Study: Intel Processors Pointer And Index Registers DI: Destination Index register DI is used to point to memory locations. is also required for some string operations. When string operations are performed, the DI register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations. The SI and the DI registers may also be used to access data stored in arrays. Slide 31

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33 EXCECUTION UNIT-Flag register Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. In 8086 The EU contains a 16 bit flag register. 9 of the 16 are active flags and remaining 7 are undefined has 9 flags and they are divided into two categories: Conditional Flags Control Flags Case Study: Intel Processors Slide 33

34 EXCECUTION UNIT-Flag register U U U U OF DF IF TF SF ZF U AF U PF U CF Overflow Direction Interrupt Trap sign Zero Auxiliary Parity Carry Case Study: Intel Processors Slide 34

35 Conditional Flags Conditional flags represent result of last arithmetic or logical instruction executed. Conditional flags are as follows: Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic. Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 D3) to upper nibble (i.e. D4 D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally by the processor to perform Binary to BCD conversion. Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8- bits of the result contains even number of 1 s, the Parity Flag is set and for odd number of 1 s, the Parity Flag is reset. Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset. Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set. Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the capacity of machine. Case Study: Intel Processors Slide 35

36 Control Flags Control flags are set or reset deliberately to control the operations of the execution unit. Control flags are as follows: Trap Flag (TP): It is used for single step control. It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode. Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit and can be cleared by executing CLI instruction. Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address. When it is reset, the string bytes are accessed from lower memory address to higher memory address. Case Study: Intel Processors Slide 36

37 EXCECUTION UNIT-Flag register Flag Purpose Carry (CF) Holds the carry after addition or the borrow after subtraction.also indicates some error conditions, as dictated by some programs and procedures. Parity (PF) PF=0;odd parity,pf=1;even parity. Auxiliary (AF) Holds the carry (half carry) after addition or borrow after subtraction between bit positions 3 and 4 of the result (for example, in BCD addition or subtraction.) Zero (ZF) Shows the result of the arithmetic or logic operation. Z=1;result is zero. Z=0; The result is not 0. Sign (SF) Holds the sign of the result after an arithmetic/logic instruction execution. S=1;negative,S=0;positive. Case Study: Intel Processors Slide 37

38 Flag Purpose Trap (TF) A control flag. Enables the trapping through an on-chip debugging feature. Interrupt (IF) A control flag. Controls the operation of the INTR (interrupt request) I=0;INTRpindisabled. I=1;INTRpinenabled. Direction (DF) A control flag. It selects either the increment or decrement mode for DI and/or SI registers during the string instructions. Overflow (OF) Overflow occurs when signed numbers are added or subtracted. An overflow indicates the result has exceeded the capacity of the machine. Case Study: Intel Processors Slide 38

39 Six of the flags are status indicators reflecting properties of the last arithmetic or logical instruction. For example, if register AL = 7Fh and the instruction ADD AL,1 is executed then the following happen AL = 80h CF = 0; there is no carry out of bit 7 PF = 0; 80h has an odd number of ones AF = 1; there is a carry out of bit 3 into bit 4 ZF = 0; the result is not zero SF = 1; bit seven is one OF = 1; the sign bit has changed Can be used to transfer program control to a new memory location; for example: ADD AL,1 JNZ 0100h

40 LOGICAL AND PHYSICAL ADDRESS In Intel literature concerning the 8086, there are three types of addresses mentioned frequently: the physical address, the offset address and the logical address. The physical/real address is the 20-bit address that is actually put on the address pins of the 8086 microprocessors and decoded by the memory interfacing circuitry. This address can have a range of 00000H to FFFFFH for the 8086 and real-mode 286, 386, and 486 CPUs. This is an actual physical location in RAM or ROM within the 1 megabyte memory range. The offset address is a location with a 64K-byte segment range. There, an offset address can range from 0000H to FFFFH. The logical address consists of a segment value and an offset address. Case Study: Intel Processors Slide 40

41 Difference between the physical and the logical address The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on the address bus lines. The logical address is an offset from location 0 of a given segment. When two segments overlap it is certainly possible for two different logical addresses to map to the same physical address. This can have disastrous results when the data begins to overwrite the subroutine stack area, or vice versa. For this reason you must be very careful when segments are allowed to overlap. You should also be careful when writing addresses on paper to do so clearly. To specify the logical address XXXX in the stack segment, use the convention SS:XXXX, which is equal to [SS] * 16 + XXXX. Case Study: Intel Processors Slide 41

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43 Calculate physical address from logical address Case Study: Intel Processors Slide 43

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Intel 8086 MICROPROCESSOR ARCHITECTURE

Intel 8086 MICROPROCESSOR ARCHITECTURE 1 Features It is a 16-bit μp. 8086 has a 20 bit address bus can access up to 2 20 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14, 16