ECE 545 Lecture 6. Behavioral Modeling of Sequential-Circuit Building Blocks. Behavioral Design Style: Registers & Counters.

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1 ECE 55 Lecture 6 Behavioral Modeling of Sequential-Circuit Building Blocks Required reading P. Chu, RTL Hardware esign using VHL Chapter 5.1, VHL Process Chapter 8, Sequential Circuit esign: Principle George Mason University 2 VHL esign Styles VHL esign Styles Behavioral esign Style: Registers & Counters ECE 8 FPGA and ASIC esign with VHL 3 dataflow Concurrent statements synthesizable structural behavioral Components and Sequential statements interconnects Registers Shift registers Counters State machines and more if you are careful Processes in VHL Processes escribe Sequential Behavior Processes in VHL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit ot every process can be synthesized Use Processes with Caution in the Code to Be Synthesized Use Processes Freely in Testbenches Anatomy of a Process OPTIOAL [label:] PROCESS [(sensitivity list)] [declaration part] statement part E PROCESS [label]; 5 6 1

2 PROCESS with a SESITIVITY LIST Component Equivalent of a Process List of signals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process fires. Every time the process fires, it will run in its entirety. WAIT statements are OT ALLOWE in a processes with SESITIVITY LIST. label: process (sensitivity list) declaration part begin statement part end process; priority: PROCESS (clk) IF w(3) = '1' THE y <= "11" ; ELSIF w(2) = '1' THE y <= "10" ; ELSIF w(1) = c THE y <= a and b; ELSE z <= "00" ; clk w a b c priority All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c All signals which appear in the sensitivity list are inputs e.g. clk ote that not all inputs need to be included in the sensitivity list y z 7 8 latch Registers Graphical symbol Truth table Timing diagram (t+1) (t) 0 1 t 1 t 2 t 3 t Time ECE 8 FPGA and ASIC esign with VHL 9 10 flip-flop latch Graphical symbol Truth table Clk (t+1) (t) 1 (t) Timing diagram t 1 t 2 t 3 t Time ETITY latch IS PORT (, : I ST_LOGIC ; : OUT ST_LOGIC) ; E latch ; ARCHITECTURE behavioral OF latch IS PROCESS (, ) IF = '1' THE <= ; E behavioral;

3 flip-flop flip-flop ETITY flipflop IS PORT (, : I ST_LOGIC ; : OUT ST_LOGIC) ; E flipflop ; ETITY flipflop IS PORT (, : I ST_LOGIC ; : OUT ST_LOGIC) ; E flipflop ; ARCHITECTURE behavioral OF flipflop IS PROCESS ( ) IF 'EVET A = '1' THE <= ; E behavioral ; ARCHITECTURE behavioral2 OF flipflop IS PROCESS ( ) IF rising_edge() THE <= ; E behavioral2; 13 1 flip-flop flip-flop with asynchronous reset ETITY flipflop IS PORT (, : I ST_LOGIC ; : OUT ST_LOGIC) ; E flipflop ; ETITY flipflop_ar IS PORT (, Resetn, : I ST_LOGIC ; : OUT ST_LOGIC) ; E flipflop_ar ; Resetn ARCHITECTURE behavioral3 OF flipflop IS PROCESS WAIT UTIL rising_edge() ; <= ; E behavioral3 ; ARCHITECTURE behavioral OF flipflop_ar IS PROCESS ( Resetn, ) IF Resetn = '0' THE <= '0' ; ELSIF rising_edge() THE <= ; E behavioral ; flip-flop with synchronous reset ETITY flipflop_sr IS PORT (, Resetn, : I ST_LOGIC ; : OUT ST_LOGIC) ; E flipflop_sr ; ARCHITECTURE behavioral OF flipflop_sr IS PROCESS() IF rising_edge() THE IF Resetn = '0' THE <= '0' ; ELSE <= ; E IF; E behavioral ; Resetn Asychronous vs. Synchronous In the IF loop, asynchronous items are Before the rising_edge() statement In the IF loop, synchronous items are After the rising_edge() statement

4 8-bit register with asynchronous reset -bit register with asynchronous reset ETITY reg8 IS PORT ( : I ST_LOGIC_VECTOR(7 OWTO 0) ; Resetn, : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR(7 OWTO 0) ) ; E reg8 ; ARCHITECTURE behavioral OF reg8 IS PROCESS ( Resetn, ) IF Resetn = '0' THE <= " " ; ELSIF rising_edge() THE <= ; E behavioral ;` 8 Resetn 8 reg8 19 ETITY regn IS GEERIC ( : ITEGER := 16 ) ; PORT ( : I ST_LOGIC_VECTOR(-1 OWTO 0) ; Resetn, : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR(-1 OWTO 0) ) ; E regn ; ARCHITECTURE behavioral OF regn IS PROCESS ( Resetn, ) IF Resetn = '0' THE <= (OTHERS => '0') ; ELSIF rising_edge() THE <= ; E behavioral ; Resetn regn 20 A word on generics Generics are typically integer values In this class, the entity inputs and outputs should be std_logic or std_logic_vector But the generics can be integer Generics are given a default value GEERIC ( : ITEGER := 16 ) ; This value can be overwritten when entity is instantiated as a component Generics are very useful when instantiating an often-used component eed a 32-bit register in one place, and 16-bit register in another Can use the same generic code, just configure them differently Use of OTHERS OTHERS stand for any index value that has not been previously mentioned. <= can be written as <= (0 => 1, OTHERS => 0 ) <= can be written as <= (7 => 1, 0 => 1, OTHERS => 0 ) or <= (7 0 => 1, OTHERS => 0 ) <= can be written as <= ( downto 1=> 1, OTHERS => 0 ) bit register with enable ETITY regne IS GEERIC ( : ITEGER := 8 ) ; PORT ( : I ST_LOGIC_VECTOR(-1 OWTO 0) ;, : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR(-1 OWTO 0) ) ; E regne ; ARCHITECTURE behavioral OF regne IS PROCESS () IF rising_edge() THE IF = '1' THE <= ; E IF; E behavioral ; regn Counters 23 ECE 8 FPGA and ASIC esign with VHL 2

5 2-bit up-counter with synchronous reset USE ieee.std_logic_unsigned.all ; ETITY upcount IS PORT ( Clear, : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR(1 OWTO 0) ) ; E upcount ; ARCHITECTURE behavioral OF upcount IS SIGAL Count : std_logic_vector(1 OWTO 0); upcount: PROCESS ( ) IF rising_edge() THE IF Clear = '1' THE Count <= "00" ; ELSE Count <= Count + 1 ; E IF; E PROCESS; <= Count; E behavioral; Clear upcount 2 -bit up-counter with asynchronous reset (1) USE ieee.std_logic_unsigned.all ; ETITY upcount_ar IS PORT (, Resetn, : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR (3 OWTO 0)) ; E upcount_ar ; Resetn upcount bit up-counter with asynchronous reset (2) ARCHITECTURE behavioral OF upcount _ar IS SIGAL Count : ST_LOGIC_VECTOR (3 OWTO 0) ; PROCESS (, Resetn ) IF Resetn = '0' THE Count <= "0000" ; ELSIF rising_edge() THE IF = '1' THE Count <= Count + 1 ; <= Count ; E behavioral ; Resetn upcount Shift Registers 27 ECE 8 FPGA and ASIC esign with VHL 28 Shift register Shift Register With Parallel (3) (2) (1) (0) (3) (2) (1) (0) (3) (2) (1) (0)

6 -bit shift register with parallel load (1) -bit shift register with parallel load (2) ETITY shift IS PORT ( : I ST_LOGIC_VECTOR(3 OWTO 0) ; : I ST_LOGIC ; : I ST_LOGIC ; : I ST_LOGIC ; : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR(3 OWTO 0) ) ; E shift ; shift ARCHITECTURE behavioral OF shift IS SIGAL t : ST_LOGIC_VECTOR(3 OWTO 0); PROCESS () IF rising_edge() THE IF = '1' THE t <= ; ELSIF = 1 THE t(0) <= t(1) ; t(1) <= t(2); t(2) <= t(3) ; t(3) <= ; <= t; E behavioral ; shift bit shift register with parallel load (2) -bit shift register with parallel load (1) ARCHITECTURE behavioral OF shift IS SIGAL t : ST_LOGIC_VECTOR(3 OWTO 0); PROCESS () IF rising_edge() THE IF = '1' THE t <= ; ELSIF = 1 THE t <= & t(3 downto 1); <= t; E behavioral ; shift ETITY shiftn IS GEERIC ( : ITEGER := 8 ) ; PORT ( : I ST_LOGIC_VECTOR(-1 OWTO 0) ; : I ST_LOGIC ; : I ST_LOGIC ; : I ST_LOGIC ; : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR(-1 OWTO 0) ) ; E shiftn ; shiftn bit shift register with parallel load (2) -bit shift register with parallel load (2) ARCHITECTURE behavioral OF shiftn IS SIGAL t: ST_LOGIC_VECTOR(-1 OWTO 0); PROCESS () IF rising_edge() THE IF = '1' THE t <= ; ELSIF = 1 THE Genbits: FOR i I 0 TO -2 LOOP t(i) <= t(i+1) ; E LOOP ; t(-1) <= ; E IF; <= t; E behavior al; shiftn ARCHITECTURE behavioral OF shiftn IS SIGAL t: ST_LOGIC_VECTOR(-1 OWTO 0); PROCESS () IF rising_edge() THE IF = '1' THE t <= ; ELSIF = 1 THE t <= & t(-1 downto 1); E IF; <= t; E behavior al; shiftn 35 ECE 8 FPGA and ASIC esign with VHL 36 6

7 -bit register with enable Generic Component Instantiation ETITY regn IS GEERIC ( : ITEGER := 8 ) ; PORT ( : I ST_LOGIC_VECTOR(-1 OWTO 0) ;, : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR(-1 OWTO 0) ) ; E regn ; ARCHITECTURE Behavior OF regn IS PROCESS () IF ('EVET A = '1' ) THE IF = '1' THE <= ; E IF; E Behavior ; regn ECE 8 FPGA and ASIC esign with VHL Circuit built of medium scale components s(0) Structural description example (1) r(0) r(1) r(2) r(3) r() r(5) s(1) p(0) p(1) p(2) p(3) w 0 w 1 w 2 w 3 priority y 1 y 0 z q(1) q(0) ena En w y 1 3 z(3) t(3) w y 0 2 z(2) t(2) y 1 z(1) t(1) En y 0 z(0) t(0) dec2to regne Clk ETITY priority_resolver IS PORT (r : I ST_LOGIC_VECTOR(5 OWTO 0) ; s : I ST_LOGIC_VECTOR(1 OWTO 0) ; clk : I ST_LOGIC; en : I ST_LOGIC; t : OUT ST_LOGIC_VECTOR(3 OWTO 0) ) ; E priority_resolver; ARCHITECTURE structural OF priority_resolver IS SIGAL p : ST_LOGIC_VECTOR (3 OWTO 0) ; SIGAL q : ST_LOGIC_VECTOR (1 OWTO 0) ; SIGAL z : ST_LOGIC_VECTOR (3 OWTO 0) ; SIGAL ena : ST_LOGIC ; 39 0 Structural description example (2) VHL-87 COMPOET mux2to1 PORT (w0, w1, s : I ST_LOGIC ; f : OUT ST_LOGIC ) ; E COMPOET ; COMPOET priority PORT (w : I ST_LOGIC_VECTOR(3 OWTO 0) ; y : OUT ST_LOGIC_VECTOR(1 OWTO 0) ; z : OUT ST_LOGIC ) ; E COMPOET ; Structural description example (3) VHL-87 COMPOET regn GEERIC ( : ITEGER := 8 ) ; PORT ( : I ST_LOGIC_VECTOR(-1 OWTO 0) ;, : I ST_LOGIC ; : OUT ST_LOGIC_VECTOR(-1 OWTO 0) ) ; E COMPOET ; COMPOET dec2to PORT (w : I ST_LOGIC_VECTOR(1 OWTO 0) ; En : I ST_LOGIC ; y : OUT ST_LOGIC_VECTOR(3 OWTO 0) ) ; E COMPOET ; 1 2 7

8 Structural description example () VHL-87 u1: mux2to1 PORT MAP (w0 => r(0), w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(2) <= r(3); u2: mux2to1 PORT MAP (w0 => r(), w1 => r(5), s => s(1), f => p(3)); Structural description example (5) VHL-87 u5: regn GEERIC MAP ( => ) E structural; PORT MAP ( => z, => En, => Clk, => t ); u3: priority PORT MAP (w => p, y => q, z => ena); u: dec2to PORT MAP (w => q, En => ena, y => z); 3 Structural description example (2) VHL-93 u1: work.mux2to1(dataflow) PORT MAP (w0 => r(0), w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(2) <= r(3); u2: work.mux2to1(dataflow) PORT MAP (w0 => r(), w1 => r(5), s => s(1), f => p(3)); u3: work.priority(dataflow) PORT MAP (w => p, y => q, z => ena); Structural description example (5) VHL-87 u: work.dec2to (dataflow) PORT MAP (w => q, En => ena, y => z); u5: work.regne(behavioral) E structural; GEERIC MAP ( => ) PORT MAP ( => z, => En, => Clk, => t ); 5 6 Instruction ROM example (1) LIBRARY ieee; USE ieee.std_logic_116.all; USE ieee.numeric_std.all; ETITY instruction_rom IS ROM GEERIC ( w : ITEGER := 16; n : ITEGER := 8; m : ITEGER := 3); PORT ( Instr_addr : I ST_LOGIC_VECTOR(m-1 OWTO 0); Instr : out ST_LOGIC_VECTOR(w-1 OWTO 0) ); E instruction_rom; ECE 8 FPGA and ASIC esign with VHL 7 8 8

9 Instruction ROM example (2) ARCHITECTURE ins_rom OF instruction_rom IS SIGAL temp: ITEGER RAGE 0 TO n-1; TYPE vector_array IS ARRAY (0 to n-1) OF ST_LOGIC_VECTOR(w-1 OWTO 0); COSTAT memory : vector_array := ( X"0000", X"59", X"A870", X"7853", X"650", X"62F", X"F72", X"F58"); Mixing esign Styles Inside of an Architecture temp <= to_integer(unsigned(instr_addr)); Instr <= memory(temp); E instruction_rom; 9 ECE 8 FPGA and ASIC esign with VHL 50 VHL esign Styles dataflow Concurrent statements synthesizable VHL esign Styles structural behavioral Components and Sequential statements interconnects Registers Shift registers Counters State machines Mixed Style Modeling architecture ARCHITECTURE_AME of ETITY_AME is Here you can declare signals, constants, functions, procedures Component declarations begin Concurrent statements: Concurrent simple signal assignment Conditional signal assignment Selected signal assignment Generate statement Component instantiation statement Process statement inside process you can use only sequential statements end ARCHITECTURE_AME; Concurrent Statements For Beginners Sequential Logic Synthesis for Beginners Use processes with very simple structure only to describe - registers - shift registers - counters - state machines. Use examples discussed in class as a template. Create generic entities for registers, shift registers, and counters, and instantiate the corresponding components in a higher level circuit using GEERIC MAP PORT MAP. Supplement sequential components with combinational logic described using concurrent statements. ECE 8 FPGA and ASIC esign with VHL

10 For Intermmediates Sequential Logic Synthesis for Intermediates 1. Use Processes with IF and CASE statements only. o not use LOOPS or VARIABLES. 2. Sensitivity list of the PROCESS should include only signals that can by themsleves change the outputs of the sequential circuit (typically, clock and asynchronous set or reset) 3. o not use PROCESSes without sensitivity list (they can be synthesizable, but make simulation inefficient) ECE 8 FPGA and ASIC esign with VHL For Intermmediates (2) Given a single signal, the assignments to this signal should only be made within a single process block in order to avoid possible conflicts in assigning values to this signal. Process 1: PROCESS (a, b) y <= a A b; E PROCESS; on-synthesizable VHL Process 2: PROCESS (a, b) y <= a OR b; E PROCESS; 57 George Mason University elays elays are not synthesizable Statements, such as wait for 5 ns a <= b after 10 ns will not produce the required delay, and should not be used in the code intended for synthesis. Initializations eclarations of signals (and variables) with initialized values, such as SIGAL a : ST_LOGIC := 0 ; cannot be synthesized, and thus should be avoided. If present, they will be ignored by the synthesis tools. Use set and reset signals instead

11 ual-edge triggered register/counter (1) In FPGAs register/counter can change only at either rising (default) or falling edge of the clock. ual-edge triggered clock is not synthesizable correctly, using either of the descriptions provided below. ual-edge triggered register/counter (2) PROCESS (clk) IF (clk EVET A clk= 1 ) THE counter <= counter + 1; ELSIF (clk EVET A clk= 0 ) THE counter <= counter + 1; E IF; E PROCESS; ual-edge triggered register/counter (3) PROCESS (clk) IF (clk EVET) THE counter <= counter + 1; E IF; E PROCESS; PROCESS (clk) counter <= counter + 1; E PROCESS; 63 11