ECOM 4311 Digital Systems Design
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1 ECOM 4311 Digital Systems Design Eng. Monther Abusultan Computer Engineering Dept. Islamic University of Gaza Page 1
2 Agenda 1. Counters Page 2
3 Counters - special name of any clocked sequential circuit whose state diagram is a circle - there are many types of counters, each suited for particular applications Page 3
4 Binary Counter - state machine that produces a straight binary count - for n-flip-flops, 2 n counts can be produced - the Next State Logic "F" is a combinational SOP/POS circuit - the speed will be limited by the Setup/Hold and Combinational Delay of "F" - this gives the maximum number of counts for n-flip flops Page 4
5 Toggle Flop - a D-Flip-Flop can produce a "Divide-by-2" effect by feeding back Qn to D - this topology is also called a "Toggle Flop" Page 5
6 Ripple Counter - Cascaded Toggle Flops can be used to form rippled counter - this is slower than a straight binary counter due to waiting for the "ripple" - this is good for low power, low speed applications Page 6
7 Shift Register - a chain of D-Flip-Flops that pass data to one another - this is good for "pipelining" - also good for Serial-to-Parallel conversion - for n-flip-flops, the data is present at the final state after n clocks Page 7
8 Ring Counter - feeding the output of a shift register back to the input creates a "ring counter" - also called a "One Hot" - The first flip-flop needs to set to 1, while the others reset to 0 - for n flip-flops, there will be n counts Page 8
9 Johnson Counter - feeding the inverted output of a shift register back to the input creates a "Johnson Counter" - this gives more states with the same reduced gate count - all flip-flops can reset to 0 - for n flip-flops, there will be 2n counts Page 9
10 Counters in VHDL - strong type casting in VHDL can make modeling counters difficult (at first glance) - the reason for this is that the STANDARD and STD_LOGIC Packages do not define "+", "-", or inequality operators for BIT_VECTOR or STD_LOGIC_VECTOR types Page 10
11 Counters in VHDL - there are a couple ways that we get around this 1) Use the STD_LOGIC_UNSIGNED Package - this package defines "+" and "-" functions for STD_LOGIC_VECTOR - we can use +1 just like normal - the vector will wrap as suspected ( ) - one catch is that we can't assign to a Port - we need to create an internal signal of STD_LOGIC_VECTOR for counting - we then assign to the Port at the end Page 11
12 Counters in VHDL using STD_LOGIC_UNSIGNED use IEEE.STD_LOGIC_UNSIGNED.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter; Page 12
13 Counters in VHDL using STD_LOGIC_UNSIGNED architecture counter_arch of counter is signal count_temp : std_logic_vector(3 downto 0); -- Notice internal signal begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= "0000"; elsif (Clock='1' and Clock'event) then if (Direction='0') then count_temp <= count_temp + '1'; else count_temp <= count_temp - '1'; end if; end if; end process; Count_Out <= count_temp; end counter_arch; -- assign to Port after the process Page 13
14 Counters in VHDL 2) Use integers for the counter and then convert back to STD_LOGIC_VECTOR - STD_LOGIC_ARITH is a Package that defines a conversion function - the function is: conv_std_logic_vector (ARG, SIZE) - functions are defined for ARG = integer, unsigned, signed, STD_ULOGIC - SIZE is the number of bits in the vector to convert to, given as an integer - we need to keep track of the RANGE and Counter Overflow Page 14
15 Counters in VHDL using STD_LOGIC_ARITH use IEEE.STD_LOGIC_ARITH.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter; Page 15
16 Counters in VHDL using STD_LOGIC_ARITH architecture counter_arch of counter is signal count_temp : integer range 0 to 15; begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= 0; elsif (Clock='1' and Clock'event) then if (count_temp = 15) then count_temp <= 0; else count_temp <= count_temp + 1; end if; end if; end process; -- integer assignment doesn't requires quotes -- we manually check for overflow Count_Out <= conv_std_logic_vector (count_temp, 4); end counter_arch; Page 16
17 Counters in VHDL 3) Use UNSIGNED data types #'s - STD_LOGIC_ARITH also defines "+", "-", and equality for UNSIGNED types - UNSIGNED is a Data type defined in STD_LOGIC_ARITH - UNSIGNED is an array of STD_LOGIC - An UNSIGNED type is the equivalent to a STD_LOGIC_VECTOR type - the equality operators assume it is unsigned (as opposed to 2's comp SIGNED) Pro's and Cons - using integers allows a higher level of abstraction and more functionality can be included - easier to write a non-synthesizable code or code that produces unwanted logic - both are synthesizable when written correctly Page 17
18 Ring Counters in VHDL - to mimic the shift register behavior, we need access to the signal value before and after clock'event - consider the following concurrent signal assignments: architecture. begin Q0 <= Q3; Q1 <= Q0; Q2 <= Q1; Q3 <= Q2; end architecture - since they are executed concurrently, it is equivalent to Q0=Q1=Q2=Q3, or a simple wire Page 18
19 Ring Counters in VHDL - since a process doesn't assign the signal values until it suspends, we can use this to model "before and after" behavior of a clock event. process (Clock, Reset) begin if (Reset = '0') then Q0<='1'; Q1<='0'; Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2; end if; end process - notice that the signals DO NOT appear in the sensitivity list. If they did the process would continually execute and not be synthesized as a flip-flop structure Page 19
20 Johnson Counters in VHDL process (Clock, Reset) begin if (Reset = '0') then Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then end if; end process Q0<=not Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2; Page 20
ECOM4311 Digital Systems Design
ECOM 4311 Digital Systems Design Eng. Monther Abusultan Computer Engineering Dept. Islamic University of Gaza Page 1 Agenda 1. VHDL : Data Types Cont d 2. VHDL : Operators 3. VHDL : Signal Assignments
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