TOPIC : Verilog Synthesis examples. Module 4.3 : Verilog synthesis

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1 TOPIC : Verilog Synthesis examples Module 4.3 : Verilog synthesis

2 Example : 4-bit magnitude comptarator Discuss synthesis of a 4-bit magnitude comparator to understand each step in the synthesis flow. Steps of the synthesis flow such as translation, logic optimization, and technology mapping are not visible to us as a designer.

3 Design specification A magnitude comparator checks if one number is greater than, equal to, or less than another number. Design a 4-bit magnitude comparator IC chip that has the following specifications: Name of the design is magnitude-comparator Inputs A and B are 4-bit inputs. No x or z values will appear on A and B inputs Output A_gt_B is true if A is greater than B Output A-lt-B is true if A is less than B Output A-eq-B is true if A is equal to B Magnitude comparator circuit must be as fast as possible. Area can be compromised for speed.

4 RTL description The RTL description that describes the magnitude comparator is below :

5 Technology library We decide to use the 65nm CMOS process say xyz -50 used by xyz Inc. to make our IC chip. ABC Inc. supplies a technology library for synthesis. Functionality, timing, area, and power dissipation information of each library cell are specified in the technology library. The library contains the following library cells. The library cells are defined in a format understood by the synthesis tool.

6 Design constraints : According to the specification, the design should be as fast as possible for the target technology, xyz-50. There are no area constraints. Thus, there is only one design constraint : Optimize the final circuit for fastest timing. Logic synthesis : The RTL description of the magnitude comparator is read by the logic synthesis tool. The design constraints and technology library for xyz-50 are provided to be logic synthesis tool. The logic synthesis tool performs the necessary optimizations and produces a gate-level description optimized for xyz-50 technology. Final, Optimized, Gate-Level Description : The logic synthesis tool produces a final, gate-level description.

7 The schematic for the gate-level circuit Gate level schematic or Netlist for Magnitude Comprator

8 Netlist for magnitude comparator

9 IC Fabrication The gate-level netlist is verified for functionality and timing and then submitted to XYZ Inc. XYZ Inc. does the chip layout, checks that the postlayout circuit meets timing requirements, and then fabricates the IC chip, using xyz-50 technology.

10 Verification of Gate-Level Netlist Functional Verification : Identical stimulus is run with the original RTL and synthesized gatelevel descriptions(netlist) of the design. The output is compared to find any mismatches. Timing verification : The gate-level netlist is typically checked for timing by use of timing simulation or by a static timing verifier. If any timing constraints are violated, the designer must either redesign part of the RTL or make tradeoffs in design constraints for logic synthesis. The entire flow is iterated until timing requirements are met.

Modeling Tips for Logic Synthesis Verilog Coding Style Use meaningful names for signals and variables Avoid mixing positive and negative edge-triggered flip-flops. Use basic building blocks vs.

11 Modeling Tips for Logic Synthesis Verilog Coding Style Use meaningful names for signals and variables Avoid mixing positive and negative edge-triggered flip-flops. Use basic building blocks vs. Use continuous assign statements : Instantiation of basic building blocks creates symmetric designs, and the logic synthesis tool is able to optimize smaller modules more effectively. Instantiate multiplexers vs. Use if-else or case statements : By using multiplexers, because if-else or case statements can cause undesired random logic to be generated by the synthesis tool.

12 Use parentheses to optimize logic structure //translates to 3 adders in series out = a + b + c + d ; //translates to 2 adders in parallel with one final adder to sum results out = (a + b) + (c + d) ; *, /, %, Multiply, divide, and modulo operators are very expensive to implement in terms of logic and area.

13 Be careful with multiple assignments to the same variable : Multiple assignments to the same variable can cause undesired logic to be generated. The previous assignment might be ignored, and only the last assignment would be used. //two assignments to the same variable (posedge clk) if(load1) q <= al; (posedge clk) if(load2) q <= a2; The synthesis tool infers two flip-flops with the outputs anded together to produce the q output. The designer needs to be careful about such situations.

14 Define if-else or case statements explicitly Branches for all possible conditions must be specified in the if-else or case statements. Otherwise, level-sensitive latches may be inferred instead of multiplexers.

CAD for VLSI Design - I. Lecture 21 V. Kamakoti and Shankar Balachandran

CAD for VLSI Design - I. Lecture 21 V. Kamakoti and Shankar Balachandran CAD for VLSI Design - I Lecture 21 V. Kamakoti and Shankar Balachandran Overview of this Lecture Understanding the process of Logic synthesis Logic Synthesis of HDL constructs Logic Synthesis What is this?