Architecture. Harvard Architecture. PIC18 Review. Architecture, Instruction Set, and Assembly Language Programming

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Register File (RISC) Sigle Cycle Istructios Sigle Word Istructios Log Word Istructios (Harvard) Reduced Istructio Set Orthogoal Istructio Set Harvard Architecture Vo Neuma

1 PIC18 Review Architecture, Istructio Set, ad Assembly Laguage Programmig 25 Microchip Techology Icorporated. All Rights Reserved. Slide 1 Architecture The high performace of the PICmicro microcotroller ca be attributed to the followig architectural features: Harvard Architecture Istructio Pipeliig Large Register File (RISC) Sigle Cycle Istructios Sigle Word Istructios Log Word Istructios (Harvard) Reduced Istructio Set Orthogoal Istructio Set Harvard Architecture Vo Neuma Architecture: es istructios ad data from a sigle memory space Limits operatig badwidth Harvard Architecture: Uses two separate memory spaces for program istructios ad data Improved operatig badwidth Allows for differet bus widths 1

2 Istructio Pipeliig Istructio fetch is overlaped with executio of previously fetched istructio Istructio Cycles 1 MAIN movlw x5 T T1 T2 T3 T4 T5 T6 T7 Time to execute ormal istructio Time to execute call istructio icludes pipelie flush Flush Flush Istructio Pipeliig Pre-ed Istructio Executig Istructio movlw x5 - Istructio Cycles 1 MAIN movlw x5 T Istructio Pipeliig Pre-ed Istructio movwf REG1 Executig Istructio movlw x5 Istructio Cycles 1 MAIN movlw x5 T T1 2

3 Istructio Pipeliig Pre-ed Istructio rcall SUB1 Executig Istructio movwf REG1 Istructio Cycles 1 MAIN movlw x5 T T1 T2 Time to execute ormal istructio Istructio Pipeliig Pre-ed Istructio addwf REG2 Executig Istructio rcall SUB1 Istructio Cycles 1 MAIN movlw x5 T T1 T2 T3 Istructio Pipeliig Pre-ed Istructio movf PORTB,w Executig Istructio rcall SUB1 Istructio Cycles 1 MAIN movlw x5 T T1 T2 T3 T4 Flush Time to execute call istructio icludes pipelie flush 3

4 Istructio Pipeliig Pre-ed Istructio Executig Istructio movf PORTB,w Istructio Cycles 1 MAIN movlw x5 T T1 T2 T3 T4 T5 Flush Istructio Pipeliig Pre-ed Istructio Executig Istructio Istructio Cycles 1 MAIN movlw x5 T T1 T2 T3 T4 T5 Flush T6 Istructio Pipeliig Pre-ed Istructio addwf REG2 Executig Istructio Istructio Cycles 1 MAIN movlw x5 T T1 T2 T3 T4 T5 Flush T6 T7 Flush 4

5 Log Word Istructio 8-bit Program Memory 8-bit Istructio o typical 8-bit MCU Example: Freescale Load Accumulator A : 2 Program Memory Locatios 2 Istructio Cycles to Execute ldaa # Limits Badwidth Icreases Memory Size Requiremets 16-bit Program Memory 16-bit Istructio o PIC18 8-bit MCU Example: Move Literal to Worig Register 1 Program Memory Locatio 1 Istructio Cycle to Execute movlw Separate busses allow differet widths 2 x 16 is roughly equivalet to 4 x 8 w f ALU d w f WREG Register File Cocept Data Bus Data Memory (Register File) Decoded Istructio Opcode from Program Memory: Arithmetic/Logic d a Address Address of Secod Fuctio to be Performed Result Source Operad Destiatio 7h 8h 9h Ah Bh Ch Dh Eh Fh 1h Register File Cocept: All of data memory is part of the register file, so ay locatio i data memory may be operated o directly All peripherals are mapped ito data memory as a series of registers Orthogoal Istructio Set: ALL istructios ca operate o ANY data memory locatio The Log Word Istructio format allows a directly addressable register file PIC18 Istructio Set Overview addwf addwfc adwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsz icf icfsz ifsz iorwf movf movff movwf mulwf f s,f d Byte Orieted Operatios Add WREG ad f Add WREG ad Carry bit to f AND WREG with f Clear f Complemet f Compare f with WREG, sip = Compare f with WREG, sip > Compare f with WREG, sip < Decremet f Decremet f, Sip if if Decremet f, Sip if if Not Icremet f Icremet f, Sip if if Icremet f, Sip if if Not Iclusive OR WREG with f Move f Move f s (src) to f d (dst) Move WREG to f Multiply WREG with f egf rlcf rlcf rrcf rrcf setf subfwb subwf subwfb swapf tstfsz xorwf bcf bsf btfsc btfss btg f,b,a f,b,a f,b,a f,b,a f,b,a Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap ibbles i f Test f, sip if if Exclusive OR WREG with f Bit Orieted Operatios Bit Clear f Bit Set f Bit Test f, Sip if if Clear Bit Test f, Sip if if Set Bit Toggle f 5

6 PIC18 Istructio Set Overview bc b bc b bov bz bov bra bz call,s Cotrol Operatios Brach if if Carry Brach if if Negative Brach if if Not Carry Brach if if Not Negative Brach if if Not Overflow Brach if if Not Zero Brach if if Overflow Brach Always Brach if if Zero Call subroutie addlw adlw iorlw lfsr movlb movlw mullw retlw sublw f, Literal Operatios Add literal ad WREG AND literal with WREG Iclusive OR literal with WREG Move 12-bit literal to FSR Move literal to BSR<3:> Move literal to WREG Multiply literal with WREG Retur with literal i WREG Subtract WREG from literal xorlw Exclusive OR literal with WREG clrwdt Clear Watchdog Timer daw goto Decimal Adjust WREG Go to address Data Memory Program Memory Operatios op No Operatio tblrd* Table Read pop Pop top of stac (TOS) tblrd*+ Table Read with post-icremet push rcall Push top of stac (TOS) Relative Call tblrd*- tblrd+* Table Read with post-decremet Table Read with pre-icremet reset retfie s s Software device RESET Retur from iterrupt Retur from subroutie tblwt* tblwt*+ tblwt*- Table Write Table Write with post-icremet Table Write with post-decremet sleep Go ito stadby mode tblwt+* Table Write with pre-icremet Istructio Set Overview Byte Orieted Operatios Opcode a f f f f f f f f OR Opcode d a f f f f f f f f File Register Address Destiatio (W or F) Access Ba ADDWF x25, W, A File Register Address Destiatio Use Access Ba (Optioal) Istructio Set Overview Bit Orieted Operatios 15 Opcode 11 b b 9 b 8 a 7 f f f f f f f f File Register Address Bit Positio (-7) BSF x25, 3, A File Register Address Access Ba Bit Positio (Optioal) 6

7 Istructio Set Overview Literal ad Cotrol Operatios Opcode OR Opcode Literal Value MOVLW x25 Literal Value Istructio Set Overview Byte to Byte Move Operatios (2 Words) Opcode Opcode 11 f s f s f s f d f d f d f d f d Source Register Address f s f s f s f s f s f s f s f s f s f d f d f d f d f d f d f d Destiatio Register Address MOV x125, x14 Source Address Destiatio Address Istructio Set Overview Call ad Goto Operatios (2 Words) Opcode Opcode CALL x1125 Subroutie Address 7

8 PIC18 Visual Iterpreter ADDLW 3 Execute, Reset Hex Dec Bi Literal Data from Istructio Word d w f ALU w f W Register Data Bus Register File Address h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh STATUS 2 1 Z DC C PIC18 Addressig Modes Data Memory Access: Mode Example Sytax Direct clrf <reg>, <dst> Idirect clrf INDF, <dst> Auto Pre-Icremet movff PREINC, <dst> Idirect Auto Post- movff POSTINC, <dst> Icremet Idirect Auto Post- movff POSTDEC, <dst> Decremet Idirect Idex Idirect movff PLUSW, <dst> Immediate (Literal) movlw <cost> Data Memory Orgaizatio Data Memory up to 4 bytes Divided ito 256 byte bas Half of ba ad half of ba 15 form a virtual ba that is accessible o matter which ba is selected h 7Fh 8h h 1h 1h 2h 2h Dh Dh Eh Eh Fh F7Fh F8h Fh Access RAM Ba GPR Ba 1 GPR Ba 2 GPR Ba 13 GPR Ba 14 GPR Ba 15 GPR Access SFR PIC16F8F2/4 Register File Map Access Ba Access RAM Access SFR 256 Bytes h 7Fh 8h h 8

9 a Bit from Istructio Register Direct Addressig BSR 4-bits from BSR Register f Operad 8-bits Ecoded i Istructio 12-bit Effective Address (Use this whe codig) 1 xefe Ba Ba1 Ba2 Ba13 Ba14 Ba D 7E 7F FC FD FE Register Direct Addressig: Example BSR 4-bits from BSR Register f Operad 8-bits Ecoded i Istructio Effective Address = MyReg equ x12 MyReg Access RAM Ba Ba 1 Ba 2 12h movlw b 1111 movwf TRISB, a bsf PORTB,, a movlb x1 movlw xaa movwf MyReg PORTB LATB TRISB BSR WREG Ba 15 Access SFR F81h F8Ah F93h FEh FE8h Register Idirect Addressig 4-bits from FSRH 8-bits from FSRL FSRH FSRL 12-bit Effective Address xd No baig RAM is fully liear whe usig idirect addressig FSRH:FSRL ca be loaded with a sigle istructio: lfsr Full 12-bit icremet / decremet of poiter possible with pre- or postmodificatio modes Three FSR register pairs available: FSR, 1 & 2 Data Memory h 1h 2h 3h 4h 5h Ah Bh Ch Dh Eh Fh Register File Address Bus 9

10 Register Idirect Addressig Several additioal idirect addressig modes have bee added to the PIC18: Idirect - o chage i FSR Auto Post-decremet FSR (FSR--) Auto Post-icremet FSR (FSR++) Auto Pre-icremet FSR (++FSR) Idex Idirect (Address = FSR + W) Register Idirect Addressig These modes are ivoed by usig special o-physical registers: Idirect - o chage: INDF Auto Post-decremet: POSTDEC Auto Post-icremet: POSTINC Auto Pre-icremet: PREINC Idex Idirect / Offset: PLUSW Register Idirect Addressig: Example 1 Example: Clear all RAM locatios from 12h to 17Fh LOOP FSRH FSR Decimal Value: FSRL lfsr,x12 clrf POSTINC btfss FSRL,7 goto LOOP <ext istructio> Register File 11Fh 12h 121h 122h 17Dh 17Eh 17Fh 18h FSRH FSRL PLUSW PREINC FE9h FEAh FEBh FECh POSTDEC FEDh POSTINC FEEh INDF FEFh 1

11 Register Idirect Addressig: Example 2 Example: Spaghetti Addressig (Do t try this at home!) FSRH FSR Decimal Value: 129 lfsr,x128 clrf INDF bsf POSTDEC, clrf POSTINC clrf PREINC movlw x2 clrf PLUSW FSRL Register File 1 126h 127h 128h 129h 12Ah 12Bh 12Ch 12Dh 12Eh FSRH FSRL PLUSW PREINC FE9h FEAh FEBh FECh POSTDEC FEDh POSTINC FEEh INDF FEFh PIC18 Addressig Modes Program Memory Access: Mode Absolute Relative Table Read / Write Table Read / Write Post Icremet Table Read / Write Post Decremet Table Read / Write Pre Icremet Example Sytax goto <addr> bra <addr> tblrd* tblwt* tblrd*+ tblrd*- tblrd+* tblwt*+ tblwt*- tblwt+* Program Memory Orgaizatio Reset Vector h Oe, cotiguous liear program memory space up to 2MB (1MWord) High Priority Iterrupt Vector Low Priority Iterrupt Vector 8h 18h 21-bit Program Couter O-chip Program Memory Stac Level 1 Stac Level 2 7Eh 8h Stac Level 3 31 Level Stac Stac Level 31 Uimplemeted Program Memory (Read as ) 1Eh 11

12 Program Memory is Byte Addressable Low byte has eve address, high byte has odd address Addresses of istructios are always eve Word Address High Byte Address 16-bit Program Memory Low Byte Address x1 x x3 x2 x5 x4 x7 x6 x9 x8 xb xa xd xc xf xe Program Couter 21 PCU PCH Program Couter PCL 21-bit PC ca access up to 2 21 = 2MB (1MWord) 22 d bit used to access cofiguratio memory at program time or via table reads & writes Cotais address of NEXT istructio (pipeliig) Lower byte accessible i data memory as PCL Upper bytes idirectly accessible via PCLATH/PCLATU Bit of PC is always except whe readig or writig program memory via table read/write mechaism PC Absolute Addressig CALL ad GOTO Istructios: = Program Memory Address Bit of the address is implied sice it is always zero due to the byte addressability of program memory PC Absolute Addressig (Program Memory) Jump to aother program memory locatio out of PC sequece Call a subroutie Used by the CALL ad GOTO istructios Full address is specified as part of the two word istructio Used whe performig Computed Goto operatio Address to jump to is calculated by the program Computed address is writte directly ito the Program Couter 12

13 PC Relative Addressig: Brach Istructios Used by sigle word brach istructios: BC / BNC: BN / BNN: BOV / BNOV: BZ / BNZ: BRA: RCALL: is the relative offset from the PC Example: BC CarryBitSet Used to perform a computed GOTO by directly modifyig the program couter PC Relative Addressig To write to PC: Write upper byte to PCLATU Write high byte to PCLATH Write low byte to PCL PCLATU WREG 1 PC_OSET = 12 8-bit Data Bus PCLATH 12 PCU PCH PCL movlw UPPER x1125 movwf PCLATU movlw HIGH x1125 movwf PCLATH movff PC_OSET, PCL PC Relative Addressig: Computed GOTO Computed GOTO used to idex ito a jump table org x218 JTS movlw UPPER JUMP_TABLE movwf PCLATU movlw HIGH JUMP_TABLE movwf PCLATH movlw x4 mulwf x219 movf PRODL, w addwf PCL, f JUMP_TABLE goto DoUserIput goto DoUserIput1 goto DoUserIput2 goto DoUserIput3 goto DoUserIput4 USER_INPUT 2 PCLATU PCLATH 21 WREG 8 98 PCU PCH PCL Compute actual offset ito table. Each goto i table occupies 4 bytes: 2 bytes per word, 2 words per goto. 13

14 Top of Stac Registers TOSU 23 TOSH PIC18 Retur Address Stac TOSL 7 STKPTR Register STKOVF STKUNF SP4:SP - Evets that push PC+2 oto the stac: PUSH CALL RCALL Iterrupt Evets that pop the top of the stac: POP RETURN RETLW RETFIE Program Couter PCU:PCH:PCL 2 Stac Stac Level Stop PC Table Reads/Writes Allows access to two bytes of data per program memory locatio Table Read / Write Addressig Modes: No Chage tblrd * tblwt * Post Icremet tblrd *+ tblwt *+ Post Decremet tblrd *- tblwt *- Pre Icremet tblrd +* tblwt +* Accessig program memory is coceptually lie register idirect addressig (data memory) Table Reads/Writes Register Idirect Addressig (Retrieves data from RAM) Table Idirect Addressig (Retrieves data from Flash) Poiter Registers FSRH : FSRL (12-bits) FSR1H : FSR1L (12-bits) FSR2H : FSR2L (12-bits) TBLPTRU : TBLPTRH : TBLPTRL (22-bits) Example movf INDF, w tblrd* Read Data to WREG movf INDF1, w movf TABLAT, w No Poiter Modificatio movf INDF2, w Example movf POSTINC, w tblrd*+ Read Data to WREG movf POSTINC1, w movf TABLAT, w Post-Icremet Poiter movf POSTINC2, w Example movf POSTDEC, w tblrd*- Read Data to WREG movf POSTDEC1, w movf TABLAT, w Post-Decremet Poiter movf POSTDEC2, w Example movf PREINC, w tblrd+* Pre-Icremet Poiter movf PREINC1, w movf TABLAT, w Read Data to WREG movf PREINC2, w Table 1-1: Compariso betwee Register Idirect Addressig ad Table Read Operatios 14

15 Table Reads PIC18F Program Memory is Divided Ito: User Memory Up to 128B Iteral Up to 2MB Exteral User IDs 8 Modifiable Bytes Cofiguratio Memory Device Settigs, Code Protects, etc. Device IDs Part ad Revisio Sigature Program Couter ca oly access User Memory (PC is 21-bits wide) Table Poiter ca access all memory (TBLPTR is 22-bits wide) Program Memory Space User Flash Uimplemeted Memory User IDs Uimplemeted Memory Cofiguratio Uimplemeted Memory Device IDs x x1 x2 x27 x3 x3d x3e x3f Table Read Operatio TBLPTRU TBLPTRH TBLPTRL 9 Data Memory (RAM) Program Memory (Flash) x x1 x x1 x2 x3 x4 x5 xa 22-bit Address TABLAT 2C x3 x5 x7 x9 xb 8-bit Data x15 2C x2 x4 x6 x8 xa x14 xb x17 x16 xc x19 x18 xd x1b x1a xe x1d x1c xf x1f x1e High Byte (Odd Addr) Low Byte (Eve Addr) Table Read Example Sedig Characters to LCD How ASCII strig tables are stored i program memory: 71h 7h 15

16 M i c r TBLPTR 7 5 TABLAT 6F Table Read Example WREG 6F Program Memory D F movlw LOW MyStrigtable movwf TBLPTRL movlw HIGH MyStrigtable movwf TBLPTRH movlw UPPER MyStrigtable movwf TBLPTRU TableReadLoop tblrd*+ movf TABLAT,w btfsc STATUS,Z bra EdLoop call LCDPutChar goto TableReadLoop EdLoop org x7 MyStrigTable DW Microchip\ 16

Section 31. Instruction Set

31 HIGHLIGHTS Section 31. Instruction Set Instruction Set This section of the manual contains the following major topics: 31.1 Introduction... 31-2 31.2 Data Memory Map... 31-3 31.3 Instruction Formats...