Superscalar Processor

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1 Superscalar Processor Design Superscalar Architecture Virendra Singh Indian Institute of Science Bangalore Lecture 20 SE-273: Processor Design

2 Superscalar Pipelines IF ID RD ALU MEM WB Mar 3,

3 Superscalar Pipelines Dynamic Pipelines 1. Alleviate the limitations of pipelined implementation 2. Use diversified pipelines 3. Temporal machine parallelism Mar 3,

4 Superscalar Pipelines (Diversified) IF ID RD EX ALU Mem1 Mem2 FP1 FP2 FP3 BR WB Mar 3,

5 Superscalar Pipelines (Diversified) Diversified Pipelines Each pipeline can be customized for particular instruction type Each instruction type incurs only necessary latency Certainly less expensive than identical copies If all inter-instruction dependencies are resolved then there is no stall after instruction issue Require special consideration Number and Mix of functional units Mar 3,

6 Dynamic Pipelines Superscalar Pipelines (Dynamic Pipelines) Buffers are needed Multi-entry buffers Every entry is hardwired to one read port and one write port Complex multi-entry buffers Minimize stalls Mar 3,

7 Superscalar Pipelines (Interpipeline-Stage Buffers) Stage i Buffer (1) Stage i+1 Single entry Stage i Buffer (n) Stage i+1 Multi-entry Buffer Mar 3, 2010 SE-273@SERC 7

8 Superscalar Pipelines (Interpipeline-Stage Buffers) Stage i Buffer (>= n) Stage i+1 In-order Out-of-order Trailing instructions are allowed to bypass stalled instruction Out-of-order execution Mar 3, 2010 SE-273@SERC 8

9 Superscalar Architecture Instruction issue and machine parallelism In-order issue with in-order completion In-Order issue with Out-of-Order completion Out-of-Order issue without-of-order Completion Mar 3,

10 Superscalar Architecture Instruction issue and machine parallelism I1 require two cycles I3 and I4 conflicts for a functional unit I5 depends on the value produced by I4 I5 and I6 has conflicts for a functional unit Mar 3, 2010 SE-273@SERC 10

11 Superscalar Pipelines (Diversified) IF ID RD EX ALU Mem1 Mem2 FP1 FP2 FP3 BR WB Mar 3,

12 Superscalar Pipeline Stages Fetch Instruction Buffer In Program Order Out of Order In Program Order Decode Dispatch Execute Complete Retire Dispatch Buffer Issuing Buffer Completion Buffer Store Buffer Mar 3,

13 Super-scalar Architecture Fetch Instruction buffer Decode Dispatch buffer Dispatch Issue Reservation station Execute finish Complete Re-order/Completion buffer Store buffer Retire Mar 3,

14 Limitations of Scalar Pipelines Scalar upper bound on throughput IPC <= 1 or CPI >= 1 Solution:wide (superscalar) pipeline Inefficient unified pipeline Long latency for each instruction Solution: diversified, specialized pipelines Rigid pipeline stall policy One stalled instruction i stalls all newer instructionsi Solution: Out of order execution, distributed execution pipelines Mar 3, 2010 SE-273@SERC 14

15 Superscalar Architecture Instruction issue and machine parallelism In-order issue with in-order completion In-Order issue with Out-of-Order completion Out-of-Order issue without-of-order Completion Mar 3,

16 Super-scalar Architecture Mar 23,

17 Super-scalar Architecture Fetch Instruction buffer Decode Dispatch buffer Dispatch Issue Reservation station Execute finish Complete Re-order/Completion buffer Store buffer Retire Mar 23,

18 Impediments to High IPC I-cache Branch Predictor FETCH Instruction Buffer Instruction Flow DECODE Integer Floating-point Media Memory Register Data Flow Reorder Buffer (ROB) Store Queue EXECUTE COMMIT D-cache Memory Data Flow

19 Superscalar Pipeline Design Instruction Fetching Issues Instruction Decoding Issues Instruction Dispatching Issues Instruction Execution Issues Instruction Completion & Retiring Issues

20 Instruction Flow Objective: Fetch multiple instructions per cycle Challenges: Branches: control dependences Branch target misalignment Instruction cache misses Solutions Code alignment (static vs.dynamic) Prediction/speculation PC Instruction Memory 3 instructions fetched

21 Instruction Fetch Fetch s instructions from I-cache I-Cache must be wide enough that each row of the I-Cache array can store s instructions and that an entire row can be accessed Fetch width = Row width Assume access latency is 1 cycle Mar 23, 2009 SE-273@SERC 21

22 I-Cache Organization Address Address er R o w D e c o d TAG TAG TAG TAG Cache Line er Row Decod TAG TAG Cache Line 1 cache line = 1 physical row 1 cache line = 2 physical rows

23 Fetch Alignment PC XX00001 Row decoder Row width Fetch group

24 Instruction Fetch Impediments: 1. Instruction misalignment Solutions Static Compiler Needs information about the I-Cache org, indexing, row size Dynamic 2. Presence of control flow change Mar 23,

25 Instruction Fetch (Mis-alignment) D E C Tag Tag Tag Tag Fetch Group Row width Organization of wide I-Cache Mar 23, 2009 SE-273@SERC 25

26 Instruction Fetch 2 way set associative i I-Cache with a line size of 16 instructions (64 bytes) Each row of the I-Cache stores 4 associative sets 9two per set) of instructions Each line of I-cache spans four physical rows Physical I-cache array is actually composed of 4 independent sub-arrays One instruction can be accessed form one array Mar 23, 2009 SE-273@SERC 26

27 Instruction Fetch IFAR T T T Odd Directory set A0 A4 A8 B0 B4 B8 A1 A5 A9 B1 B5 B9 A2 A6 A10 B2 B6 B10 A3 A7 A11 B3 B7 B11 Odd Directory set Instruction Buffer Network Mar 23, 2009 SE-273@SERC 27

28 IFAR RIOS-I Fetch Hardware T logic T logic T logic Odd directory sets A&B A0 A4 A8 B0 B4 B A1 A5 A9 B1 B5 B A2 A6 A10 B2 B6 B A3 A7 A11 B3 B7 B11 Even directory sets A & B TLB hit and buffer control logic A12 B12 mux A13 B13 mux A14 B14 mux A15 B15 mux Instruction buffer network Interlock, dispatch, branch, execution logic D Instruction n D truction n 1 Inst D truction n 2 Inst D truction n 3 Inst

29 Issues in Decoding Primary Tasks Identify individual instructions (!) Determine instruction types Determine dependences between instructions Two important factors Instruction set architecture Pipeline width

30 Decode Stage Decodes instruction types Detect inter-instruction dependencies Complexity ISA Fetch width Large number of comparators Multi-ported RF Mar 23,

31 Pentium Pro Fetch/Decode Macroinstruction bytes from IFU Instruction buffer 16 bytes To next address calculation urom Decoder Decoder Decoder uops 1 uop 1 uop Branch address calculation uop queue (6)

32 Instruction Dispatch and Issue Parallel pipeline Centralized instruction fetch Centralized instruction decode Diversified pipeline Distributed instruction execution

33 Necessity of Instruction Dispatch Instruction fetching Instruction decoding Instruction dispatching FU 1 FU 2 FU 3 FU n Instruction execution

34 Centralized Reservation Station Dispatch Centralized reservation (issue) station (dispatch buffer) Execute Completion buffer

35 Distributed Reservation Station Dispatch Dispatch buffer Issue Distributed reservation stations Execute Finish Completion buffer Complete

36 Issues in Instruction Execution Current trends More parallelism bypassing very challenging Deeper pipelines More diversity Functional unit types Integer Floating point Load/store most difficult to make parallel Branch Specialized units (media) Very wide datapaths (256 bits/register or more)

37 Instruction Dispatching Diversified pipeline Different type instructions executed by different FU in different pipelines Distributed control Operands are fetched from RF Operands may not be available Reservation station Centralized Distributed Mar 23,

38 Instruction Dispatching Mar 23,

39 Instruction Issue Mar 23,

40 Instruction Issue Mar 23,

41 Issues in Completion/Retirement Out of order execution ALU instructions Load/store instructions In order completion/retirement Precise exceptions Memory coherence and consistency Solutions Reorder buffer Store buffer Loadqueue snooping (later)

42 Instruction Dispatching Mar 23,

43 Super-scalar Architecture Fetch Instruction buffer Decode Dispatch buffer Dispatch Issue Reservation station Execute finish Complete Re-order/Completion buffer Store buffer Retire Mar 23,

44 Thank You Mar 3,

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