Documentation. Implementation Xilinx ISE v10.1. Simulation

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1 DS317 September 19, 2008 Introduction The Xilinx LogiCORE IP Generator is a fully verified first-in first-out () memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all configurations and delivers maximum performance (up to 500 MHz) while utilizing minimum resources. Delivered through the Xilinx CORE Generator software, the structure can be customized by the user including the width, depth, status flags, memory type, and the write/read port aspect ratios. This document describes the features of the core, specifies the interfaces, and defines the input and output signals. For detailed information about designing with the core, see the Generator User Guide. (UG175). Features depths up to 4,194,304 words data widths from 1 to 1024 bits Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1) or common clock domains Selectable memory type (block, distributed, shift register, or built-in ) Synchronous or asynchronous reset option Hamming Error Correction Checking (ECC) for Virtex -5 FPGA built-in and block based First-word fall-through (FWFT) Full and empty status flags, and almost full and almost empty flags for indicating one-word-left Programmable full and empty status flags, set by user-defined constant(s) or dedicated input port(s) Configurable handshake signals Embedded register option for Virtex-5 FPGA block and built-in based Fully configurable using the Xilinx CORE Generator Supported FPGA Device Families Performance and Resources Used Documentation Design File Formats LogiCORE IP Facts Core Specifics Virtex-5, Virtex-4/XA, Virtex-II, Virtex-II Pro, Virtex-E, Virtex, Spartan -3A/3AN/3A DSP, Spartan-3E/XA, Spartan- 3/XA, Spartan-IIE, Spartan-II Provided with Core See Tables 9 and 11 User Guide Release Notes Migration Guide (1) VHDL, Verilog Instantiation Template VHDL, Verilog Design Tool Requirements Implementation Xilinx ISE v10.1 Simulation Supported Simulation Models Support Provided by Xilinx, Mentor ModelSim v6.3c Cadence IUS v6.1 Verilog Behavioral (2) VHDL Behavioral (2) Verilog Structural (3) VHDL Structural (3) 1. The Migration Guide provides instructions for converting legacy Asynchronous and Synchronous LogiCORE IP cores to Generator cores. 2. Behavioral models are not cycle accurate and do not model synchronization delay. See the simulation section of the Generator User Guide (UG175) for details. 3. Structural models should be used if cycle-accurate simulation is required Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. DS317 September 19,

2 Applications In digital designs, s are ubiquitous constructs required for data manipulation tasks such as clock domain crossing, low-latency memory buffering, and bus width conversion. Figure 1 highlights just one of many configurations that the Generator supports. In this example, the design has two independent clock domains and the width of the write data bus is four times wider than the read data bus. Using the Generator, the user is able to rapidly generate solutions such as this one, that is customized for their specific requirements and provides a solution fully optimized for Xilinx FPGAs. X-Ref Target - Figure 1 Core Clock 1 Domain Logic DATA IN 128 Bits Configuration: Clocks Aspect Ratio = 4:1 DATA OUT 32 Bits Clock 2 Domain Logic CLK 1 CLK 1 CLK 2 CLK 2 Figure 1: Generator Application Example Feature Overview Clock Implementation Operation The Generator enables s to be configured with either independent or common clock domains for write and read operations. The independent clock configuration of the Generator enables the user to implement unique clock domains on the write and read ports. The Generator handles the synchronization between clock domains, placing no requirements on phase and frequency. When data buffering in a single clock domain is required, the Generator can be used to generate a core optimized for that single clock. Virtex-5 FPGA Built-in Support The Generator supports the Virtex-5 FPGA built-in modules, enabling large s to be created by cascading the built-in s in both width and depth. The core expands the capabilities of the built-in s by utilizing the FPGA fabric to create optional status flags not implemented in the builtin macro. The built-in Error Correction Checking (ECC) feature in the built-in macro is also available to the user. Virtex-4 FPGA Built-in Support Support of the Virtex-4 FPGA built-in allows generation of a single primitive complete with fabric implemented flag patch, described in "Solution 1: Synchronous/Asynchronous Clock Work- Arounds," in the Virtex-4 FPGA User Guide (UG070). 2 DS317 September 19, 2008

3 First-Word Fall-Through (FWFT) The first-word fall-through (FWFT) feature provides the ability to look-ahead to the next word available from the without issuing a read operation. When data is available in the, the first word falls through the and appears automatically on the output bus (DOUT). FWFT is useful in applications that require low-latency access to data and to applications that require throttling based on the contents of the data that are read. FWFT support is included in s created with block, distributed, or Virtex-5 FPGA built-in s. Memory Types The Generator implements s built from block, distributed, shift registers, or the Virtex-5 FPGA built-in s. The core combines memory primitives in an optimal configuration based on the selected width and depth of the. The following table provides best-use recommendations for specific design requirements. The generator also creates single primitive Virtex-4 FPGA built-in s with the fabric implemented flag patch described in "Solution 1: Synchronous/Asynchronous Clock Work-Arounds," in the Virtex-4 FPGA User Guide. Table 1: Memory Configuration Benefits Clocks Common Clock Small Buffering Medium-Large Buffering High Performance Minimal Resources Virtex-5 FPGA with Built-in X X X X X Block X X X X X Shift Register X X X Distributed X X X X Non-Symmetric Aspect Ratio The core supports generating s with write and read ports of different widths, enabling automatic width conversion of the data width. Non-symmetric aspect ratios ranging from 1:8 to 8:1 are supported for the write and read port widths. This feature is available for s implemented with block that are configured to have independent write and read clocks. Embedded Registers in block and Macros (Virtex-4 and Virtex-5 Devices) In Virtex-4 and Virtex-5 FPGA block and macros, embedded output registers are available to increase performance and add a pipeline register to the macros. This feature can be leveraged to add one additional latency to the core (DOUT bus and VALID outputs) or implement the output registers for FWFT s. See Embedded Registers in block and Macros in the Generator User Guide, page 71, for more information. Error Correction Checking In the Virtex-5 FPGA architecture, the block and macros are equipped with built-in Error Correction Checking (ECC). This feature is available for both the common and independent clock block or built-in s. DS317 September 19,

4 Generator Configurations Table 2 defines the supported memory and clock configurations. Table 2: Configurations Clock Domain Memory Type Nonsymmetric Aspect Ratios First-word Fall-Through Common Clock: Block, Distributed, Shift Register This implementation category allows the user to select block, distributed, or shift register and supports a common clock for write and read data accesses. The feature set supported for this configuration includes status flags (full, almost full, empty, and almost empty) and programmable empty and full flags generated with user-defined thresholds. In addition, optional handshaking and error flags are supported (write acknowledge, overflow, valid, and underflow), and an optional data count provides the number of words in the. In addition, for the block and distributed implementations, the user has the option to select a synchronous or asynchronous reset for the core. For Virtex-5 FPGA designs, the block configuration also supports ECC. Common Clock: Virtex-5 or Virtex-4 FPGA Built-in ECC Support Embedded Register Support Common block X X X (1) Common Distributed X Common Shift Register Common Built-in (2) 1. Embedded register support is only available for Virtex-4 and Virtex-5 FPGA block -based s. 2. The built-in primitive is only available in the Virtex-5 and Virtex-4 architectures. 3. FWFT is only supported for built-in s in Virtex-5 devices. 4. Only available for Virtex-5 FPGA common clock built-in s. 5. For non-symmetric aspect ratios, use the block implementation (feature not supported in built-in primitive). This implementation category allows the user to select the built-in available in the Virtex-5 or Virtex-4 FPGA architecture and supports a common clock for write and read data accesses. The feature set supported for this configuration includes status flags (full and empty) and optional programmable full and empty flags with user-defined thresholds. In addition, optional handshaking and error flags are available (write acknowledge, overflow, valid, and underflow). The Virtex-5 FPGA built-in configuration also supports the built-in ECC feature. X (3) X X (4) block X X X X (1) Distributed X Built-in (2), (5) 4 DS317 September 19, 2008

5 Clocks: Block and Distributed This implementation category allows the user to select block or distributed and supports independent clock domains for write and read data accesses. Operations in the read domain are synchronous to the read clock and operations in the write domain are synchronous to the write clock. The feature set supported for this type of includes non-symmetric aspect ratios (different write and read port widths), status flags (full, almost full, empty, and almost empty), as well as programmable full and empty flags generated with user-defined thresholds. Optional read data count and write data count indicators provide the number of words in the relative to their respective clock domains. In addition, optional handshaking and error flags are available (write acknowledge, overflow, valid, and underflow). For Virtex-5 FPGA designs, the block configuration also supports ECC. Clocks: Virtex-5 or Virtex-4 FPGA Built-in This implementation category allows the user to select the built-in available in the Virtex-5 or Virtex-4 FPGA architecture. Operations in the read domain are synchronous to the read clock and operations in the write domain are synchronous to the write clock. The feature set supported for this configuration includes status flags (full and empty) and programmable full and empty flags generated with user-defined thresholds. In addition, optional handshaking and error flags are available (write acknowledge, overflow, valid, and underflow). The Virtex-5 FPGA built-in configuration also supports the built-in ECC feature. DS317 September 19,

6 Generator Features Table 3 summarizes the supported Generator features for each clock configuration and memory type. For detailed information, see the Generator User Guide. Table 3: Configurations Summary Clocks Common Clock Feature Block Distributed Built-in Block Distributed, Shift Register Built-in Non-symmetric Aspect Ratios (1) X Symmetric Aspect Ratios X X X X X X Almost Full X X X X Almost Empty X X X X Handshaking X X X X X X Data Count X X X X Programmable Empty/Full Thresholds X X X (2) X X X (2) First-Word Fall- Through X X X (3) X X (4) X (3) Synchronous Reset X X (5) Asynchronous Reset x (6) X (6) X X (6) X (6) X DOUT Reset Value X (7) X X (7) X ECC X (8) X (8) X (8) X (8) Embedded Register X (9) X (9) X (10) 1. For applications with a single clock that require non-symmetric ports, use the independent clock configuration and connect the write and read clocks to the same source. A dedicated solution for common clocks will be available in a future release. Contact your Xilinx representative for more details. 2. For built-in s, the range of Programmable Empty/Full threshold is limited to take advantage of the logic internal to the macro. 3. First-Word-Fall-Through is only supported for the Virtex-5 FPGA built-in s. 4. First-Word-Fall-Through is supported for distributed only. 5. Synchronous reset is available and optional for common clock configurations using distributed and block only. 6. Asynchronous reset is optional for all s built using distributed and block. 7. All architectures except Virtex, Virtex-E, Spartan-II, and Spartan-IIE FPGAs. 8. ECC is only supported for the Virtex-5 FPGA and block and built-in s. 9. Embedded register option is only supported in Virtex-4 and Virtex-5 FPGA block s. 10. Embedded register option is supported only in Virtex-5 FPGA common clock built-in s. See Embedded Registers in block and Macros (Virtex-4 and Virtex-5 Devices). 6 DS317 September 19, 2008

7 Interfaces The following sections define the interface signals. Figure 2 illustrates these signals (both standard and optional ports) for a core that supports independent write and read clocks. X-Ref Target - Figure 2 DIN[N:0] WR_EN DOUT[M:0] RD_EN WR_CLK RD_CLK FULL EMPTY ALMOST_FULL PROG_FULL Write Clock Domain Read Clock Domain ALMOST_EMPTY PROG_EMPTY WR_ACK VALID OVERFLOW UNDERFLOW PROG_FULL_THRESH_ASSERT PROG_EMPTY_THRESH_ASSERT PROG_FULL_THRESH_NEGATE PROG_EMPTY_THRESH_NEGATE PROG_FULL_THRESH PROG_EMPTY_THRESH RST Figure 2: with Clocks: Interface Signals Interface Signals: s With Clocks The RST signal, as defined Table 4, causes a reset of the entire core logic (both write and read clock domains. It is an asynchronous input synchronized internally in the core before use. The initial hardware reset should be generated by the user. See the Generator User Guide for specific information about reset requirements and behavior. Table 4: Reset Signal for s with Clocks Note: Optional ports represented in italics Name Direction Description RST Reset: An asynchronous reset signal that initializes all internal pointers and output registers. DS317 September 19,

8 Table 5 defines the write interface signals for s with independent clocks. The write interface signals are divided into required and optional signals and all signals are synchronous to the write clock (WR_CLK). Table 5: Write Interface Signals for s with Clocks WR_CLK Name Direction Description Required Write Clock: All signals on the write domain are synchronous to this clock. DIN[N:0] Data : The input data bus used when writing the. WR_EN FULL ALMOST_FULL PROG_FULL WR_DATA_COUNT [D:0] WR_ACK OVERFLOW Write Enable: If the is not full, asserting this signal causes data (on DIN) to be written to the. Full Flag: When asserted, this signal indicates that the is full. Write requests are ignored when the is full, initiating a write when the is full is non-destructive to the contents of the. Optional Almost Full: When asserted, this signal indicates that only one more write can be performed before the is full. Programmable Full: This signal is asserted when the number of words in the is greater than or equal to the assert threshold. It is deasserted when the number of words in the is less than the negate threshold. Write Data Count: This bus indicates the number of words written into the. The count is guaranteed to never underreport the number of words in the, to ensure the user never overflows the. The exception to this behavior is when a write operation occurs at the rising edge of WR_CLK, that write operation will only be reflected on WR_DATA_COUNT at the next rising clock edge. If D is less than log2( depth)-1, the bus is truncated by removing the least-significant bits. Write Acknowledge: This signal indicates that a write request (WR_EN) during the prior clock cycle succeeded. Overflow: This signal indicates that a write request (WR_EN) during the prior clock cycle was rejected, because the is full. Overflowing the is non-destructive to the contents of the. 8 DS317 September 19, 2008

9 Table 5: Write Interface Signals for s with Clocks (Continued) Name Direction Description PROG_FULL_THRESH PROG_FULL_THRESH_ASSERT PROG_FULL_THRESH_NEGATE Programmable Full Threshold: This signal is used to input the threshold value for the assertion and de-assertion of the programmable full (PROG_FULL) flag. The threshold can be dynamically set in-circuit during reset. The user can either choose to set the assert and negate threshold to the same value (using PROG_FULL_THRESH), or the user can control these values independently (using PROG_FULL_THRESH_ASSERT and PROG_FULL_THRESH_NEGATE). Programmable Full Threshold Assert: This signal is used to set the upper threshold value for the programmable full flag, which defines when the signal is asserted. The threshold can be dynamically set in-circuit during reset. Programmable Full Threshold Negate: This signal is used to set the lower threshold value for the programmable full flag, which defines when the signal is de-asserted. The threshold can be dynamically set in-circuit during reset. Table 6 defines the read interface signals of a with independent clocks. Read interface signals are divided into required signals and optional signals, and all signals are synchronous to the read clock (RD_CLK). Table 6: Read Interface Signals for s with Clocks Name Direction Description Required RD_CLK DOUT[M:0] RD_EN EMPTY ALMOST_EMPTY PROG_EMPTY Read Clock: All signals on the read domain are synchronous to this clock. Data : The output data bus is driven when reading the. Read Enable: If the is not empty, asserting this signal causes data to be read from the (output on DOUT). Empty Flag: When asserted, this signal indicates that the is empty. Read requests are ignored when the is empty, initiating a read while empty is non-destructive to the. Optional Almost Empty Flag: When asserted, this signal indicates that the is almost empty and one word remains in the. Programmable Empty: This signal is asserted when the number of words in the is less than or equal to the programmable threshold. It is de-asserted when the number of words in the exceeds the programmable threshold. DS317 September 19,

10 Table 6: Read Interface Signals for s with Clocks (Continued) Name Direction Description RD_DATA_COUNT [C:0] VALID UNDERFLOW PROG_EMPTY_THRESH PROG_EMPTY_THRESH_ASSERT PROG_EMPTY_THRESH_NEGATE SBITERR DBITERR Read Data Count: This bus indicates the number of words available for reading in the. The count is guaranteed to never over-report the number of words available for reading, to ensure that the user does not underflow the. The exception to this behavior is when the read operation occurs at the rising edge of RD_CLK, that read operation is only reflected on RD_DATA_COUNT at the next rising clock edge. If C is less than log2( depth)-1, the bus is truncated by removing the least-significant bits. Valid: This signal indicates that valid data is available on the output bus (DOUT). Underflow: Indicates that the read request (RD_EN) during the previous clock cycle was rejected because the is empty. Underflowing the is not destructive to the. Programmable Empty Threshold: This signal is used to input the threshold value for the assertion and de-assertion of the programmable empty (PROG_EMPTY) flag. The threshold can be dynamically set in-circuit during reset. The user can either choose to set the assert and negate threshold to the same value (using PROG_EMPTY_THRESH), or the user can control these values independently (using PROG_EMPTY_THRESH_ASSERT and PROG_EMPTY_THRESH_NEGATE). Programmable Empty Threshold Assert: This signal is used to set the lower threshold value for the programmable empty flag, which defines when the signal is asserted. The threshold can be dynamically set in-circuit during reset. Programmable Empty Threshold Negate: This signal is used to set the upper threshold value for the programmable empty flag, which defines when the signal is de-asserted. The threshold can be dynamically set in-circuit during reset. Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error on a Virtex-5 FPGA block or built-in macro. For detailed information, see "Chapter 4, Designing with the Core," in the Generator User Guide. Double Bit Error: Indicates that the ECC decoder detected a double-bit error on a Virtex-5 FPGA block or built-in macro and data in the core is corrupted. For detailed information, see "Chapter 4, Designing with the Core," in the Generator User Guide DS317 September 19, 2008

11 Interface Signals: s with Common Clock Table 7 defines the interface signals of a with a common write and read clock and is divided into standard and optional interface signals. All signals (except asynchronous reset) are synchronous to the common clock (CLK). Users have the option to select synchronous or asynchronous reset for the distributed or block implementation. See the Generator User Guide for specific information on reset requirements and behavior. Table 7: Interface Signals for s with a Common Clock Name Direction Description Required RST SRST CLK Reset: An asynchronous reset that initializes all internal pointers and output registers. Synchronous Reset: A synchronous reset that initializes all internal pointers and output registers. Clock: All signals on the write and read domains are synchronous to this clock. DIN[N:0] Data : The input data bus used when writing the. WR_EN FULL Write Enable: If the is not full, asserting this signal causes data (on DIN) to be written to the. Full Flag: When asserted, this signal indicates that the is full. Write requests are ignored when the is full, initiating a write when the is full is non-destructive to the contents of the. DOUT[M:0] Data : The output data bus driven when reading the. RD_EN EMPTY DATA_COUNT [C:0] ALMOST_FULL PROG_FULL WR_ACK OVERFLOW Read Enable: If the is not empty, asserting this signal causes data to be read from the (output on DOUT). Empty Flag: When asserted, this signal indicates that the is empty. Read requests are ignored when the is empty, initiating a read while empty is non-destructive to the. Optional Data Count: This bus indicates the number of words stored in the. If C is less than log2( depth)-1, the bus is truncated by removing the least-significant bits. Almost Full: When asserted, this signal indicates that only one more write can be performed before the is full. Programmable Full: This signal is asserted when the number of words in the is greater than or equal to the assert threshold. It is deasserted when the number of words in the is less than the negate threshold. Write Acknowledge: This signal indicates that a write request (WR_EN) during the prior clock cycle succeeded. Overflow: This signal indicates that a write request (WR_EN) during the prior clock cycle was rejected, because the is full. Overflowing the is non-destructive to the. DS317 September 19,

12 Table 7: Interface Signals for s with a Common Clock (Continued) Name Direction Description PROG_FULL_THRESH PROG_FULL_THRESH_ASSERT PROG_FULL_THRESH_NEGATE ALMOST_EMPTY PROG_EMPTY VALID UNDERFLOW PROG_EMPTY_THRESH PROG_EMPTY_THRESH_ASSERT Programmable Full Threshold: This signal is used to set the threshold value for the assertion and de-assertion of the programmable full (PROG_FULL) flag. The threshold can be dynamically set in-circuit during reset. The user can either choose to set the assert and negate threshold to the same value (using PROG_FULL_THRESH), or the user can control these values independently (using PROG_FULL_THRESH_ASSERT and PROG_FULL_THRESH_NEGATE). Programmable Full Threshold Assert: This signal is used to set the upper threshold value for the programmable full flag, which defines when the signal is asserted. The threshold can be dynamically set in-circuit during reset. Programmable Full Threshold Negate: This signal is used to set the lower threshold value for the programmable full flag, which defines when the signal is de-asserted. The threshold can be dynamically set in-circuit during reset. Almost Empty Flag: When asserted, this signal indicates that the is almost empty and one word remains in the. Programmable Empty: This signal is asserted after the number of words in the is less than or equal to the programmable threshold. It is de-asserted when the number of words in the exceeds the programmable threshold. Valid: This signal indicates that valid data is available on the output bus (DOUT). Underflow: Indicates that read request (RD_EN) during the previous clock cycle was rejected because the is empty. Underflowing the is non-destructive to the. Programmable Empty Threshold: This signal is used to set the threshold value for the assertion and de-assertion of the programmable empty (PROG_EMPTY) flag. The threshold can be dynamically set in-circuit during reset. The user can either choose to set the assert and negate threshold to the same value (using PROG_EMPTY_THRESH), or the user can control these values independently (using PROG_EMPTY_THRESH_ASSERT and PROG_EMPTY_THRESH_NEGATE). Programmable Empty Threshold Assert: This signal is used to set the lower threshold value for the programmable empty flag, which defines when the signal is asserted. The threshold can be dynamically set in-circuit during reset DS317 September 19, 2008

13 Table 7: Interface Signals for s with a Common Clock (Continued) Name Direction Description PROG_EMPTY_THRESH_NEGATE SBITERR DBITERR Programmable Empty Threshold Negate: This signal is used to set the upper threshold value for the programmable empty flag, which defines when the signal is de-asserted. The threshold can be dynamically set in-circuit during reset. Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error on a Virtex-5 FPGA block or built-in macro. For detailed information, see "Chapter 4, Designing with the Core," in the Generator User Guide. Double Bit Error: Indicates that the ECC decoder detected a double-bit error on a Virtex-5 FPGA block or built-in macro and data in the core is corrupted. For detailed information, see "Chapter 4, Designing with the Core," in the Generator User Guide. Port Summary Table 8 describes all the Generator ports. For detailed information about any of the ports, see "Chapter 3, Core Architecture," in the Generator User Guide. Table 8: Generator Ports Port Name or Optional Port Clocks Port Available Common Clock RST I Yes Yes Yes SRST I Yes No Yes CLK I No No Yes DATA_COUNT[C:0] O Yes No Yes Write Interface Signals WR_CLK I No Yes No DIN[N:0] I No Yes Yes WR_EN I No Yes Yes FULL O No Yes Yes ALMOST_FULL O Yes Yes Yes PROG_FULL O Yes Yes Yes WR_DATA_COUNT[D:0] O Yes Yes No WR_ACK O Yes Yes Yes OVERFLOW O Yes Yes Yes PROG_FULL_THRESH I Yes Yes Yes PROG_FULL_THRESH_ASSERT I Yes Yes Yes PROG_FULL_THRESH_NEGATE I Yes Yes Yes DS317 September 19,

14 Table 8: Generator Ports (Continued) Port Name or Read Interface Signals Optional Port Clocks Port Available Common Clock RD_CLK I No Yes No DOUT[M:0] O No Yes Yes RD_EN I No Yes Yes EMPTY O No Yes Yes ALMOST_EMPTY O Yes Yes Yes PROG_EMPTY O Yes Yes Yes RD_DATA_COUNT[C:0] O Yes Yes No VALID O Yes Yes Yes UNDERFLOW O Yes Yes Yes PROG_EMPTY_THRESH I Yes Yes Yes PROG_EMPTY_THRESH_ASSERT I Yes Yes Yes PROG_EMPTY_THRESH_NEGATE I Yes Yes Yes SBITERR O Yes Yes Yes DBITERR O Yes Yes Yes Resource Utilization and Performance Performance and resource utilization for a varies depending on the configuration and features selected during core customization. The following tables show resource utilization data and maximum performance values for a variety of sample configurations. Table 9 identifies the results for a configured without optional features. Benchmarks were performed using Virtex-II 2v3000, Virtex-4 4vlx15-11, and Virtex-5 5vlx50-2 FPGAs. Table 9: Benchmarks: Configured without Optional Features Type Synchronous (block ) Synchronous (block ) Depth x Width 512 x x 16 FPGA Family Performance (MHz) LUTs FFs Resources Block Shift Register Distributed Virtex MHz Virtex MHz Virtex-II 195 MHz Virtex MHz Virtex MHz Virtex-II 190 MHz DS317 September 19, 2008

15 Table 9: Benchmarks: Configured without Optional Features (Continued) Type Synchronous (Distributed ) Synchronous (Distributed ) Clocks (block ) Clocks (block ) Clocks (Distributed Clocks (Distributed Shift Register Shift Register Depth x Width 64 x x x x x x x x 16 FPGA Family Performance (MHz) LUTs Resources Virtex MHz Virtex MHz Virtex-II 265 MHz Virtex MHz Virtex MHz Virtex-II 185 MHz Virtex MHz Virtex MHz Virtex-II 230 MHz Virtex MHz Virtex MHz Virtex-II 225 MHz Virtex MHz Virtex MHz Virtex-II 290 MHz Virtex MHz Virtex MHz Virtex-II 195 MHz Virtex MHz Virtex MHz Virtex-II 255 MHz Virtex MHz Virtex MHz Virtex-II 180 MHz FFs Block Shift Register Distributed DS317 September 19,

16 Table 10 provides results for s configured with multiple programmable thresholds. The benchmarks were performed using Virtex-II 2v3000, Virtex-4 4vlx15-11, and Virtex-5 5vlx50-2 FPGAs. Table 10: Benchmarks: Configured with Multiple Programmable Thresholds Type Synchronous (block ) Synchronous (block ) Synchronous (Distributed ) Synchronous (Distributed ) Clocks (block Clocks (block ) Clocks (Distributed Clocks (Distributed Shift Register Shift Register Depth x Width 512 x x x x x x x x x x 16 FPGA Family Performance (MHz) LUTs FFs Resources Block Shift Register Distributed Virtex MHz Virtex MHz Virtex-II 195 MHz Virtex MHz Virtex MHz Virtex-II 190 MHz Virtex MHz Virtex MHz Virtex-II 235 MHz Virtex MHz Virtex MHz Virtex-II 190 MHz Virtex MHz Virtex MHz Virtex-II 230 MHz Virtex MHz Virtex MHz Virtex-II 215 MHz Virtex MHz Virtex MHz Virtex-II 245 MHz Virtex MHz Virtex MHz Virtex-II 190 MHz Virtex MHz Virtex MHz Virtex-II 250 MHz Virtex MHz Virtex MHz Virtex-II 180 MHz DS317 September 19, 2008

17 Table 11 provides results for s configured to use the Virtex-5 FPGA built-in. The benchmarks were performed using a Virtex-5 5vlx50-2 FPGA. Table 11: Benchmarks: Configured with Virtex-5 36 Resources Type Synchronous 36 (basic) Synchronous 36 (with handshaking) Clocks 36 (basic) Clocks 36 (with handshaking) Depth x Width 512 x 72 16k x x 72 16k x x 72 16k x x 72 16k x 8 Read Mode Performance (MHz) Resources LUTs FFs 36s Standard FWFT Standard FWFT Standard FWFT Standard FWFT Standard FWFT Standard FWFT Standard FWFT Standard FWFT Table 12 provides results for s configured to use the Virtex-4 built-in with patch. The benchmarks were performed using a Virtex-4 4vlx15-11 FPGA. Table 12: Benchmarks: Configured with Virtex-4 16 Patch Type Depth x Width Clock Ratios Performance (MHz) LUTs FFs Resources Distributed s 16s Built-in (basic) 512 x 36 Built-in (with handshaking) 512 x 36 WR_CLK RD_CLK RD_CLK > WR_CLK WR_CLK RD_CLK RD_CLK > WR_CLK DS317 September 19,

18 Verification Xilinx has verified the Generator core in a proprietary test environment, using an internally developed bus functional model. Tens of thousands of test vectors were generated and verified, including both valid and invalid write and read data accesses. References [1] Generator User Guide (UG175) [2] Virtex-4 User Guide (UG070) Ordering Information The Generator core is free of charge and is included with the Xilinx ISE CORE Generator system. Updates to the core are bundled with ISE IP Updates, accessible from the Xilinx Download Center. To order Xilinx software, please contact your local Xilinx sales representative. Information about additional Xilinx LogiCORE IP modules is available at the Xilinx IP Center. Related Information Xilinx products are not intended for use in life-support appliances, devices, or systems. Use of a Xilinx product in such application without the written consent of the appropriate Xilinx officer is prohibited. Support For technical support, visit Xilinx provides technical support for this product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support of the product if implemented in devices not listed in the documentation, if customized beyond that allowed in the product documentation, or if any changes are made in sections of design marked DO NOT MODIFY. Revision History The table below shows the revision history of this document. Date Version Revision 4/23/ Initial Xilinx release. 5/21/ Support for Virtex-4 built-in implementation. 11/11/ Updated for Xilinx software v6.3i. 04/28/ /31/ The original product specification has been divided into two documents - a data sheet and a user guide. The document has also been updated to indicate core support of first-word fall-through feature and Xilinx software v7.1i. Updated Xilinx v7.1i to SP3, removed references to first-word fall-through as new in this release. Updated basic benchmark value to reflect increased performance. 1/18/ Minor updates for release v2.3, advanced ISE support to 8.1i. 7/13/ Added support for Virtex-5, ISE to v8.2i, core version to 3.1 9/21/ Core version updated to 3.2, support for Spartan-3A added to Facts table. 2/15/ Updates to Xilinx tools 9.1i, core version /02/ Added support for Spartan-3A DSP devices, upgraded Cadence IUS version to DS317 September 19, 2008

19 Date Version Revision 8/8/ Updated to Xilinx tools v9.2i; Cadence IUS v /10/ Updated for IP2 Jade Minor release. 3/24/ Updated core to version 4.3; Xilinx tools to /19/ Updated core to version 4.4; Xilinx tools 10.1, SP3. Notice of Disclaimer Xilinx is providing this design, code, or information (collectively, the "Information") to you "AS IS" with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Except as stated herein, none of the Information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. DS317 September 19,

20 20 DS317 September 19, 2008