Computer Architecture Lecture No.4 5-Instruction Set Architecture and Design 5-1 Memory locations and Operations. word

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1 5-Instruction Set Architecture and Design There are basic principles involved in instruction set architecture and design. Therefore, this section includes many important issues will discuss. 5-1 Memory locations and Operations. The main memory can be modeled as an array of millions of adjacent cells, each capable of storing a binary digit (bit), having value of 1 or 0. These cells are organized in the form of groups of fixed number, say n, of cells that can be dealt with as an atomic entity. An entity consisting of 8 bits is called a byte. In many systems, the entity consisting of n bits that can be stored and retrieved in and out of the memory using one basic memory operation is called a word (the smallest addressable entity). Typical size of a word ranges from 16 to 64 bits. It is, however, customary to express the size of the memory in terms of bytes. For example, the size of a typical memory of a personal computer is 256 Mbytes, that is, 256 * 2 20 = 2 28 bytes. ( where 265 = 2 8 and Mbytes = 2 20 ) In order to be able to move a word in and out of the memory, a distinct address has to be assigned to each word. This address will be used to determine the location in the memory in which a given word is to be stored. This is called a memory write operation. Similarly, the address will be used to determine the memory location from which a word is to be retrieved from the memory. This is called a memory read operation (as mentioned in lecture 2). The number of bits, l, needed to distinctly address M words in a memory is given by l = log 2 M. For example, if the size of the memory is 64 M (read as 64 mega words), then the number of bits in the address is log 2 (64 * 2 20 ) = log 2 (2 26 ) = 26 bits. Alternatively, if the number of bits in the address is l, then the maximum memory size (in terms of the number of words that 24

2 can be addressed using these l bits) is M = 2 l. Figure (4.1) illustrates the concept of memory words and word address as explained above. Figure (4.1) Illustration of the main memory addressing 5.2 Instruction formats. Any instruction issued by the processor must carry at least two types of information. These are the operation to be performed, encoded in what is called the op-code field, and the address information of the operand on which the operation is to be performed, encoded in what is called the address field. 25

3 5.3 Instructions Types Instructions can be classified based on the number of operands as: Three Address Instructions In instruction that have three operands, one of the operand specifies the destination as an address where the result is to be saved. The other two operands specify the source either as addresses of memory location or constants. Example 1: Execute the following instruction using three address format: Sol : the solution is shown below, together with comments that explain the register transfer operation of each instruction. 1 mul R1,c,b R1 c*b 2 sub R2,r,d R2 r-d 3 div X, R1,R2 X r1/r2 The advantage of the three-address format is that it results in short programs when evaluating arithmetic expressions Two'Address Instructions In this type both operands specify sources. The first operand also specifies the destination address after the result is to be saved. The first operand must be an address in memory, but the second may be an address or a constant. Example 2 : Execute the following instruction using two address format : Sol : the solution is shown below, together with comments that explain the register transfer operation of each instruction. 26

4 1 mov R1,c R1 c 2 mul R1,b R1 R1*b 3 Mov R2,r R2 r 4 Sub R2,d R2 R2-d 5 Div R1,R2 R1 R1/R2 6 Mov x,r1 x R1 Note that : In this type of instruction we can use (mov) beside the arithmetic operations. This method requires more steps than previous method to represent the same instruction. For temporary storage use a register One'Address Instructions Some computer has only one general purpose register, usually called Ac "Accumulator". It is implied as one of the source operands and the destination operand in memory instruction the other source operand is specified in the instruction as location in memory. Example 3 : Execute the following instruction using one address format : Sol : the solution is shown below, together with comments that explain the register transfer operation of each instruction. 1 load r Ac r 2 Sub d Ac Ac-d 3 Store t T Ac 4 load c Ac c 5 Mul b Ac Ac*b 6 Div t Ac Ac/t 7 Store x X Ac 27

5 Note that : In this type of instruction we can use (load) and (store) beside the arithmetic operations. This method requires more steps than previous methods to represent the same instruction. For temporary storage use a memory location and is not a register. Why? Zero'Address Instructions Some computers have arithmetic instruction in which all operands are implied, these zero operand instruction use a stack. A stack is a list structure in which all insertion and deletion occur at one end, the element on a stack may be removed only in the reverse of the order in which they were entered. The process of inserting an item is called Pushing, removing an item is called Popping. Example: Execute the following instruction using Zero-address format: Sol : 1 Push d TOS d "TOP :Top OF Stack" 2 Push r TOS r 3 Sub Pop d Pop r Sub them TOS (r-d) 4 Push b TOS b 5 Push c TOS c 6 Mul Pop c Pop b multiply them TOS (c*b) 7 Div Pop (c*b) Pop (r-d) 28

6 Divide TOS (c*b) / (r-d) 8 Pop x X TOS Home Work: Execute the following instruction using all previous instruction format types: 1- X = (A + B)* (C + D) 2- S = F-(C*B)+M 3- N= (A+B*C)/ (F*E) 5.4 Instruction Length Instruction length is the number of bits or bytes which defines an instruction. This can be done simply by specifying how many bits in each field in the instruction. The length of pcode field is inferred from the (No. of instructions) supported by the processor. By convert the No. of instruction supported by the processor to the form 2 n, n will be the No. of bits for (opcode field). Example : If the CPU can do 64 instruction, then the no. of bits in the opcode field will be : n=6.therefore the no. of bits =6. The length of address field is inferred from memory which is formulated as follow: 2 n B 2 n W (30 KW, 256 MB, 1GB..) Where n will be the No. of bits in each address field. 29

7 Example : Memory size = 1 KB 1K = 2 10 n= 10 Address bits =10 Example: A Computer have memory size 16 kw where word is 16 bit. The instruction stored in one location (word) the instruction have three parts : operation code field, and address field. 1- How many bit in each field? 2- Draw the instruction format and indicate the No. of bits. 3- Specify the No. of operation in this computer. SOL: 1- Memory size = 16 kw 16 k = = bit address line. No. of bit for operand field = 14. Now: The instruction stored in one location (word) and the word =16 bit No. of bit for opcode field = = 2 2- Opcode Operand (address) 2 bit 14 bit 3-The No. of bit for operation = 2 No. of bit for opcode field = 2 2 = 4 operations 30

Chapter 04: Instruction Sets and the Processor organizations. Lesson 18: Stack-based processor Organisation

Chapter 04: Instruction Sets and the Processor organizations Lesson 18: Stack-based processor Organisation 1 Objective To understand stack based processor organisation Instruction set of a stack organized