SST26WF040B/040BA SST26WF080B/080BA

Transcription

1 SST26WF040B/040BA SST26WF080B/080BA 1.8V 4 Mbit and 8 Mbit Serial Quad I/O (SQI) Flash Memory Features Single Voltage Read and Write Operations V Serial Interface Architecture - Mode 0 and Mode 3 - Nibble-wide multiplexed I/O s with SPI-like serial command structure - x1/x2/x4 Serial Peripheral Interface (SPI) Protocol High Speed Clock Frequency MHz max Burst Modes - Continuous linear burst - 8/16/32/64 Byte linear burst with wrap-around Superior Reliability - Endurance: 100,000 Cycles (min) - Greater than 100 years Data Retention Low Power Consumption: - Active Read current: 15 ma 104 MHz) - Standby current: 10 µa (typical) - Deep Power-Down current: 1.8 µa (typical) Fast Erase Time - Sector/Block Erase: 18 ms (typ), 25 ms (max) - Chip Erase: 35 ms (typ), 50 ms (max) Page-Program Bytes per page in x1 or x4 mode End-of-Write Detection - Software polling the BUSY bit in status register Flexible Erase Capability - Uniform 4 KByte sectors - Four 8 KByte top and bottom parameter overlay blocks - One 32 KByte top and bottom overlay block - Uniform 64 KByte overlay blocks Write-Suspend - Suspend Program or Erase operation to access another block/sector Software Reset (RST) mode Software Write Protection - Individual-Block Write Protection with permanent lock-down capability - 64 KByte blocks, two 32 KByte blocks, and eight 8 KByte parameter blocks - Read Protection on top and bottom 8 KByte parameter blocks Security ID - One-Time Programmable (OTP) 2 KByte, Secure ID - 64 bit unique, factory pre-programmed identifier - User-programmable area Temperature Range - Industrial: -40 C to +85 C Packages Available - 8-contact WDFN (6mm x 5mm) - 8-lead SOIC (150 mil) - 8-contact USON (2mm x 3mm) - 8-ball XFBGA (Z-Scale ) All devices are RoHS compliant Product Description The Serial Quad I/O (SQI ) family of flash-memory devices features a six-wire, 4-bit I/O interface that allows for low-power, high-performance operation in a low pin-count package. SST26WF040B/040BA and SST26WF080B/ 080BA also support full command-set compatibility to traditional Serial Peripheral Interface (SPI) protocol. System designs using SQI flash devices occupy less board space and ultimately lower system costs. All members of the 26 Series, SQI family are manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST26WF040B/040BA and SST26WF080B/ 080BA significantly improves performance and reliability, while lowering power consumption. This device writes (Program or Erase) with a single power supply of V. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. SST26WF040B/040BA and SST26WF080B/080BA is offered in 8-contact WDFN (6 mm x 5 mm), 8-lead SOIC (150 mil), 8-contact USON, and 8-ball XFBGA (Z-Scale ) packages. See Figure 2-1 for pin assignments. Two configurations are available upon order: SST26WF040B and SST26WF080B default at powerup has the WP# and Hold# pins enabled and SST26WF040BA and SST26WF080BA default at power-up has the WP# and Hold# pins disabled Microchip Technology Inc. DS C-page 1

2 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E- mail at We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS A is version A of document DS ). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: Microchip s Worldwide Web site; Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at to receive the most current information on all of our products. DS C-page Microchip Technology Inc.

3 1.0 BLOCK DIAGRAM FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches X - Decoder OTP SuperFlash Memory Y - Decoder Control Logic Page Buffer, I/O Buffers and Data Latches Serial Interface WP# HOLD# SIO [3:0] B Microchip Technology Inc. DS C-page 3

4 2.0 PIN DESCRIPTION FIGURE 2-1: PIN DESCRIPTION FOR 8-LEAD SOIC, 8-CONTACT WDFN, AND 8-BALL XFBGA 1 8 V DD 1 8 V DD SO/SIO1 WP#/SIO2 2 3 Top View 7 6 HOLD#/SIO3 SO/SIO1 WP#/SIO2 2 3 Top View 7 6 HOLD#/SIO3 V SS 4 5 SI/SIO0 V SS 4 5 SI/SIO soic S2A P wson QA P1.0 8-Lead SOIC 8-Contact WDFN Top View (Balls Facing Down) 1 8 VDD 2 1 SO/SIO1 WP#/ SIO2 V SS SO/SIO1 WP#/SIO2 2 3 Top View 7 6 HOLD#/SIO3 V DD HOLD#/ SIO3 SI/SIO0 VSS 4 5 SI/SIO0 A B C D 8-Ball CSP xfbga P1.0 8-Contact USON x4-USON P1.0 DS C-page Microchip Technology Inc.

5 TABLE 2-1: PIN DESCRIPTION Symbol Pin Name Functions Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SIO[3:0] Serial Data Input/Output To transfer commands, addresses, or data serially into the device or data out of the device. Inputs are latched on the rising edge of the serial clock. Data is shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO) command instruction configures these pins for Quad I/O mode. SI SO Serial Data Input for SPI mode Serial Data Output for SPI mode To transfer commands, addresses or data serially into the device. Inputs are latched on the rising edge of the serial clock. SI is the default state after a power on reset. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. SO is the default state after a power on reset. Chip Enable The device is enabled by a high to low transition on. must remain low for the duration of any command sequence; or in the case of Write operations, for the command/data input sequence. WP# Write Protect The WP# pin is used in conjunction with the WPEN and IOC bits in the configuration register to prohibit Write operations to the Block-Protection register. This pin only works in SPI, single-bit and dual-bit Read mode. HOLD# Hold Temporarily stops serial communication with the SPI Flash memory while the device is selected. This pin only works in SPI, single-bit and dual-bit Read mode. This pin must be tied high when not in use. V DD Power Supply To provide power supply voltage. V SS Ground Microchip Technology Inc. DS C-page 5

6 3.0 MEMORY ORGANIZATION The SST26WF040B/040BA and SST26WF080B/080BA SQI memory array is organized in uniform, 4 KByte erasable sectors with the following erasable blocks: eight 8 KByte parameter, two 32 KByte overlay, and six 64 KByte blocks (4 Mbit) or fourteen 64 KByte (8 Mbit) overlay blocks. See Figure 3-1. FIGURE 3-1: MEMORY MAP Top of Memory Block 8 KByte 8 KByte 8 KByte 8 KByte 32 KByte 64 KByte... 2 Sectors for 8 KByte blocks 8 Sectors for 32 KByte blocks 16 Sectors for 64 KByte blocks 64 KByte 4 KByte 4 KByte... 4 KByte 4 KByte 64 KByte 32 KByte 8 KByte 8 KByte 8 KByte 8 KByte Bottom of Memory Block F41.0 DS C-page Microchip Technology Inc.

7 4.0 DEVICE OPERATION The SST26WF040B/040BA and SST26WF080B/ 080BA support both Serial Peripheral Interface (SPI) bus protocol and a 4-bit multiplexed SQI bus protocol. To provide backward compatibility to traditional SPI Serial Flash devices, the device s initial state after a power-on reset is SPI mode which supports multi-i/o (x1/x2/x4) Read/Write commands. A command instruction configures the device to SQI mode. The dataflow in the SQI mode is similar to the SPI mode, except it uses four multiplexed I/O signals for command, address, and data sequence. SQI Flash Memory supports both Mode 0 (0,0) and Mode 3 (1,1) bus operations. The difference between the two modes is the state of the signal when the bus master is in stand-by mode and no data is being transferred. The signal is low for Mode 0 and signal is high for Mode 3. For both modes, the Serial Data I/O (SIO[3:0]) is sampled at the rising edge of the clock signal for input, and driven after the falling edge of the clock signal for output. The traditional SPI protocol uses separate input (SI) and output (SO) data signals as shown in Figure 4-1. The SQI protocol uses four multiplexed signals, SIO[3:0], for both data in and data out, as shown in Figure 4-2. This means the SQI protocol quadruples the traditional bus transfer speed at the same clock frequency, without the need for more pins on the package. FIGURE 4-1: MODE 3 SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE) MODE 3 SI SO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB HIGH IMPEDANCE DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB F03.0 FIGURE 4-2: SQI SERIAL QUAD I/O PROTOCOL CLK MODE 3 MODE 3 SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3 MSB F Device Protection The SST26WF040B/040BA and SST26WF080B/ 080BA offer a flexible memory protection scheme that allows the protection state of each individual block to be controlled separately. In addition, the Write-Protection Lock-Down register prevents any change of the lock status during device operation. To avoid inadvertent writes during power-up, the device is write-protected by default after a power-on reset cycle. A Global Block-Protection Unlock command offers a single command cycle that unlocks the entire memory array for faster manufacturing throughput. For extra protection, there is an additional non-volatile register that can permanently write-protect the Block- Protection register bits for each individual block. Each of the corresponding lock-down bits are one time programmable (OTP) once written, they cannot be erased. Data that had been previously programmed into these blocks cannot be altered by programming or erase and is not reversible INDIVIDUAL BLOCK PROTECTION The SST26WF040B/040BA and SST26WF080B/ 080BA have a Block-Protection register which provides a software mechanism to write-lock the individual memory blocks and write-lock, and/or read-lock, the individual parameter blocks. The Block-Protection register is 24 bits (4 Mbit) or 32 (8 Mbit) wide: two bits each for the eight 8 KByte parameter blocks (write-lock and read-lock), and one bit each for the remaining 32 KByte and 64 KByte overlay blocks (write-lock). See Table 5-6 for address range protected per register bit. Each bit in the Block-Protection register (BPR) can be written to a 1 (protected) or 0 (unprotected). For the parameter blocks, the most significant bit is for read-lock, and the least significant bit is for write-lock. Read-locking the parameter blocks provides additional security for sensitive data after retrieval (e.g., after initial boot). If a block is read-locked all reads to the block return data 00H. The Write Block-Protection Register command is a two-cycle command which requires that Write-Enable (WREN) is executed prior to the Write Block-Protection Microchip Technology Inc. DS C-page 7

8 Register command. The Global Block-Protection Unlock command clears all write protection bits in the Block-Protection register WRITE-PROTECTION LOCK- DOWN (VOLATILE) To prevent changes to the Block-Protection register, use the Lock-Down Block-Protection Register (LBPR) command to enable Write-Protection Lock-Down. Once Write-Protection Lock-Down is enabled, the Block-Protection register can not be changed. To avoid inadvertent lock down, the WREN command must be executed prior to the LBPR command. To reset Write-Protection Lock-Down, performing a power cycle on the device is required. The Write-Protection Lock-Down status may be read from the Status register WRITE-LOCK LOCK-DOWN (NON-VOLATILE) The non-volatile Write-Lock Lock-Down register is an alternate register that permanently prevents changes to the block-protect bits. The non-volatile Write-Lock Lock-Down register (nvwldr) is 16 bits (4 Mbit) or 24 bits (8 Mbit) wide per device: one bit each for the eight 8-KByte parameter blocks, and one bit each for the remaining 32 KByte and 64 KByte overlay blocks. See Table 5-6 for address range protected per register bit. Writing 1 to any or all of the nvwldr bits disables the change mechanism for the corresponding Write-Lock bit in the BPR, and permanently sets this bit to a 1 (protected) state. After this change, both bits will be set to 1, regardless of the data entered in subsequent writes to either the nvwldr or the BPR. Subsequent writes to the nvwldr can only alter available locations that have not been previously written to a 1. This method provides write-protection for the corresponding memory-array block by protecting it from future program or erase operations. Writing a 0 in any location in the nvwldr has no effect on either the nvwldr or the corresponding Write-Lock bit in the BPR. Note that if the Block-Protection register had been previously locked down, see Write-Protection Lock- Down (Volatile), the device must be power cycled before using the nvwldr. If the Block-Protection register is locked down and the Write nvwldr command is accessed, the command will be ignored. 4.2 Hardware Write Protection The hardware Write Protection pin (WP#) is used in conjunction with the WPEN and IOC bits in the configuration register to prohibit write operations to the Block-Protection and Configuration registers. The WP# pin function only works in SPI single-bit and dual-bit read mode when the IOC bit in the configuration register is set to 0. The WP# pin function is disabled when the WPEN bit in the configuration register is 0. This allows installation of the SST26WF040B/040BA and SST26WF080B/ 080BA in a system with a grounded WP# pin while still enabling Write to the Block-Protection register. The Lock-Down function of the Block-Protection Register supersedes the WP# pin, see Table 4-1 for Write Protection Lock-Down states. The factory default setting at power-up of the WPEN bit is 0, disabling the Write Protect function of the WP# after power-up. WPEN is a non-volatile bit; once the bit is set to 1, the Write Protect function of the WP# pin continues to be enabled after power-up. The WP# pin only protects the Block-Protection Register and Configuration Register from changes. Therefore, if the WP# pin is set to low before or after a Program or Erase command, or while an internal Write is in progress, it will have no effect on the Write command. The IOC bit takes priority over the WPEN bit in the configuration register. When the IOC bit is 1, the function of the WP# pin is disabled and the WPEN bit serves no function. When the IOC bit is 0 and WPEN is 1, setting the WP# pin active low prohibits Write operations to the Block Protection Register. TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES WP# IOC WPEN WPLD Execute WBPR Instruction Configuration Register L Not Allowed Protected L Not Allowed Writable L Not Allowed Protected L Allowed Writable H 0 X 1 Not Allowed Writable H 0 X 0 Allowed Writable X 1 X 1 Not Allowed Writable X Allowed Writable 1. Default at power-up Register settings for SST26WF040B and SST26WF080B 2. Factory default setting is 0. This is a non-volatile bit; default at power-up is the value set prior to power-down. 3. Default at power-up Register settings for SST26WF040BA and SST26WF080BA DS C-page Microchip Technology Inc.

9 4.3 Security ID SST26WF040B/040BA and SST26WF080B/080BA offers a 2 KByte Security ID (Sec ID) feature. The Security ID space is divided into two parts one factory-programmed, 64-bit segment and one user-programmable segment. The factory-programmed segment is programmed during manufacturing with a unique number and cannot be changed. The user-programmable segment is left unprogrammed for the customer to program as desired. Use the Program Security ID (PSID) command to program the Security ID using the address shown in Table 5-5. The Security ID can be locked using the Lockout Security ID (LSID) command. This prevents any future write operations to the Security ID. The factory-programmed portion of the Security ID can t be programmed by the user; neither the factoryprogrammed nor user-programmable areas can be erased. 4.4 Hold Operation The HOLD# pin pauses active serial sequences without resetting the clocking sequence. This pin is active after every power up and only operates during SPI single-bit and dual-bit modes. Two factory configurations are available: SST26WF040B and SST26WF080B ship with the IOC bit set to 0 and the HOLD# pin function enabled; SST26WF040BA and SST26WF080BA ship with the IOC bit set to 1 and the HOLD# pin function disabled. The HOLD# pin is always disabled in SQI mode and only works in SPI single-bit and dual-bit read mode. To activate the Hold mode, must be in active low state. The Hold mode begins when the active low state coincides with the falling edge of the HOLD# signal. The Hold mode ends when the HOLD# signal s rising edge coincides with the active low state. If the falling edge of the HOLD# signal does not coincide with the active low state, then the device enters Hold mode when the next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the active low state, then the device exits Hold mode when the next reaches the active low state. See Figure 4-3. Once the device enters Hold mode, SO will be in high impedance state while SI and can be VIL or VIH. If is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and must be driven active low. FIGURE 4-3: HOLD CONDITION WAVEFORM. HOLD# Active Hold Active Hold Active F Microchip Technology Inc. DS C-page 9

10 4.5 Status Register The Status register is a read-only register that provides the following status information: whether the flash memory array is available for any Read or Write operation, if the device is write-enabled, whether an erase or program operation is suspended, and if the Block- Protection register and/or Security ID are locked down. During an internal Erase or Program operation, the Status register may be read to determine the completion of an operation in progress. Table 4-2 describes the function of each bit in the Status register. TABLE 4-2: STATUS REGISTER Bit Name Function 0 BUSY Write operation status 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 WEL Write-Enable Latch status 1 = Device is write-enabled 0 = Device is not write-enabled 2 WSE Write Suspend-Erase status 1 = Erase suspended 0 = Erase is not suspended 3 WSP Write Suspend-Program status 1 = Program suspended 0 = Program is not suspended 4 WPLD Write Protection Lock-Down status 1 = Write Protection Lock-Down enabled 0 = Write Protection Lock-Down disabled 5 SEC 1 Security ID status 1 = Security ID space locked 0 = Security ID space not locked Default at Power-up Read/Write (R/ W) 0 R 0 R 0 R 0 R 0 R 0 1 R 6 RES Reserved for future use 0 R 7 BUSY Write operation status 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 0 R 1. The Security ID status will always be 1 at power-up after a successful execution of the Lockout Security ID instruction, otherwise default at power-up is WRITE-ENABLE LATCH (WEL) The Write-Enable Latch (WEL) bit indicates the status of the internal memory s Write-Enable Latch. If the WEL bit is set to 1, the device is write enabled. If the bit is set to 0 (reset), the device is not write enabled and does not accept any memory Program or Erase, Protection Register Write, or Lock-Down commands. The Write-Enable Latch bit is automatically reset under the following conditions: Power-up Reset Write-Disable (WRDI) instruction Page-Program instruction completion Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Write-Block-Protection register instruction Lock-Down Block-Protection register instruction Program Security ID instruction completion Lockout Security ID instruction completion Write-Suspend instruction SPI Quad Page Program Write Status Register WRITE SUSPEND ERASE STATUS (WSE) The Write Suspend-Erase status (WSE) indicates when an Erase operation has been suspended. The WSE bit is 1 after the host issues a suspend command during an Erase operation. Once the suspended Erase resumes, the WSE bit is reset to 0. DS C-page Microchip Technology Inc.

11 4.5.3 WRITE SUSPEND PROGRAM STATUS (WSP) The Write Suspend-Program status (WSP) bit indicates when a Program operation has been suspended. The WSP is 1 after the host issues a suspend command during the Program operation. Once the suspended Program resumes, the WSP bit is reset to WRITE PROTECTION LOCK-DOWN STATUS (WPLD) The Write Protection Lock-Down status (WPLD) bit indicates when the Block-Protection register is lockeddown to prevent changes to the protection settings. The WPLD is 1 after the host issues a Lock-Down Block-Protection command. After a power cycle, the WPLD bit is reset to SECURITY ID STATUS (SEC) The Security ID Status (SEC) bit indicates when the Security ID space is locked to prevent a Write command. The SEC is 1 after the host issues a Lockout SID command. Once the host issues a Lockout SID command, the SEC bit can never be reset to BUSY The Busy bit determines whether there is an internal Erase or Program operation in progress. If the BUSY bit is 1, the device is busy with an internal Erase or Program operation. If the bit is 0, no Erase or Program operation is in progress CONFIGURATION REGISTER The Configuration register is a Read/Write register that stores a variety of configuration information. See Table 4-3 for the function of each bit in the register. TABLE 4-3: CONFIGURATION REGISTER Bit Name Function Default at Power-up Read/Write (R/W) 0 RES Reserved 0 R 1 IOC I/O Configuration for SPI Mode 1 = WP# and HOLD# pins disabled 0 = WP# and HOLD# pins enabled 0 1 R/W 2 RES Reserved 0 R 3 BPNV Block-Protection Volatility State 1 = No memory block has been permanently locked 1 R 0 = Any block has been permanently locked 4 RES Reserved 0 R 5 RES Reserved 0 R 6 RES Reserved 0 R 7 WPEN Write-Protection Pin (WP#) Enable 1 = WP# enabled 0 = WP# disabled 1. SST26WF040B and SST26WF080B default at Power-up is 0 SST26WF040BA and SST26WF080BA default at Power-up is 1 2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down. 0 2 R/W Microchip Technology Inc. DS C-page 11

12 4.5.8 I/O CONFIGURATION (IOC) The I/O Configuration (IOC) bit re-configures the I/O pins. The IOC bit is set by writing a 1 to Bit 1 of the Configuration register. When IOC bit is 0 the WP# pin and HOLD# pin are enabled (SPI or Dual Configuration setup). When IOC bit is set to 1 the SIO2 pin and SIO3 pin are enabled (SPI Quad I/O Configuration setup). The IOC bit must be set to 1 before issuing the following SPI commands: SQOR (6BH), SQIOR (EBH), RBSPI (ECH), and SPI Quad page program (32H). Without setting the IOC bit to 1, those SPI commands are not valid. The I/O configuration bit does not apply when in SQI mode. The default at power-up for SST26WF040B and SST26WF080B is 0 and for SST26WF040BA and SST26WF080BA is BLOCK-PROTECTION VOLATILITY STATE (BPNV) The Block-Protection Volatility State bit indicates whether any block has been permanently locked with the non-volatile Write-Lock Lock-Down register (nvwldr). When no bits in the nvwldr have been set (the default state from the factory) the BPNV bit is `1'; when one or more bits in the nvwldr are set to `1' the BPNV bit will also be `0' from that point forward, even after power-up WRITE-PROTECT ENABLE (WPEN) The Write-Protect Enable (WPEN) bit is a non-volatile bit that enables the WP# pin. The Write-Protect (WP#) pin and the Write-Protect Enable (WPEN) bit control the programmable hardware write-protect feature. Setting the WP# pin to low, and the WPEN bit to 1, enables Hardware write-protection. To disable Hardware write protection, set either the WP# pin to high or the WPEN bit to 0. There is latency associated with writing to the WPEN bit. Poll the BUSY bit in the Status register, or wait T WPEN, for the completion of the internal, self-timed Write operation. When the chip is hardware write protected, only Write operations to Block-Protection and Configuration registers are disabled. See Hardware Write Protection on page 8 and Table 4-1 for more information about the functionality of the WPEN bit. DS C-page Microchip Technology Inc.

13 5.0 INSTRUCTIONS Instructions are used to read, write (erase and program), and configure the SST26WF040B/040BA and SST26WF080B/080BA. The complete list of the instructions is provided in Table 5-1. TABLE 5-1: Instruction DEVICE OPERATION INSTRUCTIONS FOR SST26WF040B/040BA AND SST26WF080B/080BA (1 OF 2) Description Command Cycle 1 SPI Mode SQI Address Cycle(s) 2, 3 Dummy Cycle(s) 3 Data Cycle(s) 3 Max Freq Configuration NOP No Operation 00H X X RSTEN Reset Enable 66H X X MHz RST 4 Reset Memory 99H X X EQIO Enable Quad I/O 38H X RSTQIO 5 Reset Quad I/O FFH X X RDSR Read Status Register 05H X to X to WRSR Write Status Register 01H X X RDCR Read Configuration 35H X to Register X to Read Read Read Memory 03H X to 40 MHz High-Speed Read Read Memory at Higher Speed 0BH X to 104 MHz X to SQOR 6 SPI Quad Output Read 6BH X to SQIOR 7 SPI Quad I/O Read EBH X to SDOR 8 SPI Dual Output Read 3BH X to SDIOR 9 SPI Dual I/O Read BBH X to 80 MHz SB Set Burst Length C0H X X RBSQI SQI nb Burst with 0CH X 3 3 n to MHz Wrap RBSPI 7 SPI nb Burst with Wrap ECH X 3 3 n to Identification JEDEC-ID JEDEC-ID Read 9FH X to 104 Quad J-ID Quad I/O J-ID Read AFH X to MHz SFDP Serial Flash Discoverable Parameters 5AH X to Write WREN Write Enable 06H X X WRDI Write Disable 04H X X MHz SE 10 Erase 4 KBytes of 20H X X Memory Array BE 11 Erase 64, 32 or 8 KBytes of Memory Array D8H X X CE Erase Full Array C7H X X PP Page Program 02H X X to Microchip Technology Inc. DS C-page 13

14 TABLE 5-1: Instruction SPI Quad PP 6 WRSU WRRE Protection RBPR DEVICE OPERATION INSTRUCTIONS FOR SST26WF040B/040BA AND SST26WF080B/080BA (CONTINUED) (2 OF 2) Description SQI Quad Page Program Suspends Program/ Erase Resumes Program/ Erase Read Block-Protection Register Command Cycle 1 32H X to MHz B0H X X H X X H X to MHz X to 6 WBPR Write Block-Protection 42H X X to 6 Register LBPR Lock Down Block- 8DH X X Protection Register nvwldr non-volatile Write E8H X X to 6 Lock-Down Register ULBPR Global Block Protection 98H X X Unlock RSID Read Security ID 88H X to 2048 X to 2048 PSID Program User A5H X X to 256 Security ID area LSID Lockout Security ID Programming 85H X X SPI Mode Address Cycle(s) 2, 3 Dummy Cycle(s) 3 Data Cycle(s) 3 Max Freq Power Saving DPD Deep Power-down Mode B9H X X RDPD Release from Deep Power-down and Read ID ABH X X to MHz 0 1. Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode. 2. Address bits above the most significant bit of each density can be V IL or V IH. 3. Address, Dummy/Mode bits, and Data cycles are two clock periods in SQI and eight clock periods in SPI mode. 4. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. 5. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode. 6. Data cycles are two clock periods. IOC bit must be set to 1 before issuing the command. 7. Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to 1 before issuing the command. 8. Data cycles are four clock periods. 9. Address, Dummy/Mode bits, and Data cycles are four clock periods. 10. Sector Addresses: Use A MS - A 12, remaining address are don t care, but must be set to V IL or V IH. 11. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: A MS - A 16 for 64 KByte; A MS - A 15 for 32 KByte; A MS - A 13 for 8 KByte. Remaining addresses are don t care, but must be set to V IL or V IH. SQI DS C-page Microchip Technology Inc.

15 5.1 No Operation (NOP) The No Operation command only cancels a Reset Enable command. NOP has no impact on any other command. 5.2 Reset-Enable (RSTEN) and Reset (RST) The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode. This operation consists of two commands: Reset-Enable (RSTEN) followed by Reset (RST). To reset the SST26WF040B/040BA and SST26WF080B/080BA, the host drives low, sends the Reset-Enable command (66H), and drives high. Next, the host drives low again, sends the Reset command (99H), and drives high, see Figure 5-1. The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the Reset-Enable. Once the Reset-Enable and Reset commands are successfully executed, the device returns to normal operation Read mode and then does the following: resets the protocol to SPI mode, resets the burst length to 8 Bytes, clears all the bits, except for bit 4 (WPLD) and bit 5 (SEC), in the Status register to their default states, and clears bit 1 (IOC) in the configuration register to its default state. A device reset during an active Program or Erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. Depending on the prior operation, the reset timing may vary. Recovery from a Write operation requires more latency time than recovery from other operations. See Table 8-2 on page 46 for Rest timing parameters. FIGURE 5-1: RESET SEQUENCE T CPH CLK MODE 3 MODE 3 MODE 3 SIO(3:0) C1 C0 C3 C F05.0 Note: C[1:0] = 66H; C[3:2] = 99H 5.3 Read (40 MHz) The Read instruction, 03H, is supported in SPI bus protocol only with clock frequencies up to 40 MHz. This command is not supported in SQI bus protocol. The device outputs the data starting from the specified address location, then continuously streams the data output through all addresses until terminated by a lowto-high transition on. The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically return to the beginning (wrap-around) of the address space. Initiate the Read instruction by executing an 8-bit command, 03H, followed by address bits A[23:0]. must remain active low for the duration of the Read cycle. See Figure 5-2 for Read Sequence. FIGURE 5-2: READ SEQUENCE (SPI) MODE SI SO MSB 03 ADD. MSB HIGH IMPEDANCE ADD. ADD. N N+1 N+2 N+3 N+4 D OUT MSB D OUT DOUT DOUT DOUT F Microchip Technology Inc. DS C-page 15

16 5.4 Enable Quad I/O (EQIO) The Enable Quad I/O (EQIO) instruction, 38H, enables the flash device for SQI bus operation. Upon completion of the instruction, all instructions thereafter are expected to be 4-bit multiplexed input/output (SQI mode) until a power cycle or a Reset Quad I/O instruction is executed. See Figure 5-3. FIGURE 5-3: ENABLE QUAD I/O SEQUENCE MODE SIO0 38 SIO[3:1] F43.0 Note: SIO[3:1] must be driven V IH 5.5 Reset Quad I/O (RSTQIO) The Reset Quad I/O instruction, FFH, resets the device to 1-bit SPI protocol operation or exits the Set Mode configuration during a read sequence. This command allows the flash device to return to the default I/O state (SPI) without a power cycle, and executes in either 1- bit or 4-bit mode. If the device is in the Set Mode configuration, while in SQI High-Speed Read mode, the RSTQIO command will only return the device to a state where it can accept new SQI command instruction. An additional RSTQIO is required to reset the device to SPI mode. To execute a Reset Quad I/O operation, the host drives low, sends the Reset Quad I/O command cycle (FFH) then, drives high. Execute the instruction in either SPI (8 clocks) or SQI (2 clocks) command cycles. For SPI, SIO[3:1] are don t care for this command, but should be driven to V IH or V IL. See Figures 5-4 and 5-5. FIGURE 5-4: RESET QUAD I/O SEQUENCE (SPI) MODE SIO0 FF SIO[3:1] Note: SIO[3:1] F73.0 FIGURE 5-5: RESET QUAD I/O SEQUENCE (SQI) MODE SIO(3:0) F F F74.0 DS C-page Microchip Technology Inc.

17 5.6 High-Speed Read (104 MHz) The High-Speed Read instruction, 0BH, is supported in both SPI bus protocol and SQI protocol. On power-up, the device is set to use SPI. Initiate High-Speed Read by executing an 8-bit command, 0BH, followed by address bits A[23-0] and a dummy byte. must remain active low for the duration of the High-Speed Read cycle. See Figure 5-6 for the High-Speed Read sequence for SPI bus protocol. FIGURE 5-6: HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH) MODE SI/SIO0 0B ADD. ADD. ADD. X SO/SIO1 HIGH IMPEDANCE N N+1 N+2 N+3 N+4 D OUT DOUT DOUT DOUT D OUT MSB F31.0 In SQI protocol, the host drives low then send the Read command cycle command, 0BH, followed by three address cycles, a Set Mode Configuration cycle, and two dummy cycles. Each cycle is two nibbles (clocks) long, most significant nibble first. After the dummy cycles, the device outputs data on the falling edge of the signal starting from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high transition on. The internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to address location H. During this operation, blocks that are Read-locked will output data 00H. The Set Mode Configuration bit M[7:0] indicates if the next instruction cycle is another SQI High-Speed Read command. When M[7:0] = AXH, the device expects the next continuous instruction to be another Read command, 0BH, and does not require the op-code to be entered again. The host may initiate the next Read cycle by driving low, then sending the four-bits input for address A[23:0], followed by the Set Mode configuration bits M[7:0], and two dummy cycles. After the two dummy cycles, the device outputs the data starting from the specified address location. There are no restrictions on address location access. When M[7:0] is any value other than AXH, the device expects the next instruction initiated to be a command instruction. To reset/exit the Set Mode configuration, execute the Reset Quad I/O command, FFH. While in the Set Mode configuration, the RSTQIO command will only return the device to a state where it can accept new SQI command instruction. An additional RSTQIO is required to reset the device to SPI mode. See Figure 5-10 for the SPI Quad I/O Mode Read sequence when M[7:0] = AXH. FIGURE 5-7: SIO(3:0) MODE 3 MSN HIGH-SPEED READ SEQUENCE (SQI) LSN C0 C1 A5 A4 A3 A2 A1 A0 M1 M0 X X X X H0 L0 H8 L8 Command Address Mode Dummy Data Byte 0 Data Byte 7 Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble Hx = High Data Nibble, Lx = Low Data Nibble C[1:0] = 0BH F Microchip Technology Inc. DS C-page 17

18 5.7 SPI Quad-Output Read The SPI Quad-Output Read instruction supports up to 104 MHz frequency. SST26WF040B and SST26WF080B requires the IOC bit in the configuration register to be set to 1 prior to executing the command. Initiate SPI Quad-Output Read by executing an 8-bit command, 6BH, followed by address bits A[23-0] and a dummy byte. must remain active low for the duration of the SPI Quad Mode Read. See Figure 5-8 for the SPI Quad Output Read sequence. Following the dummy byte, the device outputs data from SIO[3:0] starting from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high transition on. The internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. FIGURE 5-8: SPI QUAD OUTPUT READ MODE SIO0 6BH OP Code A[23:16] A[15:8] A[7:0] X b4 b0 b4 b0 Data Data Address Dummy Byte 0 Byte N SIO1 b5 b1 b5 b1 SIO2 b6 b2 b6 b2 SIO3 b7 b3 b7 b3 Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble F48.3 DS C-page Microchip Technology Inc.

19 5.8 SPI Quad I/O Read The SPI Quad I/O Read (SQIOR) instruction supports up to 104 MHz frequency. SST26WF040B and SST26WF080B requires the IOC bit in the configuration register to be set to 1 prior to executing the command. Initiate SQIOR by executing an 8-bit command, EBH. The device then switches to 4-bit I/O mode for address bits A[23-0], followed by the Set Mode configuration bits M[7:0], and two dummy bytes. must remain active low for the duration of the SPI Quad I/O Read. See Figure 5-9 for the SPI Quad I/O Read sequence. Following the dummy bytes, the device outputs data from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high transition on. The internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. The Set Mode Configuration bit M[7:0] indicates if the next instruction cycle is another SPI Quad I/O Read command. When M[7:0] = AXH, the device expects the next continuous instruction to be another Read command, EBH, and does not require the op-code to be entered again. The host may set the next SQIOR cycle by driving low, then sending the four-bit wide input for address A[23:0], followed by the Set Mode configuration bits M[7:0], and two dummy cycles. After the two dummy cycles, the device outputs the data starting from the specified address location. There are no restrictions on address location access. When M[7:0] is any value other than AXH, the device expects the next instruction initiated to be a command instruction. To reset/exit the Set Mode configuration, execute the Reset Quad I/O command, FFH. See Figure 5-10 for the SPI Quad I/O Mode Read sequence when M[7:0] = AXH. FIGURE 5-9: SPI QUAD I/O READ SEQUENCE MODE SIO0 EBH A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 b4 b0 SIO1 A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 b5 b1 SIO2 A22 A18 A14 A10 A6 A2 M6 M2 X X X X b6 b2 b6 b2 SIO3 A23 A19 A15 A11 A7 A3 M7 M3 Address Set Mode X X X X Dummy MSN LSN b7 b3 b7 b3 Data Data Byte 0 Byte 1 Note: MS F Microchip Technology Inc. DS C-page 19

20 FIGURE 5-10: BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH SIO0 b4 b0 b4 b0 A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 SIO1 b5 b1 b5 b1 A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 Note: MSN= Most SIO2 SIO3 b6 b2 b6 b2 A22A18 A14 A10 A6 A2 M6 M2 X X X X b6 b2 MSN LSN b7 b3 b7 b3 A23A19 A15 A11 A7 A3 M7 M3 X X X X b7 b3 Data Byte N Data Byte N+1 Address Set Mode Dummy Data Byte F Set Burst The Set Burst command specifies the number of bytes to be output during a Read Burst command before the device wraps around. It supports both SPI and SQI protocols. To set the burst length the host drives low, sends the Set Burst command cycle (C0H) and one data cycle, then drives high. After power-up or reset, the burst length is set to eight Bytes (00H). See Table 5-2 for burst length data and Figures 5-11 and 5-12 for the sequences. TABLE 5-2: BURST LENGTH DATA Burst Length High Nibble (H0) Low Nibble (L0) 8 Bytes 0h 0h 16 Bytes 0h 1h 32 Bytes 0h 2h 64 Bytes 0h 3h FIGURE 5-11: SET BURST LENGTH SEQUENCE (SQI) MODE SIO(3:0) Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = C0H C1 C0 H0 L0 MSN LSN F32.0 DS C-page Microchip Technology Inc.

21 FIGURE 5-12: SET BURST LENGTH SEQUENCE (SPI) MODE SIO0 C0 D IN SIO[3:1] Note: SIO[3:1] must be F SQI Read Burst with Wrap (RBSQI) SQI Read Burst with wrap is similar to High Speed Read in SQI mode, except data will output continuously within the burst length until a low-to-high transition on. To execute a SQI Read Burst operation, drive low then send the Read Burst command cycle (0CH), followed by three address cycles, and then three dummy cycles. Each cycle is two nibbles (clocks) long, most significant nibble first. After the dummy cycles, the device outputs data on the falling edge of the signal starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low-tohigh transition on. During RBSQI, the internal address pointer automatically increments until the last byte of the burst is reached, then it wraps around to the first byte of the burst. All bursts are aligned to addresses within the burst length, see Table 5-3. For example, if the burst length is eight Bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern repeats until the command is terminated by a low-to-high transition on. During this operation, blocks that are Read-locked will output data 00H SPI Read Burst with Wrap (RBSPI) SPI Read Burst with Wrap (RBSPI) is similar to SPI Quad I/O Read except the data will output continuously within the burst length until a low-to-high transition on. To execute a SPI Read Burst with Wrap operation, drive low, then send the Read Burst command cycle (ECH), followed by three address cycles, and then three dummy cycles. After the dummy cycle, the device outputs data on the falling edge of the signal starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low-tohigh transition on. During RBSPI, the internal address pointer automatically increments until the last byte of the burst is reached, then it wraps around to the first byte of the burst. All bursts are aligned to addresses within the burst length, see Table 5-3. For example, if the burst length is eight Bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. The pattern repeats until the command is terminated by a low-to-high transition on. During this operation, blocks that are Read-locked will output data 00H. TABLE 5-3: BURST ADDRESS RANGES Burst Length Burst Address Ranges 8 Bytes 00-07H, 08-0FH, 10-17H, 18-1FH Bytes 00-0FH, 10-1FH, 20-2FH, 30-3FH Bytes 00-1FH, 20-3FH, 40-5FH, 60-7FH Bytes 00-3FH, 40-7FH, 80-BFH, C0-FFH Microchip Technology Inc. DS C-page 21

22 5.12 SPI Dual-Output Read The SPI Dual-Output Read instruction supports up to 104 MHz frequency. Initiate SPI Dual-Output Read by executing an 8-bit command, 3BH, followed by address bits A[23-0] and a dummy byte. must remain active low for the duration of the SPI Dual-Output Read operation. See Figure 5-13 for the SPI Quad Output Read sequence. Following the dummy byte, the SST26WF040B/040BA and SST26WF080B/080BA output data from SIO[1:0] starting from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high transition on. The internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. FIGURE 5-13: FAST READ, DUAL-OUTPUT SEQUENCE MODE SIO0 SIO1 3BH OP Code A[23:16] A[15:8] A[7:0] X b6 b5 b3 b1 b6 b5 b3 b1 Address Dummy MSB b7 b4 b2 b0 Data Byte 0 b7 b4 b2 b0 Data Byte N Note: MSB = Most Significant Bit F SPI Dual I/O Read The SPI Dual I/O Read (SDIOR) instruction supports up to 80 MHz frequency. Initiate SDIOR by executing an 8-bit command, BBH. The device then switches to 2-bit I/O mode for address bits A[23-0], followed by the Set Mode configuration bits M[7:0]. must remain active low for the duration of the SPI Dual I/O Read. See Figure 5-14 for the SPI Dual I/O Read sequence. Following the Set Mode configuration bits, the SST26WF040B/040BA and SST26WF080B/080BA outputs data from the specified address location. The device continually streams data output through all addresses until terminated by a low-to-high transition on. The internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. The Set Mode Configuration bit M[7:0] indicates if the next instruction cycle is another SPI Dual I/O Read command. When M[7:0] = AXH, the device expects the next continuous instruction to be another SDIOR command, BBH, and does not require the op-code to be entered again. The host may set the next SDIOR cycle by driving low, then sending the two-bit wide input for address A[23:0], followed by the Set Mode configuration bits M[7:0]. After the Set Mode configuration bits, the device outputs the data starting from the specified address location. There are no restrictions on address location access. When M[7:0] is any value other than AXH, the device expects the next instruction initiated to be a command instruction. To reset/exit the Set Mode configuration, execute the Reset Quad I/O command, FFH. See Figure 5-15 for the SPI Dual I/O Read sequence when M[7:0] = AXH. DS C-page Microchip Technology Inc.

23 FIGURE 5-14: SPI DUAL I/O READ SEQUENCE MODE SIO0 BBH SIO A[23:16] A[15:8] A[7:0] M[7:0] (cont ) (cont ) SIO0(cont ) SIO1(cont ) I/O Switches from Input to Output MSB MSB MSB MSB Byte 0 Byte 1 Byte 2 Byte 3 Note: MSN= F53.1 FIGURE 5-15: BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH MODE SIO0 6 I/O Switch SIO1 MSB MSB A[23:16] A[15:8] A[7:0] M[7:0] (cont ) (cont ) SIO0(cont ) SIO1(cont ) I/O Switches from Input to Output MSB MSB MSB MSB Byte 0 Byte 1 Byte 2 Byte 3 Note: MSN= Most F Microchip Technology Inc. DS C-page 23

24 5.14 JEDEC-ID Read (SPI Protocol) Using traditional SPI protocol, the JEDEC-ID Read instruction identifies the device as SST26WF040B/ 040BA and SST26WF080B/080BA and the manufacturer as Microchip. To execute a JECEC-ID operation the host drives low then sends the JEDEC-ID command cycle (9FH). Immediately following the command cycle, SST26WF040B/040BA and SST26WF080B/080BA outputs data on the falling edge of the signal. The data output stream is continuous until terminated by a low-to-high transition on. The device outputs three bytes of data: manufacturer, device type, and device ID, see Table 5-4. See Figure 5-16 for instruction sequence. TABLE 5-4: DEVICE ID DATA OUTPUT Product Manufacturer ID (Byte 1) SST26WF040B and SST26WF080B Device ID Device Type (Byte 2) Device ID (Byte 3) BFH 26H 58H (SST26WF080B) 54H (SST26WF040B) FIGURE 5-16: JEDEC-ID SEQUENCE (SPI MODE) MODE SI 9F SO HIGH IMPEDANCE MSB BF MSB 26 Device ID F Read Quad J-ID Read (SQI Protocol) The Read Quad J-ID Read instruction identifies the device as SST26WF040B/040BA and SST26WF080B/ 080BA and manufacturer as Microchip. To execute a Quad J-ID operation the host drives low and then sends the Quad J-ID command cycle (AFH). Each cycle is two nibbles (clocks) long, most significant nibble first. Immediately following the command cycle, and one dummy cycle, SST26WF040B/040BA and SST26WF080B/080BA outputs data on the falling edge of the signal. The data output stream is continuous until terminated by a low-to-high transition of. The device outputs three bytes of data: manufacturer, device type, and device ID, see Table 5-4. See Figure 5-17 for instruction sequence. FIGURE 5-17: SIO(3:0) MODE 3 QUAD J-ID READ SEQUENCE Dummy MSN BFH LSN C0 C1 X X H0 L0 H1 L1 H2 L2 H0 L0 H1 L1 HN LN 26H N Device ID BFH 26H N F55.0 Note: DS C-page Microchip Technology Inc.

25 5.16 Serial Flash Discoverable Parameters (SFDP) The Serial Flash Discoverable Parameters (SFDP) contain information describing the characteristics of the device. This allows device-independent, JEDEC IDindependent, and forward/backward compatible software support for all future Serial Flash device families. See Table 11-1 on page 60 for address and data values. Initiate SFDP by executing an 8-bit command, 5AH, followed by address bits A[23-0] and a dummy byte. must remain active low for the duration of the SFDP cycle. For the SFDP sequence, see Figure FIGURE 5-18: SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE MODE SI 5A ADD. ADD. ADD. X SO HIGH IMPEDANCE N N+1 N+2 N+3 N+4 D OUT D OUT D OUT D OUT D OUT MSB F Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to 1, but it does not change a protected memory area. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. To execute a Sector-Erase operation, the host drives low, then sends the Sector Erase command cycle (20H) and three address cycles, and then drives high. Address bits [A MS :A 12 ] (A MS = Most Significant Address) determine the sector address (SA X ); the remaining address bits can be V IL or V IH. To identify the completion of the internal, self-timed, Write operation, poll the BUSY bit in the Status register, or wait T SE. See Figures 5-19 and 5-20 for the Sector-Erase sequence. FIGURE 5-19: 4 KBYTE SECTOR-ERASE SEQUENCE SQI MODE (C[1:0] = 20 H) MODE SIO(3:0) Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0]=20H C1 C0 A5 A4 A3 A2 MSN LSN A1 A F07.0 FIGURE 5-20: 4 KBYTE SECTOR-ERASE SEQUENCE (SPI) MODE SI MSB 20 ADD. MSB ADD. ADD. SO HIGH IMPEDANCE F Microchip Technology Inc. DS C-page 25

26 5.18 Block-Erase The Block-Erase instruction clears all bits in the selected block to 1. Block sizes can be 8 KByte, 32 KByte or 64 KByte depending on address, see Figure 3-1, Memory Map, for details. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any write operation, execute the WREN instruction. Keep active low for the duration of any command sequence. To execute a Block-Erase operation, the host drives low then sends the Block-Erase command cycle (D8H), three address cycles, then drives high. Address bits A MS -A 13 determine the block address (BA X ); the remaining address bits can be V IL or V IH. For 32 KByte blocks, A 14 :A 13 can be V IL or V IH ; for 64 KByte blocks, A 15 :A 13 can be V IL or V IH. Poll the BUSY bit in the Status register, or wait T BE, for the completion of the internal, self-timed, Block-Erase operation. See Figures 5-21 and 5-22 for the Block-Erase sequence. FIGURE 5-21: BLOCK-ERASE SEQUENCE (SQI) MODE SIO(3:0) C1 C0 A5 A4 A3 A2 MSN LSN A1 A F08.0 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble C[1:0] = D8H FIGURE 5-22: BLOCK-ERASE SEQUENCE (SPI) MODE SI MSB D8 ADDR MSB ADDR ADDR SO HIGH IMPEDANCE F58.0 DS C-page Microchip Technology Inc.

27 5.19 Chip-Erase The Chip-Erase instruction clears all bits in the device to 1. The Chip-Erase instruction is ignored if any of the memory area is protected. Prior to any write operation, execute the WREN instruction. To execute a Chip-Erase operation, the host drives low, sends the Chip-Erase command cycle (C7H), then drives high. Poll the BUSY bit in the Status register, or wait T SCE, for the completion of the internal, self-timed, Write operation. See Figures 5-23 and 5-24 for the Chip Erase sequence. FIGURE 5-23: CHIP-ERASE SEQUENCE (SQI) MODE SIO(3:0) C1 C F09.1 Note: C[1:0] = C7H FIGURE 5-24: CHIP-ERASE SEQUENCE (SPI) MODE SI MSB C7 SO HIGH IMPEDANCE F Microchip Technology Inc. DS C-page 27

28 5.20 Page-Program The Page-Program instruction programs up to 256 Bytes of data in the memory, and supports both SPI and SQI protocols. The data for the selected page address must be in the erased state (FFH) before initiating the Page-Program operation. A Page-Program applied to a protected memory area will be ignored. Prior to the program operation, execute the WREN instruction. To execute a Page-Program operation, the host drives low then sends the Page Program command cycle (02H), three address cycles followed by the data to be programmed, then drives high. The programmed data must be between 1 to 256 Bytes and in whole Byte increments; sending less than a full Byte will cause the partial Byte to be ignored. Poll the BUSY bit in the Status register, or wait T PP, for the completion of the internal, self-timed, Block-Erase operation. See Figures 5-25 and 5-26 for the Page-Program sequence. When executing Page-Program, the memory range for the SST26WF040B/040BA and SST26WF080B/ 080BA is divided into 256 Byte page boundaries. The device handles shifting of more than 256 Bytes of data by maintaining the last 256 Bytes of data as the correct data to be programmed. If the target address for the Page-Program instruction is not the beginning of the page boundary (A[7:0] are not all zero), and the number of bytes of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page. FIGURE 5-25: PAGE-PROGRAM SEQUENCE (SQI) MODE SIO(3:0) C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 HN LN MSN LSN Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 255 Note: F10.1 FIGURE 5-26: PAGE-PROGRAM SEQUENCE (SPI) MODE SI MSB 02 ADD. LSB MSB ADD. ADD. Data Byte 0 LSB MSB LSB SO HIGH IMPEDANCE (cont ) (cont ) SI(cont ) Data Byte 1 Data Byte 2 Data Byte 255 MSB LSB MSB LSB MSB LSB Note: C[1:0] = 02H SO(cont ) HIGH IMPEDANCE F60.1 DS C-page Microchip Technology Inc.

29 5.21 SPI Quad Page-Program The SPI Quad Page-Program instruction programs up to 256 Bytes of data in the memory. The data for the selected page address must be in the erased state (FFH) before initiating the SPI Quad Page-Program operation. A SPI Quad Page-Program applied to a protected memory area will be ignored. SST26WF040B and SST26WF080B requires the ICO bit in the configuration register to be set to 1 prior to executing the command.prior to the program operation, execute the WREN instruction. To execute a SPI Quad Page-Program operation, the host drives low then sends the SPI Quad Page- Program command cycle (32H), three address cycles followed by the data to be programmed, then drives high. The programmed data must be between 1 to 256 Bytes and in whole Byte increments. The command cycle is eight clocks long, the address and data cycles are each two clocks long, most significant bit first. Poll the BUSY bit in the Status register, or wait T PP, for the completion of the internal, self-timed, Write operation.see Figure When executing SPI Quad Page-Program, the memory range for the SST26WF040B/040BA and SST26WF080B/080BA is divided into 256 Byte page boundaries. The device handles shifting of more than 256 Bytes of data by maintaining the last 256 Bytes of data as the correct data to be programmed. If the target address for the SPI Quad Page-Program instruction is not the beginning of the page boundary (A[7:0] are not all zero), and the of bytes of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page. FIGURE 5-27: SPI QUAD PAGE-PROGRAM SEQUENCE MODE SIO0 32H A20A16A12 A8 A4 A0 b4 b0 b4 b0 b4 b0 SIO1 A21A17A13 A9 A5 A1 b5 b1 b5 b1 b5 b1 SIO2 A22A18A14A10A6 A2 b6 b2 b6 b2 b6 b2 MSN LSN SIO3 A23A19A15 A11 A7 A3 b7 b3 b7 b3 Address Data Byte 0 Data Byte 1 b7 b3 Data Byte F Write-Suspend and Write-Resume Write-Suspend allows the interruption of Sector-Erase, Block-Erase, SPI Quad Page-Program, or Page-Program operations in order to erase, program, or read data in another portion of memory. The original operation can be continued with the Write-Resume command. This operation is supported in both SQI and SPI protocols. Only one write operation can be suspended at a time; if an operation is already suspended, the device will ignore the Write-Suspend command. Write-Suspend during Chip-Erase is ignored; Chip-Erase is not a valid command while a write is suspended. The Write- Resume command is ignored until any write operation (Program or Erase) initiated during the Write-Suspend is complete. The device requires a minimum of 500 µs between each Write-Suspend command Write-Suspend During Sector- Erase or Block-Erase Issuing a Write-Suspend instruction during Sector- Erase or Block-Erase allows the host to program or read any sector that was not being erased. The device will ignore any programming commands pointing to the suspended sector(s). Any attempt to read from the suspended sector(s) will output unknown data because the Sector- or Block-Erase will be incomplete. To execute a Write-Suspend operation, the host drives low, sends the Write Suspend command cycle (B0H), then drives high. The Status register indicates that the erase has been suspended by changing the WSE bit from 0 to 1, but the device will not accept another command until it is ready. To determine when the device will accept a new command, poll the BUSY bit in the Status register or wait T WS Microchip Technology Inc. DS C-page 29

30 5.24 Write Suspend During Page Programming or SPI Quad Page Programming Issuing a Write-Suspend instruction during Page Programming allows the host to erase or read any sector that is not being programmed. Erase commands pointing to the suspended sector(s) will be ignored. Any attempt to read from the suspended page will output unknown data because the program will be incomplete. To execute a Write Suspend operation, the host drives low, sends the Write Suspend command cycle (B0H), then drives high. The Status register indicates that the programming has been suspended by changing the WSP bit from 0 to 1, but the device will not accept another command until it is ready. To determine when the device will accept a new command, poll the BUSY bit in the Status register or wait T WS Write-Resume Write-Resume restarts a Write command that was suspended, and changes the suspend status bit in the Status register (WSE or WSP) back to 0. To execute a Write-Resume operation, the host drives low, sends the Write Resume command cycle (30H), then drives high. To determine if the internal, self-timed Write operation completed, poll the BUSY bit in the Status register, or wait the specified time T SE, T BE or T PP for Sector-Erase, Block-Erase, or Page-Programming, respectively. The total write time before suspend and after resume will not exceed the uninterrupted write times T SE, T BE or T PP Read Security ID The Read Security ID operation is supported in both SPI and SQI modes. To execute a Read Security ID (SID) operation in SPI mode, the host drives low, sends the Read Security ID command cycle (88H), two address cycles, and then one dummy cycle. To execute TABLE 5-5: PROGRAM SECURITY ID Program Security ID Unique ID Pre-Programmed at factory User Programmable a Read Security ID operation in SQI mode, the host drives low and then sends the Read Security ID command, two address cycles, and three dummy cycles. After the dummy cycles, the device outputs data on the falling edge of the signal, starting from the specified address location. The data output stream is continuous through all SID addresses until terminated by a low-to-high transition on. See Table 5-5 for the Security ID address range Program Security ID The Program Security ID instruction programs one to 2040 Bytes of data in the user-programmable, Security ID space. This Security ID space is one-time programmable (OTP). The device ignores a Program Security ID instruction pointing to an invalid or protected address, see Table 5-5. Prior to the program operation, execute WREN. To execute a Program SID operation, the host drives low, sends the Program Security ID command cycle (A5H), two address cycles, the data to be programmed, then drives high. The programmed data must be between 1 to 256 Bytes and in whole Byte increments. The device handles shifting of more than 256 Bytes of data by maintaining the last 256 Bytes of data as the correct data to be programmed. If the target address for the Program Security ID instruction is not the beginning of the page boundary, and the number of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page. The Program Security ID operation is supported in both SPI and SQI mode. To determine the completion of the internal, self-timed Program SID operation, poll the BUSY bit in the software status register, or wait T PSID for the completion of the internal self-timed Program Security ID operation. Address Range H 0008H 07FFH 5.28 Lockout Security ID The Lockout Security ID instruction prevents any future changes to the Security ID, and is supported in both SPI and SQI modes. Prior to the operation, execute WREN. To execute a Lockout SID, the host drives low, sends the Lockout Security ID command cycle (85H), then drives high. Poll the BUSY bit in the software status register, or wait T PSID, for the completion of the Lockout Security ID operation. DS C-page Microchip Technology Inc.

31 5.29 Read-Status Register (RDSR) and Read-Configuration Register (RDCR) The Read-Status Register (RDSR) and Read Configuration Register (RDCR) commands output the contents of the Status and Configuration registers. These commands function in both SPI and SQI modes. The Status register may be read at any time, even during a Write operation. When a Write is in progress, poll the BUSY bit before sending any new commands to assure that the new commands are properly received by the device. To Read the Status or Configuration registers, the host drives low, then sends the Read-Status-Register command cycle (05H) or the Read Configuration Register command (35H). A dummy cycle is required in SQI mode. Immediately after the command cycle, the device outputs data on the falling edge of the signal. The data output stream continues until terminated by a low-to-high transition on. See Figures 5-28 and 5-29 for the RDSR instruction sequence. FIGURE 5-28: READ-STATUS-REGISTER AND READ CONFIGURATION REGISTER SEQUENCE (SQI) MODE 3 0 SIO(3:0) C1 C MSN LSN X X H0 L0 H0 L0 H0 L0 Dummy Status Byte Status Byte Status Byte Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, C[1:0]=05H or 35H F11.0 FIGURE 5-29: READ-STATUS-REGISTER AND READ CONFIGURATION REGISTER SEQUENCE (SPI) MODE SI SO MSB 05 or 35H HIGH IMPEDANCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status or Configuration Register Out F Microchip Technology Inc. DS C-page 31

32 5.30 Write-Status Register (WRSR) The Write-Status Register (WRSR) command writes new values to the Status register. To execute a Write- Status Register operation, the host drives low, then sends the Write-Status Register command cycle (01H), two cycles of data, and then drives high. The first cycle of data points to the Status register, the second points to the Configuration register. See Figures 5-30 and FIGURE 5-30: WRITE-STATUS-REGISTER AND WRITE CONFIGURATION REGISTER SEQUENCE (SQI) MODE SIO[3:0] MSN LSN C1 C0 H0 L0 H0 L0 Command Status Byte Configuration F63.1 Note: MSN = Most Significant Nibble; LSN = Least FIGURE 5-31: WRITE-STATUS-REGISTER AND WRITE CONFIGURATION REGISTER SEQUENCE (SPI) MODE MODE SI SO MSB MSB HIGH IMPEDANCE STATUS REGISTER MSB CONFIGURATION REGISTER MSB Note: XX = Don t Care F64.1 DS C-page Microchip Technology Inc.

33 5.31 Write-Enable (WREN) The Write Enable (WREN) instruction sets the Write- Enable-Latch bit in the Status register to 1, allowing Write operations to occur. The WREN instruction must be executed prior to any of the following operations: Sector Erase, Block Erase, Chip Erase, Page Program, Program Security ID, Lockout Security ID, Write Block- Protection Register, Lock-Down Block-Protection Register, and Non-Volatile Write-Lock Lock-Down Register, SPI Quad Page Program, and Write Status Register. To execute a Write Enable the host drives low then sends the Write Enable command cycle (06H) then drives high. See Figures 5-32 and 5-33 for the WREN instruction sequence. See Figures 5-32 and 5-33 for the WREN instruction sequence. FIGURE 5-32: WRITE-ENABLE SEQUENCE (SQI) 5.32 Write-Disable (WRDI) The Write-Disable (WRDI) instruction sets the Write- Enable-Latch bit in the Status register to 0, preventing Write operations. The WRDI instruction is ignored during any internal write operations. Any Write operation started before executing WRDI will complete. Drive high before executing WRDI. To execute a Write-Disable, the host drives low, sends the Write Disable command cycle (04H), then drives high. See Figures 5-34 and FIGURE 5-34: WRITE-DISABLE (WRDI) SEQUENCE (SQI) MODE SIO[3:0] MODE F12.1 SIO(3:0) FIGURE 5-35: F33.1 WRITE-DISABLE (WRDI) SEQUENCE (SPI) FIGURE 5-33: WRITE-ENABLE SEQUENCE (SPI) MODE MODE SI SO 04 MSB HIGH IMPEDANCE F19.0 SI MSB 06 SO HIGH IMPEDANCE F Microchip Technology Inc. DS C-page 33

34 5.33 Read Block-Protection Register (RBPR) The Read Block-Protection Register instruction outputs the Block-Protection register data which determines the protection status. To execute a Read Block-Protection Register operation, the host drives low, and then sends the Read Block-Protection Register command cycle (72H). A dummy cycle is required in SQI mode. After the command cycle, the device outputs data on the falling edge of the signal starting with the most significant nibble, see Table 5-6 for definitions of each bit in the Block-Protection register. The RBPR command does not wrap around. After all data has been output, the device will output 0H until terminated by a low-to-high transition on. Figures 5-36 and FIGURE 5-36: READ BLOCK-PROTECTION REGISTER SEQUENCE (SQI) MODE SIO[3:0] C1 C0 X X H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 HN LN MSN LSN BPR [m:m-7] BPR [7:0] F34.2 Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble Block-Protection Register (BPR) m = 23 for SST26WF040B/040BA, m = 32 for SST26WF080B/080BA FIGURE 5-37: READ BLOCK-PROTECTION REGISTER SEQUENCE (SPI) MODE SIO0 SIO 72H OP Code Data Byte 0 Data Byte 1 Data Byte 2 Data Byte N F65.1 DS C-page Microchip Technology Inc.

35 5.34 Write Block-Protection Register (WBPR) The Write Block-Protection Register (WBPR) command changes the Block-Protection register data to indicate the protection status. Execute WREN before executing WBPR. To execute a Write Block-Protection Register operation the host drives low, sends the Write Block-Protection Register command cycle (42H), sends six cycles of data, and finally drives high. Data input must be most significant nibble first. See Table 5-6 for definitions of each bit in the Block-Protection register. See Figures 5-38 and FIGURE 5-38: WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SQI) MODE Note: SIO(3:0) C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 MSN LSN HN LN BPR [m:m-7] BPR [7:0] F35.1 MSN = Most Significant Nibble, LSN = Least Significant Nibble Block-Protection Register (BPR) m = 23 for SST26WF040B/040BA, m = 32 for SST26WF080B/080BA FIGURE 5-39: WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SPI) SI MODE OP Code 42H Data Byte0 Data Byte1 Data Byte2 Data ByteN SO Note: C[1:0]=42H F Microchip Technology Inc. DS C-page 35

36 5.35 Lock-Down Block-Protection Register (LBPR) The Lock-Down Block-Protection Register instruction prevents changes to the Block-Protection register during device operation. Lock-Down resets after power cycling; this allows the Block-Protection register to be changed. Execute WREN before initiating the Lock- Down Block-Protection Register instruction. To execute a Lock-Down Block-Protection Register, the host drives low, then sends the Lock-Down Block- Protection Register command cycle (8DH), then drives high. FIGURE 5-40: N t SIO(3:0) C[1 0] 8DH LOCK-DOWN BLOCK- PROTECTION REGISTER (SQI) MODE C1 C F30.1 FIGURE 5-41: LOCK-DOWN BLOCK-PROTECTION REGISTER (SPI) MODE SIO0 8D SIO[3:1] F67.0 DS C-page Microchip Technology Inc.

37 5.36 Non-Volatile Write-Lock Lock- Down Register (nvwldr) The Non-Volatile Write-Lock Lock-Down Register (nvwldr) instruction controls the ability to change the Write-Lock bits in the Block-Protection register. Execute WREN before initiating the nvwldr instruction. To execute nvwldr, the host drives low, then sends the nvwldr command cycle (E8H), followed by six cycles of data, and then drives high. After goes high, the non-volatile bits are programmed and the programming time-out must complete before any additional commands, other than Read Status Register, can be entered. Poll the BUSY bit in the Status register, or wait T PP, for the completion of the internal, self-timed, Write operation. Data inputs must be most significant bit(s) first. FIGURE 5-42: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI) MODE Note: SIO(3:0) E 8 H0 L0 MSN LSN H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 HN LN nvwldr[47:40] BPR [7:0] M SN= Most Significant Nibble; LSN = Least Significant Nibble F36.0 FIGURE 5-43: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI) SI MODE OP Code E8H Data Byte0 Data Byte1 Data Byte2 Data ByteN SO F Microchip Technology Inc. DS C-page 37

38 5.37 Global Block-Protection Unlock (ULBPR) The Global Block-Protection Unlock (ULBPR) instruction clears all write-protection bits in the Block-Protection register, except for those bits that have been locked down with the nvwldr command. Execute WREN before initiating the ULBPR instruction. To execute a ULBPR instruction, the host drives low, then sends the ULBPR command cycle (98H), and then drives high. FIGURE 5-44: SIO(3:0) Note: C[1:0]=98H GLOBAL BLOCK- PROTECTION UNLOCK (SQI) MODE C1 C F20.1 FIGURE 5-45: GLOBAL BLOCK-PROTECTION UNLOCK (SPI) MODE SIO0 98 SIO[3:1] F68.0 TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26WF040B/040BA 1 BPR Bits Read Lock Write Lock/nVWLDR 2 Address Range Protected Block Size E000H-08FFFFH 8 KByte C000H-07DFFFH 8 KByte A000H-07BFFFH 8 KByte H - 079FFFH 8 KByte H - 007FFFH 8 KByte H - 005FFFH 8 KByte H - 003FFFH 8 KByte H - 001FFFH 8 KByte H - 077FFFH 32 KByte H - 00FFFFH 32 KByte H - 06FFFFH 64 KByte H - 05FFFFH 64 KByte H - 04FFFFH 64 KByte H - 03FFFFH 64 KByte H - 02FFFFH 64 KByte H - 01FFFFH 64 KByte 1. The default state after a power-on reset is write-protected BPR[23:0] = 5555 FF 2. nvwldr bits are one-time-programmable. Once a WLLDR bit is set, the protection state of that particular block is permanently write-locked. DS C-page Microchip Technology Inc.

39 TABLE 5-7: BLOCK-PROTECTION REGISTER FOR SST26WF080B/080BA 1 BPR Bits Read Lock Write Lock/nVWLDR 2 Address Range Protected Block Size FE000H 0FFFFFH 8 KByte FC000H - 0FDFFFH 8 KByte FA000H - 0FBFFFH 8 KByte F8000H - 0F9FFFH 8 KByte H - 007FFFH 8 KByte H - 005FFFH 8 KByte H - 003FFFH 8 KByte H - 001FFFH 8 KByte 15 0F0000H - 0F7FFFH 32 KByte H - 00FFFFH 32 KByte 13 0E0000H - 0EFFFFH 64 KByte 12 0D0000H - 0DFFFFH 64 KByte 11 0C0000H - 0CFFFFH 64 KByte 10 0B0000H - 0BFFFFH 64 KByte 9 0A0000H - 0AFFFFH 64 KByte H - 09FFFFH 64 KByte H - 08FFFFH 64 KByte H - 07FFFFH 64 KByte H - 06FFFFH 64 KByte H - 05FFFFH 64 KByte H - 04FFFFH 64 KByte H - 03FFFFH 64 KByte H - 02FFFFH 64 KByte H - 01FFFFH 64 KByte 1. The default state after a power-on reset is write-protected BPR[31:0] = 5555 FFFF 2. nvwldr bits are one-time-programmable. Once a WLLDR bit is set, the protection state of that particular block is permanently write-locked Microchip Technology Inc. DS C-page 39

40 5.38 Deep Power-Down The Deep Power-down (DPD) instruction puts the device in the lowest power consumption mode the Deep Power-down mode. The Deep Power-down instruction is ignored during an internal write operation. While the device is in Deep Power-down mode, all instructions will be ignored except for the Release Deep Power-down instruction. Enter Deep Power-down mode by initiating the Deep Power-down (DPD) instruction (B9H) while driving low. must be driven high before executing the DPD instruction. After is driven high, it requires a delay of T DPD before the standby current I SB is reduced to deep power-down current I DPD. See Table 5-8 for Deep Power-down timing. If the device is busy performing an internal erase or program operation, initiating a Deep Power-down instruction will not placed the device in Deep Power-down mode. See Figures 5-46 and 5-47 for the DPD instruction sequence. TABLE 5-8: DEEP POWER-DOWN Symbol Parameter Min Max Units TDPD High to Deep Power-down 3 µs TSBR High to Standby Mode 10 µs FIGURE 5-46: DEEP POWER-DOWN (DPD) SEQUENCE (SQI) MODE T DPD SIO(3:0) B 9 MSN LSN Standby Mode Note: MSN= Most Significant Nibble; LSN = Least Significant Nibble Deep Power-Down Mode F100.0 FIGURE 5-47: DEEP POWER-DOWN (DPD) (SPI) T DPD MODE SI MSB B9 SO HIGH IMPEDANCE Standby Mode Deep Power-Down Mode F101.0 DS C-page Microchip Technology Inc.

41 5.39 Release from Deep Power-Down and Read ID Release from Deep Power-Down (RDPD) and Read ID instruction exits Deep Power-down mode. To exit Deep Power down mode, execute the RDPD. During this command, the host drives low, then sends the Deep Power-Down command cycle (ABH), and then drives high. The device will return to Standby mode and be ready for the next instruction after T SBR. To execute RDPD and read the Device ID, the host drives low then sends the Deep Power-Down command cycle (ABH), three dummy clock cycles, and then drives high. The device outputs the Device ID on the falling edge of the signal following the dummy cycles. The data output stream is continuous until terminated by a low-to-high transition on CE, and will return to Standby mode and be ready for the next instruction after T SBR. See Figures 5-48 and 5-49 for the command sequence. FIGURE 5-48: RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE (SQI) T SBR Note: C[1:0]=A BH SIO[3:0] MODE 3 0 Op Code C1 C0 1 X X X X X X D1 D0 MSN LSN Device ID Deep Power-Down Mode Standby Mode F102.0 FIGURE 5-49: RELEASE FROM DEEP POWER-DOWN (RDPD) AND READ ID SEQUENCE (SPI) T SBR SIO[3:0] MODE Op Code AB XX XX XX Device ID Deep Power-Down Mode Standby Mode F Microchip Technology Inc. DS C-page 41

42 6.0 ELECTRICAL SPECIFICATIONS Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias C to +125 C Storage Temperature C to +150 C D. C. Voltage on Any Pin to Ground Potential V to V DD +0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential V to V DD +2.0V Package Power Dissipation Capability (T A = 25 C) W Surface Mount Solder Reflow Temperature C for 10 seconds Output Short Circuit Current ma 1. Output shorted for no more than one second. No more than one output shorted at a time. TABLE 6-1: OPERATING RANGE Range Ambient Temp V DD Industrial -40 C to +85 C V TABLE 6-2: AC CONDITIONS OF TEST 1 Input Rise/Fall Time 3ns Output Load C L = 30 pf 1. See Figure Power-Up Specifications All functionalities and DC specifications are specified for a V DD ramp rate of greater than 1V per 100 ms (0V to 3.0V in less than 300 ms). When V DD drops from the operating voltage to below the minimum V DD threshold at power-down, all operations are disabled and the device does not respond to commands. Data corruption may result if a power-down occurs while a Write-Registers, program, or erase operation is in progress. See Figure 6-2. TABLE 6-3: RECOMMENDED SYSTEM POWER-UP/DOWN TIMINGS Symbol Parameter Minimum Max Units Condition 1 T PU-READ V DD Min to Read Operation 100 µs 1 T PU-WRITE V DD Min to Write Operation 100 µs 1 T PD Power-down Duration 100 ms V OFF V DD off time 0.3 V 0V recommended 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. DS C-page Microchip Technology Inc.

43 FIGURE 6-1: POWER-UP TIMING DIAGRAM V DD V DD Max Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. V DD Min T PU-READ T PU-WRITE Device fully accessible Time F27.0 FIGURE 6-2: POWER-DOWN AND VOLTAGE DROP DIAGRAM V DD V DD Max No Device Access Allowed V DD Min T PU Device Access Allowed T PD Time F Microchip Technology Inc. DS C-page 43

44 7.0 DC CHARACTERISTICS TABLE 7-1: DC OPERATING CHARACTERISTICS (V DD = 1.65V 1.95V) Limits Symbol Parameter Min Typ Max Units Test Conditions I DDR1 Read Current 8 10 ma V DD= V DD Max, =0.1 V DD /0.9 V MHz, SO=open I DDR2 Read Current 20 ma V DD = V DD Max, =0.1 V DD /0.9 V MHz, SO=open I DDW Program and Erase Current 25 ma V DD Max I SB Standby Current µa =V DD, V IN =V DD or V SS I DPD Deep Power-down Current µa =V DD, V IN =V DD or V SS I LI Input Leakage Current 1 µa V IN =GND to V DD, V DD =V DD Max I LO Output Leakage Current 1 µa V OUT =GND to V DD, V DD =V DD Max V IL Input Low Voltage 0.3 V V DD =V DD Min V IH Input High Voltage 0.7 V DD V V DD =V DD Max V OL Output Low Voltage 0.2 V I OL =100 µa, V DD =V DD Min V OH Output High Voltage V DD -0.2 V I OH =-100 µa, V DD =V DD Min TABLE 7-2: CAPACITANCE (TA = 25 C, F=1 MHZ, OTHER PINS OPEN) Parameter Description Test Condition Maximum 1 C OUT Output Pin Capacitance V OUT = 0V 8 pf 1 C IN Input Capacitance V IN = 0V 6 pf 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7-3: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method 1 N END Endurance 100,000 Cycles JEDEC Standard A117 1 T DR Data Retention 100 Years JEDEC Standard A103 I 1 LTH Latch Up I DD ma JEDEC Standard This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7-4: WRITE TIMING PARAMETERS (V DD = 1.65V 1.95V) Symbol Parameter Minimum Maximum Units T SE Sector-Erase 25 ms T BE Block-Erase 25 ms T SCE Chip-Erase 50 ms T PP Page-Program 1.5 ms T PSID Program Security-ID 1.5 ms T WS Write-Suspend Latency 25 µs T Wpen Write-Protection Enable Bit Latency 25 ms DS C-page Microchip Technology Inc.

45 8.0 AC CHARACTERISTICS TABLE 8-1: AC OPERATING CHARACTERISTICS (V DD = 1.65V 1.95V) Limits - 40 MHz Limits - 80 MHz Limits MHz Symbol Parameter Min Max Min Max Min Max Units F CLK Serial Clock Frequency MHz T CLK Serial Clock Period ns T H Serial Clock High Time ns T L Serial Clock Low Time ns 1 T R Serial Clock Rise Time (slew rate) V/ns T 1 F Serial Clock Fall Time (slew rate) V/ns 2 T CES Active Setup Time ns 2 T CEH Active Hold Time ns T 2 CHS Not Active Setup Time ns 2 T CHH Not Active Hold Time ns T CPH High Time ns T CHZ High to High-Z Output ns T CLZ Low to Low-Z Output ns T HLS HOLD# Low Setup Time ns T HHS HOLD# High Setup Time ns T HLH HOLD# Low Hold Time ns T HHH HOLD# High Hold Time ns T HZ HOLD# Low-to-High-Z Output ns T LZ HOLD# High-to-Low-Z Output ns T DS Data In Setup Time ns T DH Data In Hold Time ns T OH Output Hold from Change ns T V Output Valid from 8/5 3 8/5 3 8/5 3 ns 1. Maximum Rise and Fall time may be limited by T H and T L requirements 2. Relative to pf/10 pf FIGURE 8-1: HOLD TIMING DIAGRAM T HHH T HLS T HHS T HZ T HLH TLZ SO SI HOLD# F Microchip Technology Inc. DS C-page 45

46 FIGURE 8-2: SERIAL INPUT TIMING DIAGRAM T CPH T CHH TCES T CEH TCHS T F T DS T DH T R SIO[3:0] MSB LSB F105.0 FIGURE 8-3: SERIAL OUTPUT TIMING DIAGRAM T H T L T CLZ T OH T CHZ SIO[3:0] MSB LSB T V F106.0 TABLE 8-2: RESET TIMING PARAMETERS T R(i) Parameter Minimum Maximum Units T R(o) Reset to Read (non-data operation) 20 ns T R(p) Reset Recovery from Program or Suspend 100 µs T R(e) Reset Recovery from Erase 1 ms FIGURE 8-4: RESET TIMING DIAGRAM T CPH CLK MODE 3 MODE 3 MODE 3 SIO(3:0) C1 C0 C3 C F14.0 Note: C[1:0] = 66H; C[3:2] = 99H DS C-page Microchip Technology Inc.

47 FIGURE 8-5: AC INPUT/OUTPUT REFERENCE WAVEFORMS V IHT V HT V HT V ILT INPUT V LT REFERENCE POINTS V LT OUTPUT F28.0 AC test inputs are driven at V IHT (0.9V DD ) for a logic 1 and V ILT (0.1V DD ) for a logic 0. Measurement reference points for inputs and outputs are V HT (0.5V DD ) and V LT (0.5V DD ). Input rise and fall times (10% 90%) are <3 ns. Note: V HT - V HIGH Test V LT - V LOW Test V IHT - V INPUT HIGH Test V ILT - V INPUT LOW Test Microchip Technology Inc. DS C-page 47

48 9.0 PACKAGING DIAGRAMS 8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at (DATUM A) N D A B (DATUM B) E NOTE 1 2X 0.15 C 2X 0.15 C 1 2 TOP VIEW SEATING PLANE C A1 A 0.10 C A3 SIDE VIEW 0.08 C 0.10 C A B D2 e C A B NOTE 1 E2 K N SEE DETAIL A BOTTOM VIEW 8 X b 0.10 C A B 0.05 C Microchip Technology Drawing C04-210B Sheet 1 of 2 DS C-page Microchip Technology Inc.

49 8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at (DATUM A) L e e/2 DETAIL A Notes: Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Terminals N 8 Pitch Overall Height Standoff e A A BSC Terminal Thickness A REF Overall Width Exposed Pad Width Overall Length Exposed Pad Length D D2 E E BSC 4.00 BSC 6.00 BSC 3.40 BSC Terminal Width b Terminal Length L Terminal-to-Exposed-Pad K Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-210B Sheet 2 of Microchip Technology Inc. DS C-page 49

50 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at D 2X 0.10 C A B N A NOTE 5 D E1 2 E 2 E1 E NOTE e B TOP VIEW NOTE 5 NX b 0.25 C A B D 0.10 C SEATING PLANE C A A1 A2 SIDE VIEW 8X 0.10 C h R0.13 h R0.13 H 0.23 SEE VIEW C VIEW A A L (L1) VIEW C Microchip Technology Drawing No. C SN Rev D Sheet 1 of 2 DS C-page Microchip Technology Inc.

51 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A Molded Package Thickness A Standoff A Overall Width E 6.00 BSC Molded Package Width E BSC Overall Length D 4.90 BSC Chamfer (Optional) h Foot Length L Footprint L REF Foot Angle 0-8 Lead Thickness c Lead Width b Mold Draft Angle Top 5-15 Mold Draft Angle Bottom 5-15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C SN Rev D Sheet 2 of Microchip Technology Inc. DS C-page 51

52 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] 8-Lead Plastic Ultra Thin Small Outline No Lead Package (PRX) - 2x3 mm Body [USON] [Also Note: called For the UDFN] most current package drawings, please see the Microchip Packaging Specification located at Note: For the most current package drawings, please see the Microchip Packaging Specification located at (DATUM A) N D A B (DATUM B) NOTE 1 E 2X C 0.20 C 2X 0.20 C 1 2 TOP VIEW SILK SCREEN SEATING PLANE C A E SIDE VIEW 1 2 D2 e 0.10 C Y C X C A B RECOMMENDED LAND PATTERN A1 NOTE 1 E2 Notes: Units Dimension Limits Contact Pitch E Contact Pad Spacing N C Contact Pad SEE Width DETAIL (X8) A X1 Contact Pad Length (X8) Y1 BOTTOM VIEW 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. MIN 0.10 C A B MILLIMETERS NOM MAX 1.27 BSC X b C A B 0.05 C Microchip Microchip Technology Technology Drawing Drawing C04-203C C SN [PRX] Sheet Rev 1 Bof 2 DS C-page Microchip Technology Inc.

53 8-Lead Plastic Ultra Thin Small Outline No Lead Package (PRX) - 2x3 mm Body [USON] [Also called UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at (DATUM A) N D A B (DATUM B) NOTE 1 E 2X 0.20 C 2X 0.20 C 1 2 TOP VIEW SEATING PLANE C A SIDE VIEW 0.10 C 0.08 C A1 1 2 D2 e 0.10 C A B NOTE 1 E C A B SEE DETAIL A N BOTTOM VIEW 8 X b 0.10 C A B 0.05 C Microchip Technology Drawing C04-203C [PRX] Sheet 1 of Microchip Technology Inc. DS C-page 53

54 8-Lead Plastic Ultra Thin Small Outline No Lead Package (PRX) - 2x3 mm Body [USON] [Also called UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at (DATUM A) L L3 e e/2 L1 DETAIL A Notes: Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Terminals N 8 Pitch Overall Height Standoff e A A BSC Overall Width Exposed Pad Width Overall Length Exposed Pad Length Terminal Width D D2 E E2 b BSC BSC Package Edge to Terminal Edge L Package Edge to Terminal Edge L Terminal Length L Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-203C [PRX] Sheet 2 of 2 DS C-page Microchip Technology Inc.

55 8-Lead Plastic Ultra Thin Small Outline No Lead Package (PRX) - 2x3 mm Body [USON] [Also called UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at C X2 E Y2 G X1 SILK SCREEN Y1 RECOMMENDED LAND PATTERN Notes: Units Dimension Limits MIN Terminal Pitch E Optional Center Pad Width Optional Center Pad Length X2 Y2 Terminal Pad Spacing C Terminal Pad Width (X8) X1 Terminal Pad Length (X8) Y1 Mininum Between Terminal Pads G 0.20 MILLIMETERS NOM 0.50 BSC Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. MAX Microchip Technology Drawing C B [PRX] Microchip Technology Inc. DS C-page 55

56 TABLE 9-1: REVISION HISTORY Revision Description Date A Initial release of data sheet Oct 2014 B Corrected document title on page 1. Oct 2014 Corrected an error in Table 10-1 on page 59 C Package drawing updates Nov 2017 DS C-page Microchip Technology Inc.

57 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Product Support Data sheets and errata, application notes and sample programs, design resources, user s guides and hardware support documents, latest software releases and archived software General Technical Support Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: CUSTOMER CHANGE NOTIFICATION SERVICE Microchip s customer notification service helps keep customers current on Microchip products. Subscribers will receive notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at Under Support, click on Customer Change Notification and follow the registration instructions Microchip Technology Inc. DS C-page 57

58 10.0 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X XXX X Device Device SST26WF040B = 4 Mbit, V, SQI Flash Memory WP#/Hold# pin Enable at power-up SST26WF040BA = 4 Mbit, V, SQI Flash Memory WP#/Hold# pin Disable at power-up SST26WF080B = 8 Mbit, V, SQI Flash Memory WP#/Hold# pin Enable at power-up SST26WF080BA = 8 Mbit, V, SQI Flash Memory WP#/Hold# pin Disable at power-up Tape and Reel Flag: Operating Frequency: Tape/Reel Indicator T Operating Frequency = Tape and Reel 104 = 104 MHz Temperature: I = -40 C to +85 C Temperature Package: MF = WDFN (6mm x 5mm Body), 8-contact SN = SOIC (150 mil Body), 8-contact NP = USON (2x3mm), 8-contact CS = Z-Scale (Chip Scale Package) 8-ball / XX Package Valid Combinations: SST26WF040B-104I/MF SST26WF040BT-104I/MF SST26WF040BA-104I/MF SST26WF040BAT-104I/MF SST26WF040B-104I/SN SST26WF040BT-104I/SN SST26WF040BA-104I/SN SST26WF040BAT-104I/SN SST26WF040B-104I/NP SST26WF040BT-104I/NP SST26WF040BA-104I/NP SST26WF040BAT-104I/NP SST26WF040BT-104I/CS SST26WF040BAT-104I/CS SST26WF080B-104I/MF SST26WF080BT-104I/MF SST26WF080BA-104I/MF SST26WF080BAT-104I/MF SST26WF080B-104I/SN SST26WF080BT-104I/SN SST26WF080BA-104I/SN SST26WF080BAT-104I/SN SST26WF080B-104I/NP SST26WF080BT-104I/NP SST26WF080BA-104I/NP SST26WF080BAT-104I/NP SST26WF080BT-104I/CS SST26WF080BAT-104I/CS DS C-page Microchip Technology Inc.

59 TABLE 10-1: PART MARKING Ordering Number SST26WF040B-104I/MF SST26WF040BA-104I/MF SST26WF040B-104I/SN SST26WF040BA-104I/SN SST26WF040B-104I/NP SST26WF040BA-104I/NP SST26WF040BT-104I/CS SST26WF080B-104I/MF SST26WF080BA-104I/MF SST26WF080B-104I/SN SST26WF080BA-104I/SN SST26WF080B-104I/NP SST26WF080BA-104I/NP SST26WF080BT-104I/CS Marking On Part 26WF040B-I/MF 26WF406B-I/MF 26WF040B-I/SN 26WF040B-I/SN 26WF040B-I/NP 26WF040B-I/NP W40B 26WF080B-I/MF 26WF080B-I/MF 26WF080B-I/SN 26WF080B-I/SN 26WF080B-I/NP 26WF080B-I/NP W80B Note: Due to intellectual property concerns, the 8-ball Chip Scale (Z-Scale ) package drawing is not included in this data sheet. Please contact Microchip Sales for more information Microchip Technology Inc. DS C-page 59

60 11.0 APPENDIX TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (1 OF 16) Address Bit Address Data Comments SFDP Header SFDP Header: 1 st DWORD 00H A7:A0 53H SFDP Signature 01H A15:A8 46H SFDP Signature= H 02H A23:A16 44H 03H A31:A24 50H SFDP Header: 2 nd DWORD 04H A7:A0 06H SFDP Minor Revision Number 05H A15:A8 01H SFDP Major Revision Number 06H A23:A16 02H Number of Parameter Headers (NPH)=3 07H A31:A24 FFH Unused. Contains FF and can not be changed. Parameter Headers JEDEC Flash Parameter Header: 1 st DWORD Parameter ID Least Significant Bit (LSB) Number. 08H A7:A0 00H When this field is set to 00H, it indicates a JEDEC-specified header. For vendor-specified headers, this field must be set to the vendor s manufacturer ID. 09H A15:A8 06H Parameter Table Minor Revision Number Minor revisions are either clarifications or changes that add parameters in existing Reserved locations. Minor revisions do NOT change overall structure of SFDP. Minor Revision starts at 00H. 0AH A23:A16 01H Parameter Table Major Revision Number Major revisions are changes that reorganize or add parameters to locations that are NOT currently Reserved. Major revisions would require code (BIOS/firmware) or hardware change to get previously defined discoverable parameters. Major Revision starts at 01H 0BH A31:A24 10H Parameter Table Length Number of DWORDs that are in the Parameter table JEDEC Flash Parameter Header: 2 nd DWORD 0CH A7:A0 30H Parameter Table Pointer (PTP) 0DH A15:A8 00H A 24-bit address that specifies the start of this header s Parameter table in the SFDP structure. The address must be DWORD-aligned. 0EH A23:A16 00H 0FH A31:A24 FFH Parameter ID Most Significant Bit (MSB) Number JEDEC Flash Parameter Header: 3 rd DWORD Parameter ID LSB Number 10H A7:A0 81H Sector map, function-specific table is assigned 81H 11H A15:A8 00H 12H A23:A16 01H Parameter Table Minor Revision Number Minor revisions are either clarifications or changes that add parameters in existing Reserved locations. Minor revisions do NOT change overall structure of SFDP. Minor Revision starts at 00H. Parameter Table Major Revision Number Major revisions are changes that reorganize or add parameters to locations that are NOT currently Reserved. Major revisions would require code (BIOS/firmware) or hardware change to get previously defined discoverable parameters. Major Revision starts at 01H DS C-page Microchip Technology Inc.

61 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (2 OF 16) Address Bit Address Data Comments 13H A31:A24 06H Parameter Table Length Number of DWORDs that are in the Parameter table JEDEC Flash Parameter Header: 4 th DWORD 14H A7:A0 00H Parameter Table Pointer (PTP) 15H A15:A8 01H This 24-bit address specifies the start of this header s Parameter Table in the SFDP structure. The address must be DWORD-aligned. 16H A23:A16 00H 17H A31:A24 FFH Parameter ID MSB Number. Microchip (Vendor) Parameter Header: 5 th DWORD 18H A7:A0 BFH ID Number Manufacture ID (vendor specified header) 19H A15:A8 00H Parameter Table Minor Revision Number 1AH A23:A16 01H Parameter Table major Revision Number, Revision 1.0 1BH A31:A24 18H Parameter Table Length, 24 Double Words Microchip (Vendor) Parameter Header: 6 th DWORD 1CH A7:A0 00H Parameter Table Pointer (PTP) 1DH A15:A8 02H This 24-bit address specifies the start of this header s Parameter Table in the SFDP structure. The address must be DWORD-aligned. 1EH A23:A16 00H 1FH A31:A24 01H Used to indicate bank number (vendor specific) JEDEC Flash Parameter Table JEDEC Flash Parameter Table: 1 st DWORD Block/Sector Erase Sizes 00: Reserved A1:A0 01: 4 KByte Erase 10: Reserved 11: Use this setting only if the 4 KByte erase is unavailable. Write Granularity 0: Single-byte programmable devices or buffer programmable A2 devices with buffer is less than 64 bytes (32 Words). 1: For buffer programmable devices when the buffer size is 64 30H FDH Bytes (32 Words) or larger. Volatile Status Register A3 0: Target flash has nonvolatile status bit. Write/Erase commands do not require status register to be written on every power on. 1: Target flash has volatile status bits Write Enable Opcode Select for Writing to Volatile Status Register A4 0: 0x50. Enables a status register write when bit 3 is set to 1. 1: 0x06 Enables a status register write when bit 3 is set to 1. A7:A5 Unused. Contains 111b and can not be changed 31H A15:A8 20H 4 KByte Erase Opcode Microchip Technology Inc. DS C-page 61

62 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (3 OF 16) Address Bit Address Data Comments Supports (1-1-2) Fast Read A16 0: (1-1-2) Fast Read NOT supported 1: (1-1-2) Fast Read supported Address Bytes Number of bytes used in addressing flash array read, write and erase 00: 3-Byte only addressing A18:A17 01: 3- or 4-Byte addressing (e.g. defaults to 3-Byte mode; enters 4- Byte mode on command) 10: 4-Byte only addressing 11: Reserved Supports Double Transfer Rate (DTR) Clocking Indicates the device supports some type of double transfer rate clocking. A19 0: DTR NOT supported 1: DTR Clocking supported 32H F1H Supports (1-2-2) Fast Read Device supports single input opcode, dual input address, and dual output A20 data Fast Read. 0: (1-2-2) Fast Read NOT supported. 1: (1-2-2) Fast Read supported. Supports (1-4-4) Fast Read Device supports single input opcode, quad input address, and quad A21 output data Fast Read 0: (1-4-4) Fast Read NOT supported. 1: (1-4-4) Fast Read supported. Supports (1-1-4) Fast Read Device supports single input opcode & address and quad output data A22 Fast Read. 0: (1-1-4) Fast Read NOT supported. 1: (1-1-4) Fast Read supported. A23 Unused. Contains 1 can not be changed 33H A31:A24 FFH Unused. Contains FF can not be changed JEDEC Flash Parameter Table: 2 nd DWORD 34H A7:A0 FFH Flash Memory Density 35H A15:A8 FFH SST26WF040B/040BA= 003FFFFFH 36H A23:A16 3FH 37H A31:A24 00H JEDEC Flash Parameter Table: 3 rd DWORD 38H A4:A0 A7:A5 44H 39H A15:A8 EBH (1-4-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input address phase instruction Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode Bits 010b: 2 dummy clocks (8 mode bits) are needed with a single input opcode, quad input address and quad output data Fast Read Instruction. (1-4-4) Fast Read Opcode Opcode for single input opcode, quad input address, and quad output data Fast Read. DS C-page Microchip Technology Inc.

63 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (4 OF 16) Address Bit Address Data Comments 3AH A20:A16 A23:A21 08H (1-1-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 01000b: 8 dummy bits are needed with a single input opcode & address and quad output data Fast Read Instruction (1-1-4) Fast Read Number of Mode Bits 000b: No mode bits are needed with a single input opcode & address and quad output data Fast Read Instruction 3BH A31:A24 6BH (1-1-4) Fast Read Opcode Opcode for single input opcode & address and quad output data Fast Read. JEDEC Flash Parameter Table: 4 th DWORD 3CH A4:A0 A7:A5 08H 3DH A15:A8 3BH 3EH A20:A16 A23:A21 80H (1-1-2) Fast Read Number of Wait states (dummy clocks) needed before valid output 01000b: 8 dummy clocks are needed with a single input opcode, address and dual output data fast read instruction. (1-1-2) Fast Read Number of Mode Bits 000b: No mode bits are needed with a single input opcode & address and quad output data Fast Read Instruction (1-1-2) Fast Read Opcode Opcode for single input opcode& address and dual output data Fast Read. (1-2-2) Fast Read Number of Wait states (dummy clocks) needed before valid output 00000b: 0 clocks of dummy cycle. (1-2-2) Fast Read Number of Mode Bits (in clocks) 100b: 4 clocks of mode bits are needed 3FH A31:A24 BBH (1-2-2) Fast Read Opcode Opcode for single input opcode, dual input address, and dual output data Fast Read. JEDEC Flash Parameter Table: 5 th DWORD 40H A0 A3:A1 FEH Supports (2-2-2) Fast Read Device supports dual input opcode& address and dual output data Fast Read. 0: (2-2-2) Fast Read NOT supported. 1: (2-2-2) Fast Read supported. Reserved. Bits default to all 1 s. Supports (4-4-4) Fast Read Device supports Quad input opcode & address and quad output data A4 Fast Read. 0: (4-4-4) Fast Read NOT supported. 1: (4-4-4) Fast Read supported. A7:A5 Reserved. Bits default to all 1 s. 41H A15:A8 FFH Reserved. Bits default to all 1 s. 42H A23:A16 FFH Reserved. Bits default to all 1 s. 43H A31:A24 FFH Reserved. Bits default to all 1 s Microchip Technology Inc. DS C-page 63

64 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (5 OF 16) Address Bit Address Data Comments JEDEC Flash Parameter Table: 6 th DWORD 44H A7:A0 FFH Reserved. Bits default to all 1 s. 45H A15:A8 FFH Reserved. Bits default to all 1 s. 46H A20:A16 A23:A21 00H (2-2-2) Fast Read Number of Wait states (dummy clocks) needed before valid output 00000b: No dummy bit is needed (2-2-2) Fast Read Number of Mode Bits 000b: No mode bits are needed 47H A31:A24 FFH (2-2-2) Fast Read Opcode Opcode for dual input opcode& address and dual output data Fast Read. (not supported) JEDEC Flash Parameter Table: 7 th DWORD 48H A7:A0 FFH Reserved. Bits default to all 1 s. 49H A15:A8 FFH Reserved. Bits default to all 1 s. 4AH A20:A16 A23:A21 44H 4BH A31:A24 0BH JEDEC Flash Parameter Table: 8 th DWORD 4CH A7:A0 0CH 4DH A15:A8 20H 4EH A23:A16 0DH (4-4-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 00100b: 4 clocks dummy are needed with a quad input opcode & address and quad output data Fast Read Instruction (4-4-4) Fast Read Number of Mode Bits 010b: 2 clocks mode bits are needed with a quad input opcode & address and quad output data Fast Read Instruction (4-4-4) Fast Read Opcode Opcode for quad input opcode/address, quad output data Fast Read Sector Type 1 Size 4 KByte, Sector/block size = 2 N bytes Sector Type 1 Opcode Opcode used to erase the number of bytes specified by Sector Type 1 Size. Sector Type 2 Size 8 KByte, Sector/block size = 2 N bytes 4FH A31:A24 D8H Sector Type 2 Opcode Opcode used to erase the number of bytes specified by Sector Type 2 Size. JEDEC Flash Parameter Table: 9 th DWORD 50H A7:A0 0FH 51H A15:A8 D8H 52H A23:A16 10H 53H A31:A24 D8H Sector Type 3 Size 32 KByte, Sector/block size = 2 N bytes Sector Type 3 Opcode Opcode used to erase the number of bytes specified by Sector Type 3 Size. Sector Type 4 Size 64 KByte, Sector/block size = 2 N bytes Sector Type 4 Opcode Opcode used to erase the number of bytes specified by Sector Type 4 Size DS C-page Microchip Technology Inc.

65 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (6 OF 16) Address Bit Address Data Comments JEDEC Flash Parameter Table: 10 th DWORD 54H 55H 56H A3:A0 A7:A4 A10:A8 A15:A11 A17:A16 A23:A18 A24 20H 91H 48H Multiplier from typical erase time to maximum erase time Maximum time = 2*(count + 1)*Typical erase time Count = 0 A3:A0= 0000b Erase Type 1 Erase, Typical time Typical Time = (count +1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s A10:A9 units (00b:1ms, 01b:16ms, 10b:128ms, 11b:1s) A8:A4 count = 18 = 10010b A10:A9 unit = 1ms = 00b A10:A8=001b Erase Type 2 Erase, Typical time Typical time = (count+1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s A17:A16 units (00b:1ms, 01b:16ms, 10b:128ms, 11b:1s) A15:A11 count = 18 =10010b A17:A16 unit = 1ms =00b A17:A16=00b Erase Type 3 Erase, Typical time Typical time = (count+1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s A24:A23 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s) A22:A18 count = 18 = 10010b A24:A23 unit = 1ms = 00b A24=0b Erase Type 4 Erase, Typical time Typical time = (count+1)*units 57H 24H A31:A25 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s A31:A30 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s) A29:A25 count=18=10010b A31:A30 unit = 1ms =00b JEDEC Flash Parameter Table: 11 th DWORD 58H A3:A0 A7:A4 80H Multiplier from Typical Program Time to Maximum Program Time Maximum time = 2*(count +1)*Typical program time. Count =0. A3:A0=0000b Page Size Page size = 2 N bytes. N=8 A7:A4 =1000b Microchip Technology Inc. DS C-page 65

66 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (7 OF 16) Address Bit Address Data Comments 59H 5AH 5BH A13:A8 A15:A14 A18:A16 A23:A19 A30:A:24 6FH 1DH 81H Page Program Typical time Program time = (count+1)*units A13 units (0b:8µs, 1b:64µs) A12:A8 count = 11 = 01111b A13 unit = 64µs = 1b Byte Program Typical time, first byte Typical time = (count+1)*units A18 units (0b: 1µs, 1b: 8µs) A17:A14 count = 5 = 0101b A18 = 8µs = 1b A18:A16=101b Reserved A31 A31=1b JEDEC Flash Parameter Table: 12 th DWORD 5CH A3:A0 A7:A4 EDH Byte Program Typical time, Additional Byte Typical time = (count+1)*units A23 units (0b: 1µs, 1b: 8µs) A22:A19 count = 0011b A23=1μs=0b Chip Erase Typical Time Typical time = (count+1)*units 16ms to 512ms, 256ms to 8192ms, 4s to 128s, 64s to 2048s A28:A24 count =1=00001b A30:A29 units =16ms=00b Prohibited Operations During Program Suspend xxx0b: May not initiate a new erase anywhere xxx1b:may not initiate a new erase in the program suspended page size xx0xb:may not initiate a new page program anywhere xx1xb: May not initiate a new page program in program suspended page size. x0xxb:refer to the Data Sheet x1xxb: May not initiate a read in the program suspended page size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 1:0 are sufficient Prohibited Operation During Erase Suspend xxx0b: May not initiate a new erase anywhere xxx1b:may not initiate a new erase in the erase suspended page size xx0xb:may not initiate a new page program anywhere xx1xb: May not initiate a new page program in erase suspended erase type size. x0xxb:refer to the Data Sheet x1xxb: May not initiate a read in the erase suspended page size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 5:4 are sufficient DS C-page Microchip Technology Inc.

67 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (8 OF 16) Address Bit Address Data Comments 5DH 5EH 5FH A8 A12:A9 A15:A13 A19:A16 A23:A20 A30:A24 0FH 77H 38H Reserved = 1b Program Resume to Suspend Interval The device requires this typical amount of time to make progress on the program operation before allowing another suspend. Interval =500µs Program resume to suspend interval =(count+1)*64µs A12:A9= 7 =0111b Suspend in-progress program max latency Maximum time required by the flash device to suspend an in-progress program and be ready to accept another command which accesses the flash array. Max latency = 25µs program max latency =(count+1)*units units (00b:128ns, 01b:1µs, 10b:8µs, 11b:64µs) A17:A13= count = 24 = 11000b A19:A18 = 1µs =01b 0111b Suspend/Resume supported A31 0:supported 1:not supported JEDEC Flash Parameter Table: 13 th DWORD 60H A7:A0 30H Program Resume Instruction 61H A15:A8 B0H Program Suspend Instruction 62H A23:A16 30H Resume Instruction 63H A31:A24 B0H Suspend Instruction JEDEC Flash Parameter Table: 14 th DWORD 64H A1:A0 A7:A2 F7H Erase Resume to Suspend Interval The device requires this typical amount of time to make progress on the erase operation before allowing another suspend. Interval = 500µs Erase resume to suspend interval =(count+1)*64µs A23:A20= 7 =0111b Suspend in-progress erase max latency Maximum time required by the flash device to suspend an in-progress erase and be ready to accept another command which accesses the flash array. Max latency = 25µs Erase max latency =(count+1)*units units (00b:128ns, 01b:1µs, 10b:8µs, 11b:64µs) A28:A24= count = 24 = 11000b A30:A29 = 1µs =01b Reserved = 11b Status Register Polling Device Busy b: Use of legacy polling is supported by reading the status register with 05h instruction and checking WIP bit [0] (0=ready, 1=busy) Microchip Technology Inc. DS C-page 67

68 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (9 OF 16) Address Bit Address Data Comments 65H 66H A14:A8 A15 A22:A16 A23 A30:A24 A9H D5H Exit Deep Power-down to next operation delay 10 µs Delay = (count +1)*unit A12:A8 = count = 9 = 01001b A14:A13 units = 01b = 1µs Exit Power-down Instruction ABH = b A15=1b A22:A16= b Enter Power-down instruction B9H = b A23 = 1b A30:A24 = H 5CH Deep Power-down Supported A31 0:supported 1:not supported JEDEC Flash Parameter Table: 15 th DWORD 68H 69H 6AH A3:A0 A7:A4 A8 A9 A15:A10 A19:A16 A22:A20 29H C2H 5CH mode disable sequences Xxx1b: issue FF instruction 1xxxb: issue the Soft Reset 66/99 sequence mode enable sequences X_xx1xb: issue instruction 38h mode enable sequences A8 = mode supported 0:not supported 1:supported Mode Exit Method X1_xxxx:Mode Bit[7:0] Not= AXh 1x_xxxx Reserved = Mode Entry Method X1xxb: M[7:0]=AXh 1xxxb:Reserved =1 A23 HOLD and Reset Disable 0:feature is not supported 6BH A31:A24 FFH Reserved bits = 0xFF JEDEC Flash Parameter Table: 16 th DWORD 6C 6D Quad Enable Requirements (QER) 101b: Quad Enable is bit 1 of the configuration register. Volatile or Non-Volatile Register and Write Enable Instructions for Status Register 1 Xx1_xxxxb:Status Register 1 contains a mix of volatile and non-volatile A6:A0 F0H bits. The 06h instruction is used to enable writing to the register. X1x_xxxxb: Reserved = 1 1xx_xxxxb: Reserved = 1 A7 Reserved =1b A13:A8 A15:A14 30H Soft Reset and Rescue Sequence Support X1_xxxxb: reset enable instruction 66h is issued followed by reset instruction 99h. 1x_xxxxb: exit mode is required prior to other reset sequences. Exit 4-Byte Addressing Not supported DS C-page Microchip Technology Inc.

69 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (10 OF 16) Address Bit Address Data Comments 6E A23:A16 C0H 6F A31:A24 80H JEDEC Sector Map Parameter Table Exit 4-Byte Addressing Not supported A21:A14= b A23 and A22 are Reserved bits which are = 1 Enter 4-Byte Addressing Not supported 1xxx_xxxx: Reserved = 1 100H A7:A0 FFH Sector Map A7:A2=Reserved=111111b A1=Descriptor Type = Map=1b A0=Last map = 1b 101H A15:A8 00H Configuration ID = 00h 102H A23:A16 04H Region Count = 5 Regions 103H A31:A24 FFH Reserved = FFh 104H A7:A0 F3H 105H A15:A8 7FH 106H A23:A16 00H 107H A31:A24 00H 108H A7:A0 F5H 109H A15:A8 7FH 10AH A23:A16 00H 10BH A31:A24 00H 10CH A7:A0 F9H 10DH A15:A8 FFH 10EH A23:A16 05H 10FH A31:A24 00H 110H A7:A0 F5H Region 0 supports 4 KByte erase and 8 KByte erase A3:A0=0011b A7:A4=Reserved=1111b Region 0 Size 4 * 8 KBytes = 32 KBytes Count=32 KBytes/256 bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh Region 1 supports 4 KByte erase and 32 KByte erase A3:A0 = 0101b A7:A4=Reserved = 1111b Region 1 size 1 * 32 KBytes = 32 KBytes Count=32 KBytes/256 bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh Region 2 supports 4 KByte erase and 64 KByte erase A3:A0 = 1001b A7:A4=Reserved = 1111b Region 2 size 6 * 64 KBytes = 384 KBytes Count=384 KBytes/256 bytes= 1536 Value = count -1 =1535 A31:A8 = 0005FFh Region 3 supports 4 KByte erase and 32 KByte erase A3:A0 = 0101b A7:A4=Reserved = 1111b Microchip Technology Inc. DS C-page 69

70 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (11 OF 16) Address Bit Address Data Comments 111H A15:A8 7FH Region 3 size 1 * 32 KBytes = 32 KBytes Count=32 KBytes/256 bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh 112H A23:A16 00H 113H A31:A24 00H 114H A7:A0 F3H Region 4 supports 4 KByte erase and 8 KByte erase A3:A0=0011b A7:A4=Reserved=1111b 115H A15:A8 7FH Region 4 Size 4 * 8 KBytes = 32 KBytes Count=32 KBytes/256 bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh 116H A23:A16 00H 117H A31:A24 00H SST26WF040B/040BA (Vendor) Parameter Table SST26WF040B/040BA Identification 200H A7:A0 BFH Manufacturer ID 201H A15:A8 26H Memory Type 202H A23:A16 54H Device ID SST26WF040B/040BA=54H 203H A31:A24 FFH Reserved. Bits default to all 1 s. SST26WF040B/040BA Interface 204H A2:A0 A3 A6:A4 A7 B9H Interfaces Supported 000: SPI only 001: Power up default is SPI; Quad can be enabled/disabled 010: Reserved : : 111: Reserved Supports Enable Quad 0: not supported 1: supported Supports Hold#/Reset# Function 000: Hold# 001: Reset# 010: HOLD/Reset# 011: Hold# & I/O when in SQI(4-4-4), or Read Supports Software Reset 0: not supported 1: supported DS C-page Microchip Technology Inc.

71 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (12 OF 16) Address Bit Address Data Comments 205H 206H Supports Quad Reset A8 0: not supported 1: supported A10:A9 Reserved. Bits default to all 1 s A13:A11 A14 A15 A16 A17 A18 DFH FDH Byte-Program or Page-Program (256 Bytes) 011: Byte Program/Page Program in SPI and Quad Page Program once Quad is enabled Program-Erase Suspend Supported 0: Not Supported 1: Program/Erase Suspend Supported Deep Power-Down Mode Supported 0: Not Supported 1: Deep Power-Down Mode Supported OTP Capable (Security ID) Supported 0: not supported 1: supported Supports Block Group Protect 0: not supported 1: supported Supports Independent Block Protect 0: not supported 1: supported Supports Independent non Volatile Lock (Block or Sector A19 becomes OTP) 0: not supported 1: supported A23:A20 Reserved. Bits default to all 1 s. 207H A31:A24 FFH Reserved. Bits default to all 1 s. 208H A7:A0 65H V DD Minimum Supply Voltage 209H A15:A8 F1H 1.65V (F165H) 20AH A23:A16 95H V DD Maximum Supply Voltage 20BH A31:A24 F1H 1.95V (F195H) 20CH A7:A0 32H Typical time out for Byte-Program: 50 µs Typical time out for Byte Program is in µs. Represented by conversion of the actual time from the decimal to hexadecimal number. 20DH A15:A8 FFH Reserved. Bits default to all 1 s. 20EH A23:A16 0AH Typical time out for page program: 1.0ms (xxh*(0.1ms)) 20FH A31:A24 12H 210H A7:A0 23H Typical time out for Sector-Erase/Block-Erase: 18 ms Typical time out for Sector/Block-Erase is in ms. Represented by conversion of the actual time from the decimal to hexadecimal number. Typical time out for Chip-Erase: 35 ms Typical time out for Chip-Erase is in ms. Represented by conversion of the actual time from the decimal to hexadecimal number. 211H A15:A8 46H Max. time out for Byte-Program: 70 µs Typical time out for Byte Program is in µs. Represented by conversion of the actual time from the decimal to hexadecimal number. 212H A23:A16 FFH Reserved. Bits default to all 1 s Microchip Technology Inc. DS C-page 71

72 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (13 OF 16) Address Bit Address Data Comments 213H A31:A24 0FH 214H A7:A0 19H 215H A15:A8 32H 216H A23:A16 0FH 217H A31:A24 19H 218H A23:A16 19H 219H A31:A24 03H Max time out for Page-Program: 1.5ms. Typical time out for Page Program in xxh * (0.1ms) ms Max. time out for Sector Erase/Block Erase: 25ms. Max time out for Sector/Block Erase in ms Max. time out for Chip Erase: 50ms. Max time out for Chip Erase in ms. Max. time out for Program Security ID: 1.5 ms Max time out for Program Security ID in xxh*(0.1ms) ms Max. time for Write-Protection Enable Latency: 25 ms Max time out for ms. Represented by conversion of the actual time from the decimal to hexadecimal number. Max. time Write-Suspend Latency: 25 µs Max time out for Write-Suspend Latency is in µs. Represented by conversion of the actual time from the decimal to hexadecimal number.) Max. time to Deep Power-Down: 3 µs 3 µs = 03H 21AH A23:A16 0AH Max. time out from Deep Power-Down mode to Standby mode: 10 µs. 10 µs = 0AH 21BH A31:A24 FFH Reserved. Bits default to all 1 s. 21CH A23:A16 FFH Reserved. Bits default to all 1 s. 21DH A31:A24 FFH Reserved. Bits default to all 1 s. 21EH A23:A16 FFH Reserved. Bits default to all 1 s. 21FH A31:A24 FFH Reserved. Bits default to all 1 s. Supported Instructions 220H A7:A0 00H No Operation 221H A15:A8 66H Reset Enable 222H A23:A16 99H Reset Memory 223H A31:A24 38H Enable Quad I/O 224H A7:A0 FFH Reset Quad I/O 225H A15:A8 05H Read Status Register 226H A23:A16 01H Write Status Register 227H A31:A24 35H Read Configuration Register 228H A7:A0 06H Write Enable 229H A15:A8 04H Write Disable 22AH A23:A16 02H Byte Program or Page Program 22BH A31:A24 32H SPI Quad Page Program 22CH A7:A0 B0H Suspends Program/Erase 22DH A15:A8 30H Resumes Program/Erase 22EH A23:A16 72H Read Block-Protection register 22FH A31:A24 42H Write Block Protection Register 230H A7:A0 8DH Lock Down Block Protection Register 231H A15:A8 E8H Non-Volatile Write-Lock Down Register 232H A23:A16 98H Global Block Protection Unlock 233H A31:A24 88H Read Security ID 234H A7:A0 A5H Program User Security ID Area 235H A15:A8 85H Lockout Security ID Programming DS C-page Microchip Technology Inc.

73 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (14 OF 16) Address Bit Address Data Comments 236H A23:A16 C0H Set Burst Length 237H A31:A24 9FH JEDEC-ID 238H A7:A0 AFH Quad J-ID 239H A15:A8 5AH SFDP 23AH A23:A16 B9H Deep Power-Down Mode 23BH A31:A24 ABH Release Deep Power-Down Mode 23CH A4:A0 06H (1-4-4) SPI nb Burst with Wrap Number of Wait states (dummy clocks) needed before valid output 00110b: 6 clocks of dummy cycle A7:A5 (1-4-4) SPI nb Burst with Wrap Number of Mode Bits 000b: Set Mode bits are not supported 23DH A15:A8 ECH (1-4-4) SPI nb Burst with Wrap Opcode 23EH A20:A16 06H (4-4-4) SQI nb Burst with Wrap Number of Wait states (dummy clocks) needed before valid output 00110b: 6 clocks of dummy cycle A23:A21 (4-4-4) SQI nb Burst with Wrap Number of Mode Bits 000b: Set Mode bits are not supported 23FH A31:A24 0CH (4-4-4) SQI nb Burst with Wrap Opcode 240H A4:A0 00H (1-1-1) Read Memory Number of Wait states (dummy clocks) needed before valid output 00000b: Wait states/dummy clocks are not supported. A7:A5 (1-1-1) Read Memory Number of Mode Bits 000b: Mode bits are not supported, 241H A15:A8 03H (1-1-1) Read Memory Opcode 242H A20:A16 08H (1-1-1) Read Memory at Higher Speed Number of Wait states (dummy clocks) needed before valid output 01000: 8 clocks (8 bits) of dummy cycle A23:A21 (1-1-1) Read Memory at Higher Speed Number of Mode Bits 000b: Mode bits are not supported, 243H A31:A24 0BH (1-1-1) Read Memory at Higher Speed Opcode 244H A7:A0 FFH Reserved. Bits default to all 1 s. 245H A15:A8 FFH Reserved. Bits default to all 1 s. 246H A23:A16 FFH Reserved. Bits default to all 1 s. 247H A31:A24 FFH Reserved. Bits default to all 1 s. Security ID 248H A7:A0 FFH Security ID size in bytes Example: If the size is 2 KBytes, this field would be 07FFH 249H A15:A8 07H Security ID Range Unique ID (Pre-programmed at factory) 0000H H User Programmable 0008H - 07FFH 24AH A23:A16 FFH Reserved. Bits default to all 1 s. 24BH A31:A24 FFH Reserved. Bits default to all 1 s Microchip Technology Inc. DS C-page 73

74 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (15 OF 16) Address Bit Address Data Comments Memory Organization/Block Protection Bit Mapping 1 24CH A7:A0 02H 24DH A15:A8 02H 24EH A23:A16 FFH 24FH A31:A24 06H 250H A7:A0 03H 251H A15:A8 00H 252H A23:A16 FDH 253H A31:A24 FDH 254H A7:A0 04H 255H A15:A8 03H 256H A23:A16 00H 257H A31:A24 FCH 258H A7:A0 03H 259H A15:A8 00H Section 1: Sector Type Number: Sector type in JEDEC Parameter Table (bottom, 8 KByte) Section 1 Number of Sectors Four of 8KB blocks (2 n ) Section 1 Block Protection Bit Start ((2 m ) +1)+ c, c=ffh or -1, m= 3 for 4 Mb Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 1 (bottom) Block Protection Bit End ((2 m ) +1)+ c, c=06h or 6, m= 3 for 4 Mb Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 2: Sector Type Number Sector type in JEDEC Parameter Table (32 KByte Block) Section 2 Number of Sectors One of 32 KByte Block (2 n, n=0) Section 2 Block Protection Bit Start ((2 m ) +1)+ c, c=fdh or -3, m= 3 for 4 Mb The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 2 Block Protection Bit End ((2 m ) +1)+ c, c=fdh or -3, m= 3 for 4 Mb The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 3: Sector Type Number Sector type in JEDEC Parameter Table (64 KByte Block) Section 3 Number of Sectors Thirty of 64 KByte Block (2 n -2, n= 3) Section 3 Block Protection Bit Start Section 3 Block Protection Bit starts at 00H Section 3 Block Protection Bit End ((2 m ) +1)+ c, c=fch or -4, m= 3 for 4 Mb Section 4: Sector Type Number Sector type in JEDEC Parameter Table (32 KByte Block) Section 4 Number of Sectors One of 32KByte Block (2 n, n=0) DS C-page Microchip Technology Inc.

75 TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF040B/040BA (CONTINUED) (16 OF 16) Address Bit Address Data Comments 25AH A23:A16 FEH 25BH A31:A24 FEH 25CH A7:A0 02H 25DH A15:A8 02H 25EH A23:A16 07H 25FH A31:A24 0EH Section 4 Block Protection Bit Start ((2 m ) +1)+ c, c=feh or -2, m= 3 for 4 Mb The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 4 Block Protection Bit End ((2 m ) +1)+ c, c=feh or -2, m= 3 for 4 Mb The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 5 Sector Type Number: Sector type in JEDEC Parameter Table (top, 8 KByte) Section 5 Number of Sectors Four of 8 KByte blocks (2 n ) 1. See Mapping Guidance Details for more detailed mapping information Section 5 Block Protection Bit Start ((2 m ) +1)+ c, c=07h or 7, m= 3 for 4 Mb Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 5 (Top) Block Protection Bit End (((2 m ) +1)+ c, c=0eh or 15, m= 3 for 4 Mb, Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative Microchip Technology Inc. DS C-page 75

76 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (1 OF 16) Address Bit Address Data Comments SFDP Header SFDP Header: 1 st DWORD 00H A7:A0 53H SFDP Signature 01H A15:A8 46H SFDP Signature= H 02H A23:A16 44H 03H A31:A24 50H SFDP Header: 2 nd DWORD 04H A7:A0 06H SFDP Minor Revision Number 05H A15:A8 01H SFDP Major Revision Number 06H A23:A16 02H Number of Parameter Headers (NPH)=3 07H A31:A24 FFH Unused. Contains FF and can not be changed. Parameter Headers JEDEC Flash Parameter Header: 1 st DWORD Parameter ID Least Significant Bit (LSB) Number. 08H A7:A0 00H When this field is set to 00H, it indicates a JEDEC-specified header. For vendor-specified headers, this field must be set to the vendor s manufacturer ID. 09H A15:A8 06H Parameter Table Minor Revision Number Minor revisions are either clarifications or changes that add parameters in existing Reserved locations. Minor revisions do NOT change overall structure of SFDP. Minor Revision starts at 00H. 0AH A23:A16 01H Parameter Table Major Revision Number Major revisions are changes that reorganize or add parameters to locations that are NOT currently Reserved. Major revisions would require code (BIOS/firmware) or hardware change to get previously defined discoverable parameters. Major Revision starts at 01H 0BH A31:A24 10H Parameter Table Length Number of DWORDs that are in the Parameter table JEDEC Flash Parameter Header: 2 nd DWORD 0CH A7:A0 30H Parameter Table Pointer (PTP) 0DH A15:A8 00H A 24-bit address that specifies the start of this header s Parameter table in the SFDP structure. The address must be DWORD-aligned. 0EH A23:A16 00H 0FH A31:A24 FFH Parameter ID Most Significant Bit (MSB) Number JEDEC Flash Parameter Header: 3 rd DWORD Parameter ID LSB Number 10H A7:A0 81H Sector map, function-specific table is assigned 81H 11H A15:A8 00H 12H A23:A16 01H 13H A31:A24 06H Parameter Table Minor Revision Number Minor revisions are either clarifications or changes that add parameters in existing Reserved locations. Minor revisions do NOT change overall structure of SFDP. Minor Revision starts at 00H. Parameter Table Major Revision Number Major revisions are changes that reorganize or add parameters to locations that are NOT currently Reserved. Major revisions would require code (BIOS/firmware) or hardware change to get previously defined discoverable parameters. Major Revision starts at 01H Parameter Table Length Number of DWORDs that are in the Parameter table DS C-page Microchip Technology Inc.

77 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (2 OF 16) Address Bit Address Data Comments JEDEC Flash Parameter Header: 4 th DWORD 14H A7:A0 00H Parameter Table Pointer (PTP) 15H A15:A8 01H This 24-bit address specifies the start of this header s Parameter Table in the SFDP structure. The address must be DWORD-aligned. 16H A23:A16 00H 17H A31:A24 FFH Parameter ID MSB Number. Microchip (Vendor) Parameter Header: 5 th DWORD 18H A7:A0 BFH ID Number Manufacture ID (vendor specified header) 19H A15:A8 00H Parameter Table Minor Revision Number 1AH A23:A16 01H Parameter Table major Revision Number, Revision 1.0 1BH A31:A24 18H Parameter Table Length, 24 Double Words Microchip (Vendor) Parameter Header: 6 th DWORD 1CH A7:A0 00H Parameter Table Pointer (PTP) 1DH A15:A8 02H This 24-bit address specifies the start of this header s Parameter Table in the SFDP structure. The address must be DWORD-aligned. 1EH A23:A16 00H 1FH A31:A24 01H Used to indicate bank number (vendor specific) JEDEC Flash Parameter Table JEDEC Flash Parameter Table: 1 st DWORD Block/Sector Erase Sizes 00: Reserved A1:A0 01: 4 KByte Erase 10: Reserved 11: Use this setting only if the 4 KByte erase is unavailable. Write Granularity 0: Single-byte programmable devices or buffer programmable A2 devices with buffer is less than 64 bytes (32 Words). 1: For buffer programmable devices when the buffer size is 64 30H FDH Bytes (32 Words) or larger. Volatile Status Register A3 0: Target flash has nonvolatile status bit. Write/Erase commands do not require status register to be written on every power on. 1: Target flash has volatile status bits Write Enable Opcode Select for Writing to Volatile Status Register A4 0: 0x50. Enables a status register write when bit 3 is set to 1. 1: 0x06 Enables a status register write when bit 3 is set to 1. A7:A5 Unused. Contains 111b and can not be changed 31H A15:A8 20H 4 KByte Erase Opcode Microchip Technology Inc. DS C-page 77

78 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (3 OF 16) Address Bit Address Data Comments Supports (1-1-2) Fast Read A16 0: (1-1-2) Fast Read NOT supported 1: (1-1-2) Fast Read supported Address Bytes Number of bytes used in addressing flash array read, write and erase 00: 3-Byte only addressing A18:A17 01: 3- or 4-Byte addressing (e.g. defaults to 3-Byte mode; enters 4- Byte mode on command) 10: 4-Byte only addressing 11: Reserved Supports Double Transfer Rate (DTR) Clocking Indicates the device supports some type of double transfer rate clocking. A19 0: DTR NOT supported 1: DTR Clocking supported 32H F1H Supports (1-2-2) Fast Read Device supports single input opcode, dual input address, and dual output A20 data Fast Read. 0: (1-2-2) Fast Read NOT supported. 1: (1-2-2) Fast Read supported. Supports (1-4-4) Fast Read Device supports single input opcode, quad input address, and quad A21 output data Fast Read 0: (1-4-4) Fast Read NOT supported. 1: (1-4-4) Fast Read supported. Supports (1-1-4) Fast Read Device supports single input opcode & address and quad output data A22 Fast Read. 0: (1-1-4) Fast Read NOT supported. 1: (1-1-4) Fast Read supported. A23 Unused. Contains 1 can not be changed 33H A31:A24 FFH Unused. Contains FF can not be changed JEDEC Flash Parameter Table: 2 nd DWORD 34H A7:A0 FFH Flash Memory Density 35H A15:A8 FFH SST26WF080B/080BA= 007FFFFFH 36H A23:A16 7FH 37H A31:A24 00H JEDEC Flash Parameter Table: 3 rd DWORD 38H A4:A0 A7:A5 44H 39H A15:A8 EBH (1-4-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input address phase instruction Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode Bits 010b: 2 dummy clocks (8 mode bits) are needed with a single input opcode, quad input address and quad output data Fast Read Instruction. (1-4-4) Fast Read Opcode Opcode for single input opcode, quad input address, and quad output data Fast Read. DS C-page Microchip Technology Inc.

79 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (4 OF 16) Address Bit Address Data Comments 3AH A20:A16 A23:A21 08H (1-1-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 01000b: 8 dummy bits are needed with a single input opcode & address and quad output data Fast Read Instruction (1-1-4) Fast Read Number of Mode Bits 000b: No mode bits are needed with a single input opcode & address and quad output data Fast Read Instruction 3BH A31:A24 6BH (1-1-4) Fast Read Opcode Opcode for single input opcode & address and quad output data Fast Read. JEDEC Flash Parameter Table: 4 th DWORD 3CH A4:A0 A7:A5 08H 3DH A15:A8 3BH 3EH A20:A16 A23:A21 80H (1-1-2) Fast Read Number of Wait states (dummy clocks) needed before valid output 01000b: 8 dummy clocks are needed with a single input opcode, address and dual output data fast read instruction. (1-1-2) Fast Read Number of Mode Bits 000b: No mode bits are needed with a single input opcode & address and quad output data Fast Read Instruction (1-1-2) Fast Read Opcode Opcode for single input opcode& address and dual output data Fast Read. (1-2-2) Fast Read Number of Wait states (dummy clocks) needed before valid output 00000b: 0 clocks of dummy cycle. (1-2-2) Fast Read Number of Mode Bits (in clocks) 100b: 4 clocks of mode bits are needed 3FH A31:A24 BBH (1-2-2) Fast Read Opcode Opcode for single input opcode, dual input address, and dual output data Fast Read. JEDEC Flash Parameter Table: 5 th DWORD 40H A0 A3:A1 FEH Supports (2-2-2) Fast Read Device supports dual input opcode& address and dual output data Fast Read. 0: (2-2-2) Fast Read NOT supported. 1: (2-2-2) Fast Read supported. Reserved. Bits default to all 1 s. Supports (4-4-4) Fast Read Device supports Quad input opcode & address and quad output data A4 Fast Read. 0: (4-4-4) Fast Read NOT supported. 1: (4-4-4) Fast Read supported. A7:A5 Reserved. Bits default to all 1 s. 41H A15:A8 FFH Reserved. Bits default to all 1 s. 42H A23:A16 FFH Reserved. Bits default to all 1 s. 43H A31:A24 FFH Reserved. Bits default to all 1 s Microchip Technology Inc. DS C-page 79

80 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (5 OF 16) Address Bit Address Data Comments JEDEC Flash Parameter Table: 6 th DWORD 44H A7:A0 FFH Reserved. Bits default to all 1 s. 45H A15:A8 FFH Reserved. Bits default to all 1 s. 46H A20:A16 A23:A21 00H (2-2-2) Fast Read Number of Wait states (dummy clocks) needed before valid output 00000b: No dummy bit is needed (2-2-2) Fast Read Number of Mode Bits 000b: No mode bits are needed 47H A31:A24 FFH (2-2-2) Fast Read Opcode Opcode for dual input opcode& address and dual output data Fast Read. (not supported) JEDEC Flash Parameter Table: 7 th DWORD 48H A7:A0 FFH Reserved. Bits default to all 1 s. 49H A15:A8 FFH Reserved. Bits default to all 1 s. 4AH A20:A16 A23:A21 44H 4BH A31:A24 0BH JEDEC Flash Parameter Table: 8 th DWORD 4CH A7:A0 0CH 4DH A15:A8 20H 4EH A23:A16 0DH (4-4-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 00100b: 4 clocks dummy are needed with a quad input opcode & address and quad output data Fast Read Instruction (4-4-4) Fast Read Number of Mode Bits 010b: 2 clocks mode bits are needed with a quad input opcode & address and quad output data Fast Read Instruction (4-4-4) Fast Read Opcode Opcode for quad input opcode/address, quad output data Fast Read Sector Type 1 Size 4 KByte, Sector/block size = 2 N bytes Sector Type 1 Opcode Opcode used to erase the number of bytes specified by Sector Type 1 Size. Sector Type 2 Size 8 KByte, Sector/block size = 2 N bytes 4FH A31:A24 D8H Sector Type 2 Opcode Opcode used to erase the number of bytes specified by Sector Type 2 Size. JEDEC Flash Parameter Table: 9 th DWORD 50H A7:A0 0FH 51H A15:A8 D8H 52H A23:A16 10H 53H A31:A24 D8H Sector Type 3 Size 32 KByte, Sector/block size = 2 N bytes Sector Type 3 Opcode Opcode used to erase the number of bytes specified by Sector Type 3 Size. Sector Type 4 Size 64 KByte, Sector/block size = 2 N bytes Sector Type 4 Opcode Opcode used to erase the number of bytes specified by Sector Type 4 Size DS C-page Microchip Technology Inc.

81 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (6 OF 16) Address Bit Address Data Comments JEDEC Flash Parameter Table: 10 th DWORD 54H 55H 56H A3:A0 A7:A4 A10:A8 A15:A11 A17:A16 A23:A18 A24 20H 91H 48H Multiplier from typical erase time to maximum erase time Maximum time = 2*(count + 1)*Typical erase time Count = 0 A3:A0= 0000b Erase Type 1 Erase, Typical time Typical Time = (count +1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s A10:A9 units (00b:1ms, 01b:16ms, 10b:128ms, 11b:1s) A8:A4 count = 18 = 10010b A10:A9 unit = 1ms = 00b A10:A8=001b Erase Type 2 Erase, Typical time Typical time = (count+1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s A17:A16 units (00b:1ms, 01b:16ms, 10b:128ms, 11b:1s) A15:A11 count = 18 =10010b A17:A16 unit = 1ms =00b A17:A16=00b Erase Type 3 Erase, Typical time Typical time = (count+1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s A24:A23 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s) A22:A18 count = 18 = 10010b A24:A23 unit = 1ms = 00b A24=0b Erase Type 4 Erase, Typical time Typical time = (count+1)*units 57H 24H A31:A25 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s A31:A30 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s) A29:A25 count=18=10010b A31:A30 unit = 1ms =00b JEDEC Flash Parameter Table: 11 th DWORD 58H A3:A0 A7:A4 80H Multiplier from Typical Program Time to Maximum Program Time Maximum time = 2*(count +1)*Typical program time. Count =0. A3:A0=0000b Page Size Page size = 2 N bytes. N=8 A7:A4 =1000b Microchip Technology Inc. DS C-page 81

82 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (7 OF 16) Address Bit Address Data Comments 59H 5AH 5BH A13:A8 A15:A14 A18:A16 A23:A19 A30:A:24 6FH 1DH 81H Page Program Typical time Program time = (count+1)*units A13 units (0b:8µs, 1b:64µs) A12:A8 count = 11 = 01111b A13 unit = 64µs = 1b Byte Program Typical time, first byte Typical time = (count+1)*units A18 units (0b: 1µs, 1b: 8µs) A17:A14 count = 5 = 0101b A18 = 8µs = 1b A18:A16=101b Reserved A31 A31=1b JEDEC Flash Parameter Table: 12 th DWORD 5CH A3:A0 A7:A4 EDH Byte Program Typical time, Additional Byte Typical time = (count+1)*units A23 units (0b: 1µs, 1b: 8µs) A22:A19 count = 0011b A23=1μs=0b Chip Erase Typical Time Typical time = (count+1)*units 16ms to 512ms, 256ms to 8192ms, 4s to 128s, 64s to 2048s A28:A24 count =1=00001b A30:A29 units =16ms=00b Prohibited Operations During Program Suspend xxx0b: May not initiate a new erase anywhere xxx1b:may not initiate a new erase in the program suspended page size xx0xb:may not initiate a new page program anywhere xx1xb: May not initiate a new page program in program suspended page size. x0xxb:refer to the Data Sheet x1xxb: May not initiate a read in the program suspended page size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 1:0 are sufficient Prohibited Operation During Erase Suspend xxx0b: May not initiate a new erase anywhere xxx1b:may not initiate a new erase in the erase suspended page size xx0xb:may not initiate a new page program anywhere xx1xb: May not initiate a new page program in erase suspended erase type size. x0xxb:refer to the Data Sheet x1xxb: May not initiate a read in the erase suspended page size 0xxxb: Additional erase or program restrictions apply 1xxxb: The erase and program restrictions in bits 5:4 are sufficient DS C-page Microchip Technology Inc.

83 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (8 OF 16) Address Bit Address Data Comments 5DH 5EH 5FH A8 A12:A9 A15:A13 A19:A16 A23:A20 A30:A24 0FH 77H 38H Reserved = 1b Program Resume to Suspend Interval The device requires this typical amount of time to make progress on the program operation before allowing another suspend. Interval =500µs Program resume to suspend interval =(count+1)*64µs A12:A9= 7 =0111b Suspend in-progress program max latency Maximum time required by the flash device to suspend an in-progress program and be ready to accept another command which accesses the flash array. Max latency = 25µs program max latency =(count+1)*units units (00b:128ns, 01b:1µs, 10b:8µs, 11b:64µs) A17:A13= count = 24 = 11000b A19:A18 = 1µs =01b 0111b Suspend/Resume supported A31 0:supported 1:not supported JEDEC Flash Parameter Table: 13 th DWORD 60H A7:A0 30H Program Resume Instruction 61H A15:A8 B0H Program Suspend Instruction 62H A23:A16 30H Resume Instruction 63H A31:A24 B0H Suspend Instruction JEDEC Flash Parameter Table: 14 th DWORD 64H A1:A0 A7:A2 F7H Erase Resume to Suspend Interval The device requires this typical amount of time to make progress on the erase operation before allowing another suspend. Interval = 500µs Erase resume to suspend interval =(count+1)*64µs A23:A20= 7 =0111b Suspend in-progress erase max latency Maximum time required by the flash device to suspend an in-progress erase and be ready to accept another command which accesses the flash array. Max latency = 25µs Erase max latency =(count+1)*units units (00b:128ns, 01b:1µs, 10b:8µs, 11b:64µs) A28:A24= count = 24 = 11000b A30:A29 = 1µs =01b Reserved = 11b Status Register Polling Device Busy b: Use of legacy polling is supported by reading the status register with 05h instruction and checking WIP bit [0] (0=ready, 1=busy) Microchip Technology Inc. DS C-page 83

84 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (9 OF 16) Address Bit Address Data Comments 65H 66H A14:A8 A15 A22:A16 A23 A30:A24 A9H D5H Exit Deep Power-down to next operation delay 10 µs Delay = (count +1)*unit A12:A8 = count = 9 = 01001b A14:A13 units = 01b = 1µs Exit Power-down Instruction ABH = b A15=1b A22:A16= b Enter Power-down instruction B9H = b A23 = 1b A30:A24 = H 5CH Deep Power-down Supported A31 0:supported 1:not supported JEDEC Flash Parameter Table: 15 th DWORD 68H 69H 6AH A3:A0 A7:A4 A8 A9 A15:A10 A19:A16 A22:A20 29H C2H 5CH mode disable sequences Xxx1b: issue FF instruction 1xxxb: issue the Soft Reset 66/99 sequence mode enable sequences X_xx1xb: issue instruction 38h mode enable sequences A8 = mode supported 0:not supported 1:supported Mode Exit Method X1_xxxx:Mode Bit[7:0] Not= AXh 1x_xxxx Reserved = Mode Entry Method X1xxb: M[7:0]=AXh 1xxxb:Reserved =1 A23 HOLD and Reset Disable 0:feature is not supported 6BH A31:A24 FFH Reserved bits = 0xFF JEDEC Flash Parameter Table: 16 th DWORD 6C 6D Quad Enable Requirements (QER) 101b: Quad Enable is bit 1 of the configuration register. Volatile or Non-Volatile Register and Write Enable Instructions for Status Register 1 Xx1_xxxxb:Status Register 1 contains a mix of volatile and non-volatile A6:A0 F0H bits. The 06h instruction is used to enable writing to the register. X1x_xxxxb: Reserved = 1 1xx_xxxxb: Reserved = 1 A7 Reserved =1b A13:A8 A15:A14 30H Soft Reset and Rescue Sequence Support X1_xxxxb: reset enable instruction 66h is issued followed by reset instruction 99h. 1x_xxxxb: exit mode is required prior to other reset sequences. Exit 4-Byte Addressing Not supported DS C-page Microchip Technology Inc.

85 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (10 OF 16) Address Bit Address Data Comments 6E A23:A16 C0H 6F A31:A24 80H JEDEC Sector Map Parameter Table Exit 4-Byte Addressing Not supported A21:A14= b A23 and A22 are Reserved bits which are = 1 Enter 4-Byte Addressing Not supported 1xxx_xxxx: Reserved = 1 100H A7:A0 FFH Sector Map A7:A2=Reserved=111111b A1=Descriptor Type = Map=1b A0=Last map = 1b 101H A15:A8 00H Configuration ID = 00h 102H A23:A16 04H Region Count = 5 Regions 103H A31:A24 FFH Reserved = FFh 104H A7:A0 F3H 105H A15:A8 7FH 106H A23:A16 00H 107H A31:A24 00H 108H A7:A0 F5H 109H A15:A8 7FH 10AH A23:A16 00H 10BH A31:A24 00H 10CH A7:A0 F9H 10DH A15:A8 FFH 10EH A23:A16 0DH 10FH A31:A24 00H 110H A7:A0 F5H Region 0 supports 4 KByte erase and 8 KByte erase A3:A0=0011b A7:A4=Reserved=1111b Region 0 Size 4 * 8 KBytes = 32 KBytes Count=32 KBytes/256 bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh Region 1 supports 4 KByte erase and 32 KByte erase A3:A0 = 0101b A7:A4=Reserved = 1111b Region 1 size 1 * 32 KBytes = 32 KBytes Count=32 KBytes/256 bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh Region 2 supports 4 KByte erase and 64 KByte erase A3:A0 = 1001b A7:A4=Reserved = 1111b Region 2 size 14 * 64 KBytes = 896 KBytes Count=896 KBytes/256 bytes= 3584 Value = count -1 =3583 A31:A8 = 000DFFh Region 3 supports 4 KByte erase and 32 KByte erase A3:A0 = 0101b A7:A4=Reserved = 1111b Microchip Technology Inc. DS C-page 85

86 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (11 OF 16) Address Bit Address Data Comments 111H A15:A8 7FH Region 3 size 1 * 32 KBytes = 32 KBytes Count=32 KBytes/256 bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh 112H A23:A16 00H 113H A31:A24 00H 114H A7:A0 F3H Region 4 supports 4 KByte erase and 8 KByte erase A3:A0=0011b A7:A4=Reserved=1111b 115H A15:A8 7FH Region 4 Size 4 * 8 KBytes = 32 KBytes Count=32 KBytes/256 bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh 116H A23:A16 00H 117H A31:A24 00H SST26WF080B/080BA (Vendor) Parameter Table SST26WF080B/080BA Identification 200H A7:A0 BFH Manufacturer ID 201H A15:A8 26H Memory Type 202H A23:A16 58H Device ID SST26WF080B/080BA=58H 203H A31:A24 FFH Reserved. Bits default to all 1 s. SST26WF080B/080BA Interface 204H A2:A0 A3 A6:A4 A7 B9H Interfaces Supported 000: SPI only 001: Power up default is SPI; Quad can be enabled/disabled 010: Reserved : : 111: Reserved Supports Enable Quad 0: not supported 1: supported Supports Hold#/Reset# Function 000: Hold# 001: Reset# 010: HOLD/Reset# 011: Hold# & I/O when in SQI(4-4-4), or Read Supports Software Reset 0: not supported 1: supported DS C-page Microchip Technology Inc.

87 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (12 OF 16) Address Bit Address Data Comments 205H 206H Supports Quad Reset A8 0: not supported 1: supported A10:A9 Reserved. Bits default to all 1 s A13:A11 A14 A15 A16 A17 A18 DFH FDH Byte-Program or Page-Program (256 Bytes) 011: Byte Program/Page Program in SPI and Quad Page Program once Quad is enabled Program-Erase Suspend Supported 0: Not Supported 1: Program/Erase Suspend Supported Deep Power-Down Mode Supported 0: Not Supported 1: Deep Power-Down Mode Supported OTP Capable (Security ID) Supported 0: not supported 1: supported Supports Block Group Protect 0: not supported 1: supported Supports Independent Block Protect 0: not supported 1: supported Supports Independent non Volatile Lock (Block or Sector A19 becomes OTP) 0: not supported 1: supported A23:A20 Reserved. Bits default to all 1 s. 207H A31:A24 FFH Reserved. Bits default to all 1 s. 208H A7:A0 65H V DD Minimum Supply Voltage 209H A15:A8 F1H 1.65V (F165H) 20AH A23:A16 95H V DD Maximum Supply Voltage 20BH A31:A24 F1H 1.95V (F195H) 20CH A7:A0 32H Typical time out for Byte-Program: 50 µs Typical time out for Byte Program is in µs. Represented by conversion of the actual time from the decimal to hexadecimal number. 20DH A15:A8 FFH Reserved. Bits default to all 1 s. 20EH A23:A16 0AH Typical time out for page program: 1.0ms (xxh*(0.1ms)) 20FH A31:A24 12H 210H A7:A0 23H Typical time out for Sector-Erase/Block-Erase: 18 ms Typical time out for Sector/Block-Erase is in ms. Represented by conversion of the actual time from the decimal to hexadecimal number. Typical time out for Chip-Erase: 35 ms Typical time out for Chip-Erase is in ms. Represented by conversion of the actual time from the decimal to hexadecimal number. 211H A15:A8 46H Max. time out for Byte-Program: 70 µs Typical time out for Byte Program is in µs. Represented by conversion of the actual time from the decimal to hexadecimal number. 212H A23:A16 FFH Reserved. Bits default to all 1 s Microchip Technology Inc. DS C-page 87

88 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (13 OF 16) Address Bit Address Data Comments 213H A31:A24 0FH 214H A7:A0 19H 215H A15:A8 32H 216H A23:A16 0FH 217H A31:A24 19H 218H A23:A16 19H 219H A31:A24 03H Max time out for Page-Program: 1.5ms. Typical time out for Page Program in xxh * (0.1ms) ms Max. time out for Sector Erase/Block Erase: 25ms. Max time out for Sector/Block Erase in ms Max. time out for Chip Erase: 50ms. Max time out for Chip Erase in ms. Max. time out for Program Security ID: 1.5 ms Max time out for Program Security ID in xxh*(0.1ms) ms Max. time for Write-Protection Enable Latency: 25 ms Max time out for ms. Represented by conversion of the actual time from the decimal to hexadecimal number. Max. time Write-Suspend Latency: 25 µs Max time out for Write-Suspend Latency is in µs. Represented by conversion of the actual time from the decimal to hexadecimal number.) Max. time to Deep Power-Down: 3 µs 3 µs = 03H 21AH A23:A16 0AH Max. time out from Deep Power-Down mode to Standby mode: 10 µs. 10 µs = 0AH 21BH A31:A24 FFH Reserved. Bits default to all 1 s. 21CH A23:A16 FFH Reserved. Bits default to all 1 s. 21DH A31:A24 FFH Reserved. Bits default to all 1 s. 21EH A23:A16 FFH Reserved. Bits default to all 1 s. 21FH A31:A24 FFH Reserved. Bits default to all 1 s. Supported Instructions 220H A7:A0 00H No Operation 221H A15:A8 66H Reset Enable 222H A23:A16 99H Reset Memory 223H A31:A24 38H Enable Quad I/O 224H A7:A0 FFH Reset Quad I/O 225H A15:A8 05H Read Status Register 226H A23:A16 01H Write Status Register 227H A31:A24 35H Read Configuration Register 228H A7:A0 06H Write Enable 229H A15:A8 04H Write Disable 22AH A23:A16 02H Byte Program or Page Program 22BH A31:A24 32H SPI Quad Page Program 22CH A7:A0 B0H Suspends Program/Erase 22DH A15:A8 30H Resumes Program/Erase 22EH A23:A16 72H Read Block-Protection register 22FH A31:A24 42H Write Block Protection Register 230H A7:A0 8DH Lock Down Block Protection Register 231H A15:A8 E8H Non-Volatile Write-Lock Down Register 232H A23:A16 98H Global Block Protection Unlock 233H A31:A24 88H Read Security ID 234H A7:A0 A5H Program User Security ID Area 235H A15:A8 85H Lockout Security ID Programming DS C-page Microchip Technology Inc.

89 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (14 OF 16) Address Bit Address Data Comments 236H A23:A16 C0H Set Burst Length 237H A31:A24 9FH JEDEC-ID 238H A7:A0 AFH Quad J-ID 239H A15:A8 5AH SFDP 23AH A23:A16 B9H Deep Power-Down Mode 23BH A31:A24 ABH Release Deep Power-Down Mode 23CH A4:A0 06H (1-4-4) SPI nb Burst with Wrap Number of Wait states (dummy clocks) needed before valid output 00110b: 6 clocks of dummy cycle A7:A5 (1-4-4) SPI nb Burst with Wrap Number of Mode Bits 000b: Set Mode bits are not supported 23DH A15:A8 ECH (1-4-4) SPI nb Burst with Wrap Opcode 23EH A20:A16 06H (4-4-4) SQI nb Burst with Wrap Number of Wait states (dummy clocks) needed before valid output 00110b: 6 clocks of dummy cycle A23:A21 (4-4-4) SQI nb Burst with Wrap Number of Mode Bits 000b: Set Mode bits are not supported 23FH A31:A24 0CH (4-4-4) SQI nb Burst with Wrap Opcode 240H A4:A0 00H (1-1-1) Read Memory Number of Wait states (dummy clocks) needed before valid output 00000b: Wait states/dummy clocks are not supported. A7:A5 (1-1-1) Read Memory Number of Mode Bits 000b: Mode bits are not supported, 241H A15:A8 03H (1-1-1) Read Memory Opcode 242H A20:A16 08H (1-1-1) Read Memory at Higher Speed Number of Wait states (dummy clocks) needed before valid output 01000: 8 clocks (8 bits) of dummy cycle A23:A21 (1-1-1) Read Memory at Higher Speed Number of Mode Bits 000b: Mode bits are not supported, 243H A31:A24 0BH (1-1-1) Read Memory at Higher Speed Opcode 244H A7:A0 FFH Reserved. Bits default to all 1 s. 245H A15:A8 FFH Reserved. Bits default to all 1 s. 246H A23:A16 FFH Reserved. Bits default to all 1 s. 247H A31:A24 FFH Reserved. Bits default to all 1 s. Security ID 248H A7:A0 FFH Security ID size in bytes Example: If the size is 2 KBytes, this field would be 07FFH 249H A15:A8 07H Security ID Range Unique ID (Pre-programmed at factory) 0000H H User Programmable 0008H - 07FFH 24AH A23:A16 FFH Reserved. Bits default to all 1 s. 24BH A31:A24 FFH Reserved. Bits default to all 1 s Microchip Technology Inc. DS C-page 89

90 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (15 OF 16) Address Bit Address Data Comments Memory Organization/Block Protection Bit Mapping 1 24CH A7:A0 02H 24DH A15:A8 02H 24EH A23:A16 FFH 24FH A31:A24 06H 250H A7:A0 03H 251H A15:A8 00H 252H A23:A16 FDH 253H A31:A24 FDH 254H A7:A0 04H 255H A15:A8 04H 256H A23:A16 00H 257H A31:A24 FCH 258H A7:A0 03H 259H A15:A8 00H Section 1: Sector Type Number: Sector type in JEDEC Parameter Table (bottom, 8 KByte) Section 1 Number of Sectors Four of 8KB blocks (2 n ) Section 1 Block Protection Bit Start ((2 m ) +1)+ c, c=ffh or -1, m= 4 for 8 Mb Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 1 (bottom) Block Protection Bit End ((2 m ) +1)+ c, c=06h or 6, m= 4 for 8 Mb Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 2: Sector Type Number Sector type in JEDEC Parameter Table (32 KByte Block) Section 2 Number of Sectors One of 32 KByte Block (2 n, n=0) Section 2 Block Protection Bit Start ((2 m ) +1)+ c, c=fdh or -3, m= 4 for 8 Mb The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 2 Block Protection Bit End ((2 m ) +1)+ c, c=fdh or -3, m= 4 for 8 Mb The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 3: Sector Type Number Sector type in JEDEC Parameter Table (64 KByte Block) Section 3 Number of Sectors 14 of 64 KByte Block (2 n -2, n= 4) Section 3 Block Protection Bit Start Section 3 Block Protection Bit starts at 00H Section 3 Block Protection Bit End ((2 m ) +1)+ c, c=fch or -4, m= 4 for 8 Mb Section 4: Sector Type Number Sector type in JEDEC Parameter Table (32 KByte Block) Section 4 Number of Sectors One of 32KByte Block (2 n, n=0) DS C-page Microchip Technology Inc.

91 TABLE 11-2: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) SST26WF080B/080BA (CONTINUED) (16 OF 16) Address Bit Address Data Comments 25AH A23:A16 FEH 25BH A31:A24 FEH 25CH A7:A0 02H 25DH A15:A8 02H 25EH A23:A16 07H 25FH A31:A24 0EH Section 4 Block Protection Bit Start ((2 m ) +1)+ c, c=feh or -2, m= 4 for 8 Mb The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 4 Block Protection Bit End ((2 m ) +1)+ c, c=feh or -2, m= 4 for 8 Mb The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 5 Sector Type Number: Sector type in JEDEC Parameter Table (top, 8 KByte) Section 5 Number of Sectors Four of 8 KByte blocks (2 n ) 1. See Mapping Guidance Details for more detailed mapping information Section 5 Block Protection Bit Start ((2 m ) +1)+ c, c=07h or 7, m= 4 for 8 Mb Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative. Section 5 (Top) Block Protection Bit End (((2 m ) +1)+ c, c=0eh or 15, m= 4 for 8 Mb, Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one then the number is less than zero or negative Mapping Guidance Details The SFDP Memory Organization/Block Protection Bit Mapping defines the memory organization including uniform sector/block sizes and different contiguous sectors/blocks sizes. In addition, this bit defines the number of these uniform and different sectors/blocks from address H to the full range of Memory and the associated Block Locking Register bits of each sector/block. Each major Section is defined as follows: TABLE 11-3: Major Section X SECTION DEFINITION Section X: Sector Type Number Section X: Number of Sectors Section X: Block-Protection Register Bit Start Location Section X: Block-Protection Register Bit End Location A Major Section consists of Sector Type Number, Number of Sector of this type, and the Block-Protection Bit Start/End locations. This is tied directly to JEDEC Flash Parameter Table Sector Size Type (in 7th DWORD and 8th DWORD section). Note that the contiguous 4KByte Sectors across the full memory range are not included on this section because they are not defined in the JEDEC Flash Parameter Table Sector Size Type section. Only the sectors/blocks that are dependently tied with the Block-Protection Register bits are defined. A major section is a partition of contiguous same-size sectors/blocks. There will be several Major Sections as Microchip Technology Inc. DS C-page 91

92 you dissect across memory from h to the full range. Similar sector/block size that re-appear may be defined as a different Major Section Sector Type Number Sector Type Number is the sector/block size typed defined in JEDEC Flash Parameter Table: SFDP address locations 4CH, 4EH, 50H and 52H. Sector Type 1, which is represented by 01H, is located at address 4CH. Sector Type 2, which is represented by 02H, is located at address location 4EH. Sector Type 3, which is represented by 03H, is located at address location 50H. Sector Type 4, represented by 04H, is located at address location 52H. Contiguous Same Sector Type # Size can re-emerge across the memory range and this Sector Type # will indicate that it is a separate/independent Major Section from the previous contiguous sectors/blocks Number of Sectors Number of Sectors represents the number of contiguous sectors/blocks with similar size. A formula calculates the contiguous sectors/blocks with similar size. Given the sector/block size, type, and the number of sectors, the address range of these sectors/blocks can be determined along with specific Block Locking Register bits that control the read/write protection of each sectors/blocks Block-Protection Register Bit Start Location (BPSL) Block-Protection Register Bit Start Location (BPSL) designates the start bit location in the Block-Protection Register where the first sector/block of this Major Section begins. If the value of BPSL is 00H, this location is the 0 bit location. If the value is other than 0, then this value is a constant value adder (c) for a given formula, (2 m + 1) + (c). See Memory Configuration. From the initial location, there will be a bit location for every increment by 1 until it reaches the Block Protection Register Bit End Location (BPEL). This number range from BPSL to BPEL will correspond to, and be equal to, the number of sectors/blocks on this Major Section Block Protection Register Bit End Location (BPEL) Block Protection Register Bit End Location designates the end bit location in the Block Protection Register bit where the last sector/block of this Major Section ends. The value in this field is a constant value adder (c) for a given formula or equation, (2 m + 1) + (c). See Memory Configuration 11.6 Memory Configuration For the SST26WF040B/040BA and SST26WF080B/ 080BA family, the memory configuration is setup with different contiguous block sizes from bottom to the top of the memory. For example, starting from bottom of memory it has four 8KByte blocks, one 32KByte block, x number of 64KByte blocks depending on memory size, then one 32KByte block, and four 8KByte block on the top of memory. See Table TABLE 11-4: MEMORY BLOCK DIAGRAM REPRESENTATION 8 KByte Bottom Block Section 1: Sector Type Number (from H) Section 1: Number of Sectors Section 1: Block-Protection Register Bit Start Location Section 1: Block-Protection Register Bit End Location 32 KByte Section 2: Sector Type Number Section 2: Number of Sectors Section 2: Block-Protection Register Bit Start Location Section 2: Block-Protection Register Bit End Location 64 KByte Section 3: Sector Type Number Section 3: Number of Sectors Section 3: Block-Protection Register Bit Start Location Section 3: Block-Protection Register Bit End Location 32 KByte Section 4: Sector Type Number Section 4: Number of Sectors Section 4: Block-Protection Register Bit Start Location Section 4: Block-Protection Register Bit End Location DS C-page Microchip Technology Inc.

93 TABLE 11-4: MEMORY BLOCK DIAGRAM REPRESENTATION 8 KByte (Top Block) Section 5: Sector Type Number Section 5: Number of Sectors Section 5: Block-Protection Register Bit Start Location Section 5: Block-Protection Register Bit End Location Classifying these sector/block sizes via the Sector Type derived from JEDEC Flash Parameter Table: SFDP address locations 4EH, 50H, and 52H is as follows: 8 KByte Blocks are classified as Sector Type 2 (@4EH of SFDP) 32 KByte Blocks are classified as Sector Type 3 (@50H of SFDP) 64 KByte Blocks are classified as Sector Type 4 (@52H of SFDP) For the Number of Sectors associated with the contiguous sectors/blocks, a formula is used to determine the number of sectors/blocks of these Sector Types: 8KByte Block (Type 2) is calculated by 2 n. n is a byte. 32KByte Block (Type 3) is calculated by 2 n. n is a byte. 64KByte Block (Type 4) is calculated by (2m - 2). m can either be a 4, 5, 6, 7 or 8 depending on the memory size. This m field is going to be used for the 64KByte Block Section and will also be used for the Block Protection Register Bit Location formula. m will have a constant value for specific densities and is defined as: 8Mbit = 4 16Mbit = 5 32Mbit = 6 64Mbit = 7 128Mbit = 8 Block Protect Register Start/End Bits are mapped in the SFDP by using the formula (2 m + 1) + (c). m is a constant value that represents the different densities from 8Mbit to 128Mbit (used also in the formula calculating number of 64 KByte Blocks above). The values that are going to be placed in the Block Protection Bit Start/End field table are the constant value adder (c) in the formula and are represented in two s compliment except when the value is 00H. If the value is 00H, this location is the 0 bit location. If the value is other than 0, then this is a constant value adder (c) that will be used in the formula. The most significant (left most) bit indicates the sign of the integer; it is sometimes called the sign bit. If the sign bit is zero, then the number is greater than or equal to zero, or positive. If the sign bit is one, then the number is less than zero, or negative. See Table 11-5 for an example of this formula. TABLE 11-5: BPSL/BPEL EQUATION WITH ACTUAL CONSTANT ADDER DERIVED FROM THE FORMULA (2 M + 1) + (C) Block Size 8 Mbit to 128 Mbit Comments 8 KByte (Type 2) Bottom BPSL = (2 m + 1) + FFH BPEL = (2 m + 1) + 04H 32 KByte (Type3) BPSL = BPEL= (2 m + 1) + 0FDH 0FDH= -3 0FFH = -1; 06H = 6 Odd address bits are Read-Lock bit locations and even address bits are Write-Lock bit locations Microchip Technology Inc. DS C-page 93

94 TABLE 11-5: BPSL/BPEL EQUATION WITH ACTUAL CONSTANT ADDER DERIVED FROM THE FORMULA (2 M + 1) + (C) Block Size 8 Mbit to 128 Mbit Comments 64 KByte (Type 4) BPSL = 00H BPEL = (2 m + 1) + FCH 32 KByte (Type 3) BPSL = BPEL= (2 m + 1) + 0FEH 0FEH=-2 8 KByte (Type 2) Top BPSL = (2 m + 1) + 07H BPEL = (2 m + 1) + 0EH 00H is Block-Protection Register bit 0 location; 0FCH = -4 07H = 7; 0EH = 14 Odd address bits are Read-Lock bit locations and even address bits are Write-Lock bit locations. DS C-page Microchip Technology Inc.

95 Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company s quality system processes and procedures are for its PIC MCUs and dspic DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS == Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, chipkit, chipkit logo, CryptoMemory, CryptoRF, dspic, FlashFlex, flexpwr, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maxstylus, maxtouch, MediaLB, megaavr, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picopower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyavr, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mtouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dspicdem, dspicdem.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter- Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorbench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. 2017, Microchip Technology Incorporated, All Rights Reserved. ISBN: Microchip Technology Inc. DS C-page 95

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