Instruction content (2/2) Instruction content (1/2) The Instruction Set. Chapter 9. Each instruction must contain 4 basic pieces of information

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1 CS.216 Computer Architecture and Organization Chapter 9 The Instruction Set L/O/G/O Overview Much of the computer s architecture / organization is hidden from a HLL programmer In the abstract sense, the programmer should not care what the underlying architecture really is The instruction set is the boundary where the computer designer and the computer programmer can view the same machine Thus, an examination of the instruction set goes a long way to explaining the computer s CPU itself This section investigates the design of the instruction set and the impact of the set on the design of the overall computer system Readings: Chapters 10 and 11 Instruction content (1/2) Each instruction must contain 4 basic pieces of information Operation code: specifies the operation to be performed, expressed as a binary code Source operand references: operands required for the instruction are specified Result reference: where should the result of the operation be placed? Instruction content (2/2) Next instruction reference: how/whereisthenext instruction to be found In most cases, this is not explicitly stated in the instruction Next instruction is the one that logically follows the current one in the program (sequential / linear progression through the program)

2 Instruction types (1/2) An instruction set should be functionally complete Permit the user to formulate any high-level data processing task Five categories of instructions Arithmetic operations Logic operations Data movement (internal to the system) I/O (data movements between the computer and external devices) Control operations Addresses in an Instruction (1/8) In a typical arithmetic or logical instruction, 3 addresses are required -- 2 operands and a result These addresses can be explicitly given or implied by the instruction 3 address instructions Both operands and the destination for the result are explicitly contained in the instruction word Example: X =Y +Z Instruction types (2/2) Instruction sets have been designed with Small numbers of instructions (1) Hundreds of instructions Trend today is to use enough to get the job done well (more on this in the RISC/CISC discussions to come) Until the 1980s, the trend was to construct more and more complex instruction sets containing hundreds of instructions and variations Addresses in an Instruction (2/8) With memory speeds (due to caching) approaching the speed of the processor, this gives a high degree of flexibility to the compiler Avoid the hassles of keeping items in the register set -- use memory as one large set of registers This format is rarely used due to the length of addresses themselves and the resulting length of the instruction words

3 Addresses in an Instruction (3/8) 2 address instructions One of the addresses is used to specify both an operand and the result location Example: X =X +Y Very common in instruction sets 1 address instructions Two addresses are implied in the instruction Traditional accumulator-based operations Example: Acc = Acc + X Addresses in an Instruction (5/8) Trade off: Fewer addresses in the instruction results in More primitive instructions Less complex CPU Instructions with shorter length More total instructions in a program Longer, more complex programs Longer execution times Addresses in an Instruction (4/8) 0 address instructions All addresses are implied, as in register-based operations Example: TBA (transfer register B to A) Stack-based operations All operations are based on the use of a stack in memory to store operands Interact with the stack using push and pop operations Addresses in an Instruction (6/8) Consider Y = (A-B) / (C+D*E) 3 address 2 address

4 Addresses in an Instruction (7/8) Consider Y = (A-B) / (C+D*E) 1 address Endian Wars (1/3) Architects must specify how data is stored (its byte ordering) in memory and registers This leads to the endian wars Big endian Little endian Consider the hex value $ and how it is stored in memory starting at address $100 Big endian stores most significant byte in the lowest address: Addresses in an Instruction (8/8) 0 address Convert to postfix (reverse Polish) notation Y = AB-CDE*+/ PUSH A PUSH B SUB PUSH C PUSH D PUSH E MPY ADD DIV POP Y Endian Wars (2/3) Little endian stores the word in reverse: Observations: In storing several data items into a memory segment, each item will have the same address (big or little endian does not change this) Endianness does not effect the ordering of items in a data structure No general consensus as to which is best Little endian: Intel X86, Pentium, VAX Big endian: S370, Motorola 680x0, RISCs

5 Endian Wars (3/3) Instruction Formats (1/7) No real advantage in one style over the other Decision is based on supporting previous machines in many cases Biggest problems: Data transfers between machines of different endianness Must go though a format conversion process Manipulation of individual bytes (bits) of multibyte word The instruction format defines the layout of instruction word in terms of its constituent parts Most basic issue is the instruction length Longer instruction lengths permit more opcodes, addressing modes, addressing ranges, etc. Longer does not imply a significant increase in functionality, however Instruction lengths are equal to the basic memory transfer data size or a multiple of that size If the memory system retrieves 32 bit words, instructions should be 32 bits (or 64) Instruction Formats (2/7) PDP-8: 12-bit fixed length variable format Allocation of bits Tradeoff between number of opcodes supported (rich instruction set) and the power of the addressing capability

6 Instruction Formats (4/7) PDP-10: 36-bit fixed length fixed format Stressed orthogonality, completeness, and direct addressing Trade off ease of programming with increased H/W expense Figure 11.6 Instruction formats for the PDP-11 Instruction Formats (5/7) PDP-11: variable length variable format 16-bit word length minicomputer Variable length instructions to provide flexibility -- more opcodes and memory addressing modes Cost of the flexibility is a significant increase in the CPU complexity PowerPC format Figure 11.9 PowerPC instruction formats

7 Summary (2/2) Instruction format Size and amount allocated to different fields Fixed and variable formats Complexity Summary (1/2) In this section, we have looked at the instruction set of the machine Content types of information contained in them Functional completeness Addressing in instructions Number of addresses included and the impact on the program Addressing modes -- how is the effective address determined D o y o u h a v e a n y Question! L/O/G/O