Data Flow on a Queue Machine. Bruno R. Preiss. Copyright (c) 1987 by Bruno R. Preiss, P.Eng. All rights reserved.

Transcription

1 Dt Flow on Queue Mchine Bruno R. Preiss

2 2 Outline Genesis of dt-flow rchitectures Sttic vs. dynmic dt-flow rchitectures Pseudo-sttic dt-flow execution model Some dt-flow mchines Simple queue mchine Prioritized queue mchine Progrm decomposition Queue mchine processing element

3 3 Genesis of Dt Flow Dt-flow principles: synchrony nd functionlity x 1 = b b 2 4c ; x2 = 2 b b 2 4c 2 c b b 4 0 b 2 x 1 x

4 Sttic: 4 Dt-Flow Execution Models Progrm loded into memory in completed form before execution begins At most one instnce of n ctor cn be enbled Sme storge spce used for instructions nd dt Dynmic: Progrm nodes cn be instntited t run time Severl instnces of n ctor my be enbled Seprte storge spce used for instructions nd dt

5 5 b c d b c d tg p p p p p p dd 2 1 opernd slot opernd slot 5 mul 2 1 opernd slot opernd slot 9 div 2 0 opernd slot opernd slot dd 1 2:0 mul 1 4:0 div 0 instruction spce. b c d 0:0 context 0:1 context 2:1 context 4:1 context dt spce

6 6 Pseudo-sttic Dt Flow b c d b c d b c d dd 2 mul 4 div instruction spce... 0 opernd slot... 1 opernd slot 2 opernd slot... 3 opernd slot 4 opernd slot... 5 opernd slot context A dt spce opernd slot opernd slot opernd slot opernd slot opernd slot opernd slot context B Cn ssocite severl dt spces with one instruction spce Reentrncy ccomplished without code copying or tgged tokens

7 7 MIT Sttic Dt-Flow Mchine instruction memory sclr processors distribution network cell block cell block. cell block rbitrtion network PE 1 PE 2. PE n Sttic dt-flow mchine Pcket communiction bsed Networks re pipelined provide queueing 4 processor prototype built LAU System Architecture host control unit memory unit execution unit PE 1 PE... 2 PE n instruction queue Sttic dt-flow mchine Uses cyclic dt-flow grphs

8 8 Explicit externl instruction queue 32 processor prototype built

9 9 Mnchester Dt-Flow Architecture node store mtching store token queue processing unit PE 1 PE... 2 PE n switch host Dynmic dt-flow rchitecture Tgged tokens Circulr pipeline with token queue 15 processor prototype built MIT Dynmic Dt-Flow Architecture PE 1 witingmtching PE 2. n n network instruction memory instruction fetch PE n host structure memory service section Dynmic dt-flow rchitecture

10 Tgged tokens 10 Circulr pipeline with queueing in witing/mtching section

11 11 Simple Queue Mchine Uses first-in, first-out (FIFO) queue for the mnipultion of opernds nd results Its instructions implicitly reference n opernd queue Anlogous to stck mchine (c d) f b e Stck Queue instruction stck instruction queue sequence contents sequence contents fetch fetch c c fetch b b, fetch d c, d mul b fetch c, d, fetch c c, b fetch b c, d,, b fetch d d, c, b sub, b, c d sub c d, b fetch e, b, c d, e fetch e e, c d, b mul c d, e, b div (c d) (c d), b div b, e e dd (c d) (c d) b dd b e e store f store f

12 12 Generting Instruction Sequences for Simple Queue Mchine f b c d d level order conjugte b e c b c d d level order trversl c,d,,b,,e,,, c,d,,b,,e,,, e in-order trversl LEMMA: Level-order trversl of expression prse tree gives queue mchine instruction sequence Time complexity of level order conjugtion is O(N) Spce complexity of level order conjugtion is O(N)

13 13 Pipelined Execution: Stck vs. Queue opernds ALU resultsopernds ALU results queue memory stck memory Cse 1: Non-overlpped opernd fetch/execute Cse 2: Overlpped opernd fetch/execute Speed up StckMchineCycles = QueueMchineCycles nodes in number prse tree of trees cse 1 cse two-stge pipelined ALU Speed up StckMchineCycles = QueueMchineCycles pipeline stges ssumption 1 ssumption nodes in prse tree

14 14 Prioritized Queue Mchine Assign priority to the result of ech opertion Plce result in queue t position determined from priority d b (b)c Prioritized Queue Mchine instruction result queue sequence priorities fetch 0,2, ε, fetch b 1, b, plus 1,2, b, b fetch c 3, b, b, c div 2 b, c, b mul 1, (b)c b dd 0 (b)c b store d b / c c / b b d LEMMA: Acyclic dt-flow grphs generte vlid prioritized queue mchine instruction sequences

15 15 Dynmic Dt-Flow Grph Splicing Bsed on two concepts: chnnels nd contexts Chnnel: Unidirectionl communiction pth between two contexts Context: A process tht evlutes n cyclic dt-flow grph Stte of context: An instruction sequence (nd PC) nd n opernd queue Conditionl execution, itertion, subroutine clls implemented by instructions for context cretion (fork) nd intercontext communiction (send (!) nd receive (?)) context A context B B.in x b.in pointer to instruction sequence!? fork. x.in.out

16 16 Prtitioning Progrms Gol: exploit potentil prllelism Use cyclic dt-flow grph s the bsic grnule of computtion Grnule size trde-off: Smll contexts excessive intercontext communiction nd context genertion overhed Lrge contexts cnnot exploit intrcontext prllelism Context-bsed prtition is compromise between conventionl dt-flow nd tsk- or process-bsed prllelism (Ad, Concurrent Euclid) Conventionl dt-flow rchitectures ttempt to detect nd exploit opertor-level prllelism t execution time (costly nd inefficient) Tsk- or process-bsed pproch requires progrmmer to explicitly prtition progrms into grnules of computtion nd to code communictions between tsks Approch: Prtition progrms (utomticlly) into grnules of computtion more complex thn single instructions, yet less complex thn processor tsk, nd to utomticlly exploit prllelism between contexts OCCAM compiler

17 17 Queue Mchine Processing Element virtul queue rer. queue implementtion in physicl memory pge. front window registers presence bits front. rer k QP front. pge bse pge offset direction of incresing ddresses QP QP: queue pointer register Allocte pge of memory for queue of ech context Use window registers s queue cche Presence bits indicte vlidity of register contents

18 18 Queue Mchine Processing Element Architecture from dt bus MDR1 MDR2 0 A B from IR ALUOP X ALU Y R 0 -R 27 (dul ported) PC PC2 IR to control logic Z 4 from QP MAR to NAR to ddress bus MDR0 to dt bus

19 19 Queue Mchine Assembly Lnguge Syntx: opcode{}[src 1 [,src 2 ]][:dst 1 [,dst 2 ]] d b (b)c b c d fetch #: r0, r2 fetch #b: rf b plus r0,r1: r1, r2 b b fetch #c: f3 div r0,r1: r2 mul r0,r1: r1 plus r0,r1: r0 store #d,r0 b b c b c b (b)c b d

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